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| to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products are classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product depends on the product?s quality grade, as indicated below. you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application categorized as ?specific? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intended where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electronics data sheets or data books, etc. ?standard?: computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. ?high quality?: transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specifically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of renes as electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this document or renesas electronics products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics. h8/3008 hardware manual 16 users manual rev.4.00 2007.08 renesas 16-bit single-chip microcomputer h8 family/h8/300h series h8/3008 hd6413008f hd6413008te hd6413008vf hd6413008vte rev.4.00 aug. 20, 2007 page ii of xliv rej09b0395-0400 1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas products for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor g rants any license to any intellectual property ri g hts or any other ri g hts of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for dama g es or infrin g ement of any intellectual property or other ri g hts arisin g out of the use of any information in this document, includin g , but not limited to, product data, dia g rams, charts, pro g rams, al g orithms, and application circuit examples. 3. you should not use the products or the technolo g y described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exportin g the products or technolo g y described herein, you should follow the applicable export control laws and re g ulations, and procedures required by such laws and re g ulations. 4. all information included in this document such as product data, dia g rams, charts, pro g rams, al g orithms, and application circuit examples, is current as of the date this document is issued. such information, however, is subject to chan g e without any prior notice. before purchasin g or usin g any renesas products listed in this document, please confirm the latest product information with a renesas sales office. also, please pay re g ular and careful attention to additional and different information to be disclosed by renesas such as that disclosed throu g h our website. (http://www.renesas.com ) 5. renesas has used reasonable care in compilin g the information included in this document, but renesas assumes no liability whatsoever for any dama g es incurred as a result of errors or omissions in the information included in this document. 6. when usin g or otherwise relyin g on the information in this document, you should evaluate the information in li g ht of the total system before decidin g about the applicability of such information to the intended application. renesas makes no representations, warranties or g uaranties re g ardin g the suitability of its products for any particular application and specifically disclaims any liability arisin g out of the application and use of the information in this document or renesas products. 7. with the exception of products specified by renesas as suitable for automobile applications, renesas products are not desi g ned, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially hi g h quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. if you are considerin g the use of our products for such purposes, please contact a renesas sales office beforehand. renesas shall have no liability for dama g es arisin g out of the uses set forth above. 8. notwithstandin g the precedin g para g raph, you should not use renesas products for the purposes listed below: (1) artificial life support devices or systems (2) sur g ical implantations (3) healthcare intervention (e. g ., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life renesas shall have no liability for dama g es arisin g out of the uses set forth in the above and purchasers who elect to use renesas products in any of the fore g oin g applications shall indemnify and hold harmless renesas technolo g y corp., its affiliated companies and their officers, directors, and employees a g ainst any and all dama g es arisin g out of such applications. 9. you should use the products described herein within the ran g e specified by renesas, especially with respect to the maximum ratin g , operatin g supply volta g e ran g e, movement power volta g e ran g e, heat radiation characteristics, installation and other product characteristics. renesas shall have no liability for malfunctions or dama g es arisin g out of the use of renesas products beyond such specified ran g es. 10. althou g h renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to g uard a g ainst the possibility of physical injury, and injury or dama g e caused by fire in the event of the failure of a renesas product, such as safety desi g n for hardware and software includin g but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for a g in g de g radation or any other applicable measures. amon g others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowin g by infants and small children is very hi g h. you should implement safety measures so that renesas products may not be easily detached from your products. renesas shall have no liability for dama g es arisin g out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from renesas. 13. please contact a renesas sales office if you have any questions re g ardin g the information contained in this document, renesas semiconductor products, or if you have any other inquiries. notes re g ardin g these materials rev.4.00 aug. 20, 2007, page iii of xliv rej09b0395-0400 general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directions given under handling of unused pins in the manual. ? the input pins of cmos products are generally in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the possible future expansion of functions. do not access these addresses; the correct operation of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during program execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different type numbers, implement a system-evaluation test for each of the products. rev.4.00 aug. 20, 2007 page iv of xliv rej09b0395-0400 rev.4.00 aug. 20, 2007, page v of xliv rej09b0395-0400 preface the h8/3008 is a high-performan ce single-chip microcomputer that incorporates the internal 32-bit h8/300h cpu and is also equipped with peripheral functions necessary for configuring a user system. the h8/3008 is built in with a variety of peripheral functions such as rom, ram, 16-bit timer, 8-bit timer, programmable timing pattern controller (tpc), watchdog timer (wdt), serial communication interface (sci), d/a conve rter, a/d converter and i/o ports. target readers: this manual is designed for use by peop le who design application systems using the h8/3008. to use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is required. purpose: this manual provides the information of the hardware functions and electrical characteristics of the h8/3008. the h8/300h series programming manual contains detailed information of executable instructions. please read the programming manual together with this manual. how to use the book: ? to understand general functions read the manual from the beginning. the manual explains the cpu, system control functions, peripheral functions and electrical characteristics in that order. ? to understanding cpu functions refer to the separate h8/300h series programming manual. ? to see the detailed functions of registers with known names refer to appendix b ?internal i/o registers? for the summary of addresses, bit description and initialization. explanatory note: bit sequence: upper bit at left, and lower bit at right list of related documents: the latest documents are available on our web site. please make sure that you have the latest version. http://www.renesas.com/ rev.4.00 aug. 20, 2007 page vi of xliv rej09b0395-0400 user manual for h8/3008 document title document no. h8/3008 hardware manual this manual h8/300h series software manual rej09b0213-0300 user manual for development tools document title document no. c/c++ compiler, assembler, optimizing linkage editor user?s manual rej10b0058-0100h h8s, h8/300 series simulator/debugger user?s manual rej10b0211-0300 high-performance embedded workshop user?s manual rej10j1554-0100 h8s, h8/300 series high-performance embedded workshop, high-performance debugging interface user?s manual ade-702-231 application note document title document no. h8/300h for cpu application note ade-502-033 h8/300h on-chip supporting modules application note rej05b0522-0300 h8/300h technical q&a rej05b0521-0200 rev.4.00 aug. 20, 2007, page vii of xliv rej09b0395-0400 main revisions for this edition item page revision (see manual for details) all ? company name and brand names amended (before) hitachi, ltd. (after) renesas technology corp. 1.1 overview 1 description amended four mcu operating modes offer a choice of bus width and address space size. the modes (modes 1 to 4) include four expanded modes. 1.2 block diagram figure 1.1 block diagram 5 figure amended a 20 /tiocb 2 /tp 7 /pa 7 a 21 /tioca 2 /tp 6 /pa 6 a 22 /tiocb 1 /tp 5 /pa 5 a 23 /tioca 1 /tp 4 /pa 4 tclkd/tiocb 0 /tp 3 /pa 3 tclkc/tioca 0 /tp 2 /pa 2 tclkb/tp 1 /pa 1 tclka/tp 0 /pa 0 port a tp 15 /pb 7 tp 14 /pb 6 tp 13 /pb 5 tp 12 /pb 4 cs 4 /tmio 3 /tp 11 /pb 3 cs 5 /tmo 2 /tp 10 /pb 2 cs 6 /tmio 1 /tp 9 /pb 1 cs 7 /tmo 0 /tp 8 /pb 0 port b 1.3.1 pin arrangement table 1.2 comparison of h8/3008 pin arrangements 6 table amended h8/3062 f-ztat b-mask version 8.2.10 timer i/o control register (tior) bits 6 to 4?i/o control b2 to b0 (iob2 to iob0) 203 table amended bit 6 iob2 bit 5 iob1 bit 4 iob0 function 1 0 0 1 1 0 grb is an input capture re g ister 1 bits 2 to 0?i/o control a2 to a0 (ioa2 to ioa0) table amended bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 function 1 0 0 1 gra is an input capture re g ister 1 0 1 rev.4.00 aug. 20, 2007 page viii of xliv rej09b0395-0400 item page revision (see manual for details) 9.4.1 8tcnt count timing figure 9.8 count timing for internal clock input 261 figure amended 8tcnt n ? 1 n n + 1 internal clock 8tcnt input clock figure 9.9 count timing for external clock input (both-edge detection) 262 figure amended 8tcnt n ? 1 n n + 1 external clock input 8tcnt input clock 9.4.2 compare match timing figure 9.11 timing of clear by compare match 263 figure amended n h'00 8tcnt compare match si g nal figure 9.12 timing of clear by input capture figure amended input capture si g nal input capture input 8tcnt n h'00 rev.4.00 aug. 20, 2007, page ix of xliv rej09b0395-0400 item page revision (see manual for details) 9.4.3 input capture signal timing figure 9.13 timing of input capture input signal 264 figure amended input capture si g nal input capture input 8tcnt n tcorb n 9.4.4 timing of status flag setting figure 9.14 cmf flag setting timing when compare match occurs figure amended cmf compare match si g nal 8tcnt n n + 1 n tcor figure 9.15 cmfb flag setting timing when input capture occurs 265 figure amended cmfb input capture si g nal 8tcnt n n tcorb figure 9.16 timing of ovf setting figure amended ovf overflow si g nal 8tcnt h'ff h'00 rev.4.00 aug. 20, 2007 page x of xliv rej09b0395-0400 item page revision (see manual for details) 9.4.5 operation with cascaded connection compare match count mode 267 description amended ? channels 0 and 1: when bits cks2 to cks0 are set to (100) in 8tcr1, 8tcnt1 counts channel 0 compare match a events. channels 0 and 1 are controlled independently. cmf flag setting, interrupt generation, tmo pin output, counter clearing, and so on, is in accordance with the settings for each channel. note: when bit ice = 1 in 8tcsr1, the compare match register function of tcorb0 in channel 0 cannot be used. ? channels 2 and 3: when bits cks2 to cks0 are set to (100) in 8tcr3, 8tcnt3 counts channel 2 compare match a events. channels 2 and 3 are controlled independently. cmf flag setting, interrupt generation, tmo pin output, counter clearing, and so on, is in accordance with the settings for each channel. note: when bit ice = 1 in 8tcsr3, the compare match register function of tcorb2 in channel 2 cannot be used. 9.7.1 contention between 8tcnt write and clear figure 9.18 contention between 8tcnt write and clear 272 figure amended address bus 8tcnt address internal write si g nal counter clear si g nal 8tcnt n h'00 t 1 t 3 t 2 8tcnt write cycle rev.4.00 aug. 20, 2007, page xi of xliv rej09b0395-0400 item page revision (see manual for details) 9.7.2 contention between 8tcnt write and increment figure 9.19 contention between 8tcnt write and increment 273 figure amended address bus 8 tcnt address internal write si g nal 8tcnt input clock 8tcnt nm t 1 t 3 t 2 8tcnt write cycle 8tcnt write data 9.7.3 contention between tcor write and compare match figure 9.20 contention between tcor write and compare match 274 figure amended address bus tcor address internal write si g nal 8tcnt tcor nm t 1 t 3 t 2 tcor write cycle tcor write data n n + 1 compare match si g nal inhibited rev.4.00 aug. 20, 2007 page xii of xliv rej09b0395-0400 item page revision (see manual for details) 9.7.4 contention between tcor read and input capture figure 9.21 contention between tcor read and input capture 275 figure amended address bus tcorb address internal read si g nal input capture si g nal tcorb nm t 1 t 3 t 2 tcorb read cycle internal data bus n 9.7.5 contention between counter clearing by input capture and counter increment figure 9.22 contention between counter clearing by input capture and counter increment 276 figure amended counter clear si g nal 8tcnt internal clock 8tcnt n x h'00 input capture si g nal tcorb n rev.4.00 aug. 20, 2007, page xiii of xliv rej09b0395-0400 item page revision (see manual for details) 9.7.6 contention between tcor write and input capture figure 9.23 contention between tcor write and input capture 277 figure amended address bus tcor address internal write si g nal input capture si g nal 8tcnt m t 1 t 3 t 2 tcor write cycle tcor m x 9.7.7 contention between 8tcnt byte write and increment in 16-bit count mode (cascaded connection) 278 description amended if an increment pulse occurs in the t 2 or t 3 state of an 8tcnt byte write cycle in 16-bit count mode, the counter write takes priority and the byte data for which the write was performed is not incremented. the byte data for which a write was not performed is incremented. figure 9.24 shows the timing when an increment pulse occurs in the t 2 state of a byte write to 8tcnt (upper byte). if an increment pulse occurs in the t 2 state, on the other hand, the increment takes priority. figure 9.24 contention between 8tcnt byte write and increment in 16-bit count mode figure amended address bus 8tcnth address internal write si g nal 8tcnt input clock 8tcnt (upper byte) n 8tcnt write data t 1 t 3 t 2 8tcnt (upper byte) byte write cycle 8tcnt (lower byte) x + 1 n + 1 x rev.4.00 aug. 20, 2007 page xiv of xliv rej09b0395-0400 item page revision (see manual for details) 12.3.2 operation in asynchronous mode figure 12.4 sample flowchart for sci initialization 356 figure amended and note added (4) wait for at least the interval required to transmit or receive one bit, then set the te or re bit to 1 in scr * . set the rie, tie, teie, and mpie bits as necessary. setting the te or re bit enables the sci to use the txd or rxd pin. note: * in simultaneous transmitting and receiving, the te and re bits should be cleared to 0 or set to 1 simultaneously. 13.3.5 clock table 13.5 bit rates (bits/s) for various brr settings (when n = 0) 396 table amended (mhz) n 18.00 20.00 25.00 0 24193.5 26881.7 33602.2 1 12096.8 13440.9 16801.1 2 8064.5 8960.6 11200.7 table 13.6 brr settings for typical bit rates (bits/s) (when n = 0) 397 table amended (mhz) 18.00 20.00 25.00 bit/s n error n error n error 9600 2 15.99 2 6.66 3 12.49 18.4.3 selection of waiting time for exit from software standby mode table 18.3 clock frequency and waiting time for clock to settle 466 table amended div1 div0 sts2 sts1 sts0 waiting time 6 mhz 4 mhz 2 mhz 1mhz 0 1 0 0 0 8192 states 2.7 4.1 8.2 * 0 0 1 16384 states 5.5 8.2 * 16.4 0 1 0 32768 states 10.9 * 16.4 32.8 0 1 1 65536 states 21.8 32.8 65.5 1 0 0 131072 states 43.7 65.5 131.1 1 0 1 262144 states 87.4 131.1 262.1 1 1 0 1024 states 0.34 0.51 1.0 1 1 1 ille g al settin g unit ms 16.4 * 32.8 65.5 131.1 262.1 524.3 2.0 19.2 dc characteristics table 19.2 dc characteristics (2) 476 table amended item symbol min typ max current dissipation * 2 i cc * 3 standby mode 1.0 10 80 analo g power supply current durin g a/d conversion ai cc 0.6 1.5 durin g a/d and d/a conversion 0.6 1.5 idle 0.01 5.0 ? ? ? ? ? ? rev.4.00 aug. 20, 2007, page xv of xliv rej09b0395-0400 item page revision (see manual for details) 19.3 ac characteristics table 19.6 bus timing 481, 482 table amended condition a b and c item symbol min max min max unit test conditions fi g ure 19.7, fi g ure 19.8 read data setup time t rds 25 25 ns read data hold time t rdh 0 0 ns write data delay time t wdd 35 35 ns write data setup time 1 t wds1 1.0 t cyc ? 30 1.0 t cyc ? 30 ns write data setup time 2 t wds2 2.0 t cyc ? 30 2.0 t cyc ? 30 ns write data hold time t wdh 0.5 t cyc ? 15 0.5 t cyc ? 15 ns read data access time 1 t acc1 2.0 t cyc ? 45 2.0 t cyc ? 45 ns fi g ure 19.7, fi g ure 19.8 read data access time 2 t acc2 3.0 t cyc ? 45 3.0 t cyc ? 45 ns read data access time 3 t acc3 1.5 t cyc ? 45 1.5 t cyc ? 45 ns read data access time 4 t acc4 2.5 t cyc ? 45 2.5 t cyc ? 45 ns prechar g e time 1 t pch1 1.0 t cyc ? 20 1.0 t cyc ? 20 ns prechar g e time 2 t pch2 0.5 t cyc ? 20 0.5 t cyc ? 20 ns ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 19.4 a/d conversion characteristics table 19.8 a/d conversion characteristics 486 note added c.7 port b block diagrams figure c.7 (a) port b block diagram (pins pb 0 and pb 2 ) 616 figure amended pbn figure c.7 (b) port b block diagram (pins pb 1 and pb 3 ) 617 figure amended pb n rev.4.00 aug. 20, 2007 page xvi of xliv rej09b0395-0400 all trademarks and registered trademarks are the property of their respective owners. rev.4.00 aug. 20, 2007, page xvii of xliv rej09b0395-0400 contents section 1 overview ............................................................................................................. 1 1.1 overview....................................................................................................................... .... 1 1.2 block diagram .................................................................................................................. 5 1.3 pin description................................................................................................................ .. 6 1.3.1 pin arrangement .................................................................................................. 6 1.3.2 pin functions ....................................................................................................... 8 1.3.3 pin assignments in each mode ........................................................................... 12 section 2 cpu ...................................................................................................................... 17 2.1 overview....................................................................................................................... .... 17 2.1.1 features................................................................................................................ 17 2.1.2 differences from h8/300 cpu............................................................................. 18 2.2 cpu operating modes ...................................................................................................... 18 2.3 address space .................................................................................................................. . 19 2.4 register configuration...................................................................................................... 20 2.4.1 overview.............................................................................................................. 20 2.4.2 general registers ................................................................................................. 21 2.4.3 control registers ................................................................................................. 22 2.4.4 initial cpu register values ................................................................................. 23 2.5 data formats ................................................................................................................... .. 24 2.5.1 general register data formats ............................................................................ 24 2.5.2 memory data formats ......................................................................................... 25 2.6 instruction set ................................................................................................................ ... 27 2.6.1 instruction set overview ..................................................................................... 27 2.6.2 instructions and a ddressing m odes ..................................................................... 28 2.6.3 tables of instructions classified by function...................................................... 29 2.6.4 basic instruction formats .................................................................................... 38 2.6.5 notes on use of bit manipulation instructions.................................................... 39 2.7 addressing modes and effective address calculation ..................................................... 41 2.7.1 addressing modes ............................................................................................... 41 2.7.2 effective address calculation.............................................................................. 43 2.8 processing states.............................................................................................................. . 47 2.8.1 overview.............................................................................................................. 47 2.8.2 program execution state...................................................................................... 47 2.8.3 exception-handling state .................................................................................... 48 2.8.4 exception handling operation............................................................................. 49 2.8.5 bus-released state............................................................................................... 50 2.8.6 reset state............................................................................................................ 50 rev.4.00 aug. 20, 2007 page xviii of xliv rej09b0395-0400 2.8.7 power-down state ............................................................................................... 51 2.9 basic operational timing ................................................................................................. 51 2.9.1 overview.............................................................................................................. 51 2.9.2 on-chip memory access timing........................................................................ 51 2.9.3 on-chip supporting modul e access timing ...................................................... 52 2.9.4 access to external address space ....................................................................... 53 section 3 mcu operating modes .................................................................................. 55 3.1 overview....................................................................................................................... .... 55 3.1.1 operating mode selection ................................................................................... 55 3.1.2 register configuration......................................................................................... 56 3.2 mode control register (mdcr) ...................................................................................... 56 3.3 system control register (syscr) ................................................................................... 57 3.4 operating mode descriptions ........................................................................................... 60 3.4.1 mode 1 ................................................................................................................. 60 3.4.2 mode 2 ................................................................................................................. 60 3.4.3 mode 3 ................................................................................................................. 60 3.4.4 mode 4 ................................................................................................................. 60 3.4.5 modes 5 to 7 ........................................................................................................ 60 3.5 pin functions in each operating mode ............................................................................ 61 3.6 memory map in each operating mode ............................................................................ 62 3.6.1 reserved areas .................................................................................................... 62 section 4 exception handling ......................................................................................... 65 4.1 overview....................................................................................................................... .... 65 4.1.1 exception handling types and priority............................................................... 65 4.1.2 exception handling operation............................................................................. 65 4.1.3 exception vector table ....................................................................................... 66 4.2 reset.......................................................................................................................... ........ 68 4.2.1 overview.............................................................................................................. 68 4.2.2 reset sequence .................................................................................................... 68 4.2.3 interrupts after reset............................................................................................ 70 4.3 interrupts..................................................................................................................... ...... 71 4.4 trap instruction............................................................................................................... .. 71 4.5 stack status after exception handling.............................................................................. 72 4.6 notes on stack usage ....................................................................................................... 73 section 5 interrupt controller .......................................................................................... 75 5.1 overview....................................................................................................................... .... 75 5.1.1 features................................................................................................................ 75 rev.4.00 aug. 20, 2007, page xix of xliv rej09b0395-0400 5.1.2 block diagram ..................................................................................................... 76 5.1.3 pin configuration................................................................................................. 77 5.1.4 register configuration......................................................................................... 77 5.2 register descriptions ........................................................................................................ 7 8 5.2.1 system control register (syscr) ...................................................................... 78 5.2.2 interrupt priority registers a and b (ipra, iprb)............................................. 79 5.2.3 irq status register (isr).................................................................................... 84 5.2.4 irq enable register (ier) .................................................................................. 85 5.2.5 irq sense control register (iscr) .................................................................... 86 5.3 interrupt sources .............................................................................................................. . 87 5.3.1 external interrupts ............................................................................................... 87 5.3.2 internal interrupts................................................................................................. 88 5.3.3 interrupt exception handling vector table......................................................... 88 5.4 interrupt operation............................................................................................................ 92 5.4.1 interrupt handling process................................................................................... 92 5.4.2 interrupt exception handling sequence .............................................................. 97 5.4.3 interrupt res ponse time...................................................................................... 98 5.5 usage notes .................................................................................................................... .. 99 5.5.1 contention between interrupt and in terrupt-disabling instruction ...................... 99 5.5.2 instructions that inhibit interrupts........................................................................ 100 5.5.3 interrupts during eepmov instruction execution .............................................. 100 section 6 bus controller .................................................................................................... 101 6.1 overview....................................................................................................................... .... 101 6.1.1 features................................................................................................................ 101 6.1.2 block diagram ..................................................................................................... 102 6.1.3 pin configuration................................................................................................. 103 6.1.4 register configuration......................................................................................... 104 6.2 register descriptions ........................................................................................................ 1 04 6.2.1 bus width control register (abwcr)............................................................... 104 6.2.2 access state control register (astcr) ............................................................. 105 6.2.3 wait control registers h and l (wcrh, wcrl).............................................. 106 6.2.4 bus release control register (brcr) ................................................................ 110 6.2.5 bus control register (bcr) ................................................................................ 111 6.2.6 chip select control register (cscr).................................................................. 114 6.2.7 address control register (adrcr).................................................................... 115 6.3 operation...................................................................................................................... ..... 116 6.3.1 area division ....................................................................................................... 116 6.3.2 bus specifications................................................................................................ 118 6.3.3 memory interfaces ............................................................................................... 119 rev.4.00 aug. 20, 2007 page xx of xliv rej09b0395-0400 6.3.4 chip select signals .............................................................................................. 119 6.3.5 address output method....................................................................................... 120 6.4 basic bus interface ........................................................................................................... 122 6.4.1 overview.............................................................................................................. 122 6.4.2 data size and data alignment............................................................................. 122 6.4.3 valid strobes........................................................................................................ 123 6.4.4 memory areas ..................................................................................................... 124 6.4.5 basic bus control signal timing ........................................................................ 125 6.4.6 wait control ........................................................................................................ 132 6.5 idle cycle..................................................................................................................... ..... 134 6.5.1 operation ............................................................................................................. 134 6.5.2 pin states in idle cycle ........................................................................................ 136 6.6 bus arbiter.................................................................................................................... .... 137 6.6.1 operation ............................................................................................................. 137 6.7 register and pin input timi ng .......................................................................................... 139 6.7.1 register write timing ......................................................................................... 139 6.7.2 breq pin input timing ...................................................................................... 140 section 7 i/o ports .............................................................................................................. 141 7.1 overview....................................................................................................................... .... 141 7.2 port 4......................................................................................................................... ........ 144 7.2.1 overview.............................................................................................................. 144 7.2.2 register descriptions ........................................................................................... 145 7.3 port 6......................................................................................................................... ........ 148 7.3.1 overview.............................................................................................................. 148 7.3.2 register descriptions ........................................................................................... 148 7.4 port 7......................................................................................................................... ........ 151 7.4.1 overview.............................................................................................................. 151 7.4.2 register description............................................................................................. 151 7.5 port 8......................................................................................................................... ........ 152 7.5.1 overview.............................................................................................................. 152 7.5.2 register descriptions ........................................................................................... 153 7.6 port 9......................................................................................................................... ........ 156 7.6.1 overview.............................................................................................................. 156 7.6.2 register descriptions ........................................................................................... 157 7.7 port a......................................................................................................................... ....... 161 7.7.1 overview.............................................................................................................. 161 7.7.2 register descriptions ........................................................................................... 162 7.8 port b ......................................................................................................................... ....... 172 7.8.1 overview.............................................................................................................. 172 rev.4.00 aug. 20, 2007, page xxi of xliv rej09b0395-0400 7.8.2 register descriptions ........................................................................................... 173 section 8 16-bit timer ....................................................................................................... 177 8.1 overview....................................................................................................................... .... 177 8.1.1 features................................................................................................................ 177 8.1.2 block diagrams ................................................................................................... 179 8.1.3 pin configuration................................................................................................. 182 8.1.4 register configuration......................................................................................... 183 8.2 register descriptions ........................................................................................................ 1 84 8.2.1 timer start register (tstr)................................................................................ 184 8.2.2 timer synchro register (tsnc) ......................................................................... 185 8.2.3 timer mode register (tmdr) ............................................................................ 187 8.2.4 timer interrupt status re gister a (tisra)......................................................... 189 8.2.5 timer interrupt status re gister b (tisrb) ......................................................... 192 8.2.6 timer interrupt status re gister c (tisrc) ......................................................... 195 8.2.7 timer counters (16tcnt) .................................................................................. 197 8.2.8 general registers (gra, grb)........................................................................... 198 8.2.9 timer control registers (16tcr) ....................................................................... 199 8.2.10 timer i/o control register (tior) ..................................................................... 202 8.2.11 timer output level setting register c (tolr) ................................................. 204 8.3 cpu interface.................................................................................................................. .. 206 8.3.1 16-bit accessible registers ................................................................................. 206 8.3.2 8-bit accessible registers ................................................................................... 208 8.4 operation...................................................................................................................... ..... 209 8.4.1 overview.............................................................................................................. 209 8.4.2 basic functions.................................................................................................... 209 8.4.3 synchronization ................................................................................................... 217 8.4.4 pwm mode.......................................................................................................... 219 8.4.5 phase counting mode .......................................................................................... 223 8.4.6 16-bit timer output timing................................................................................ 225 8.5 interrupts ..................................................................................................................... ...... 226 8.5.1 setting of status flags.......................................................................................... 226 8.5.2 timing of clearing of status flags ...................................................................... 228 8.5.3 interrupt sources.................................................................................................. 229 8.6 usage notes .................................................................................................................... .. 230 section 9 8-bit timers ....................................................................................................... 243 9.1 overview....................................................................................................................... .... 243 9.1.1 features................................................................................................................ 243 9.1.2 block diagram ..................................................................................................... 245 rev.4.00 aug. 20, 2007 page xxii of xliv rej09b0395-0400 9.1.3 pin configuration................................................................................................. 246 9.1.4 register configuration......................................................................................... 247 9.2 register descriptions ........................................................................................................ 2 48 9.2.1 timer counters (8tcnt) .................................................................................... 248 9.2.2 time constant registers a (tcora) ................................................................. 249 9.2.3 time constant registers b (tcorb) ................................................................. 250 9.2.4 timer control register (8tcr)........................................................................... 251 9.2.5 timer control/status registers (8tcsr) ............................................................ 254 9.3 cpu interface.................................................................................................................. .. 259 9.3.1 8-bit registers ..................................................................................................... 259 9.4 operation ...................................................................................................................... .... 261 9.4.1 8tcnt count timing.......................................................................................... 261 9.4.2 compare match timing....................................................................................... 262 9.4.3 input capture si gnal timi ng ............................................................................... 263 9.4.4 timing of status flag setting .............................................................................. 264 9.4.5 operation with cascaded connection.................................................................. 265 9.4.6 input capture setting ........................................................................................... 268 9.5 interrupt ...................................................................................................................... ...... 269 9.5.1 interrupt sources.................................................................................................. 269 9.5.2 a/d converter activation.................................................................................... 270 9.6 8-bit timer applica tion example..................................................................................... 271 9.7 usage notes .................................................................................................................... .. 272 9.7.1 contention between 8tcnt write and clear...................................................... 272 9.7.2 contention between 8tcnt write and increment .............................................. 273 9.7.3 contention between tcor write and compare match ...................................... 274 9.7.4 contention between tcor read and input capture ........................................... 275 9.7.5 contention between counter clearing by input capture and counter increment ............................................................................................................. 276 9.7.6 contention between tcor write and input capture .......................................... 277 9.7.7 contention between 8tcnt byte write and increment in 16-bit count mode (cascaded connection) ........................................................................................ 278 9.7.8 contention between compare matches a and b ................................................. 279 9.7.9 8tcnt operation and internal clock source switchover .................................. 279 section 10 programmable t iming pattern controller (tpc) ................................. 283 10.1 overview....................................................................................................................... .... 283 10.1.1 features................................................................................................................ 283 10.1.2 block diagram..................................................................................................... 284 10.1.3 pin configuration................................................................................................. 285 10.1.4 register configuration......................................................................................... 286 rev.4.00 aug. 20, 2007, page xxiii of xliv rej09b0395-0400 10.2 register descriptions ........................................................................................................ 2 87 10.2.1 port a data direction register (paddr) ........................................................... 287 10.2.2 port a data register (padr) .............................................................................. 287 10.2.3 port b data direction register (pbddr)............................................................ 288 10.2.4 port b data register (pbdr) .............................................................................. 288 10.2.5 next data register a (ndra) ............................................................................ 289 10.2.6 next data register b (ndrb)............................................................................. 291 10.2.7 next data enable register a (ndera).............................................................. 293 10.2.8 next data enable register b (nderb) .............................................................. 294 10.2.9 tpc output control re gister (tpcr) ................................................................. 295 10.2.10 tpc output mode register (tpmr) ................................................................... 298 10.3 operation...................................................................................................................... ..... 300 10.3.1 overview.............................................................................................................. 300 10.3.2 output timing...................................................................................................... 301 10.3.3 normal tpc output............................................................................................. 302 10.3.4 non-overlapping tpc output ............................................................................. 304 10.3.5 tpc output triggering by input capture ............................................................ 306 10.4 usage notes .................................................................................................................... .. 307 10.4.1 operation of tpc output pins ............................................................................. 307 10.4.2 note on non-overla pping out put........................................................................ 307 section 11 watchdog timer ............................................................................................. 309 11.1 overview....................................................................................................................... .... 309 11.1.1 features................................................................................................................ 309 11.1.2 block diagram ..................................................................................................... 310 11.1.3 pin configuration................................................................................................. 310 11.1.4 register configuration......................................................................................... 311 11.2 register descriptions ........................................................................................................ 3 11 11.2.1 timer counter (tcnt)........................................................................................ 311 11.2.2 timer control/status register (tcsr) ................................................................ 312 11.2.3 reset control/status register (rstcsr) ............................................................ 314 11.2.4 notes on register access..................................................................................... 315 11.3 operation...................................................................................................................... ..... 317 11.3.1 watchdog timer op eration ................................................................................. 317 11.3.2 interval timer operation ..................................................................................... 318 11.3.3 timing of setting of over flow flag (ovf) ......................................................... 318 11.3.4 timing of setting of watchdog timer reset bit (wrst) .................................. 319 11.4 interrupts ..................................................................................................................... ...... 320 11.5 usage notes .................................................................................................................... .. 320 rev.4.00 aug. 20, 2007 page xxiv of xliv rej09b0395-0400 section 12 serial communication interface ................................................................ 321 12.1 overview....................................................................................................................... .... 321 12.1.1 features................................................................................................................ 321 12.1.2 block diagram..................................................................................................... 323 12.1.3 pin configuration................................................................................................. 324 12.1.4 register configuration......................................................................................... 325 12.2 register descriptions ........................................................................................................ 3 26 12.2.1 receive shift register (rsr) .............................................................................. 326 12.2.2 receive data register (rdr) .............................................................................. 326 12.2.3 transmit shift register (tsr) ............................................................................. 327 12.2.4 transmit data register (tdr)............................................................................. 327 12.2.5 serial mode register (smr) ............................................................................... 328 12.2.6 serial control regi ster (scr).............................................................................. 332 12.2.7 serial status register (ssr) ................................................................................ 337 12.2.8 bit rate register (brr) ...................................................................................... 342 12.3 operation ...................................................................................................................... .... 350 12.3.1 overview.............................................................................................................. 350 12.3.2 operation in async hronous m ode ....................................................................... 353 12.3.3 multiprocessor communication........................................................................... 362 12.3.4 synchronous op eration........................................................................................ 369 12.4 sci interrupts................................................................................................................. ... 377 12.5 usage notes .................................................................................................................... .. 378 12.5.1 notes on use of sci ............................................................................................ 378 section 13 smart card interface ..................................................................................... 383 13.1 overview....................................................................................................................... .... 383 13.1.1 features................................................................................................................ 383 13.1.2 block diagram..................................................................................................... 384 13.1.3 pin configuration................................................................................................. 385 13.1.4 register configuration......................................................................................... 385 13.2 register descriptions ........................................................................................................ 3 86 13.2.1 smart card mode register (scmr) .................................................................... 386 13.2.2 serial status register (ssr) ................................................................................ 388 13.2.3 serial mode register (smr) ............................................................................... 389 13.2.4 serial control regi ster (scr).............................................................................. 390 13.3 operation ...................................................................................................................... .... 391 13.3.1 overview.............................................................................................................. 391 13.3.2 pin connections ................................................................................................... 391 13.3.3 data format ......................................................................................................... 392 13.3.4 register settings .................................................................................................. 394 rev.4.00 aug. 20, 2007, page xxv of xliv rej09b0395-0400 13.3.5 clock.................................................................................................................... 396 13.3.6 transmitting and receiving data......................................................................... 398 13.4 usage notes .................................................................................................................... .. 406 section 14 a/d converter ................................................................................................. 411 14.1 overview....................................................................................................................... .... 411 14.1.1 features................................................................................................................ 411 14.1.2 block diagram ..................................................................................................... 412 14.1.3 pin configuration................................................................................................. 413 14.1.4 register configuration......................................................................................... 414 14.2 register descriptions ........................................................................................................ 4 15 14.2.1 a/d data registers a to d (addra to addrd).............................................. 415 14.2.2 a/d control/status register (adcsr) ............................................................... 416 14.2.3 a/d control register (adcr) ............................................................................ 418 14.3 cpu interface.................................................................................................................. .. 419 14.4 operation...................................................................................................................... ..... 421 14.4.1 single mode (scan = 0)..................................................................................... 421 14.4.2 scan mode (scan = 1)....................................................................................... 423 14.4.3 input sampling and a/d conversion time.......................................................... 425 14.4.4 external trigger input timi ng............................................................................. 427 14.5 interrupts ..................................................................................................................... ...... 427 14.6 usage notes .................................................................................................................... .. 428 section 15 d/a converter ................................................................................................. 435 15.1 overview....................................................................................................................... .... 435 15.1.1 features................................................................................................................ 435 15.1.2 block diagram ..................................................................................................... 436 15.1.3 pin configuration................................................................................................. 437 15.1.4 register configuration......................................................................................... 437 15.2 register descriptions ........................................................................................................ 4 38 15.2.1 d/a data registers 0 and 1 (dadr0, dadr1).................................................. 438 15.2.2 d/a control register (dacr) ............................................................................ 438 15.2.3 d/a standby control register (dastcr).......................................................... 440 15.3 operation...................................................................................................................... ..... 440 15.4 d/a output control .......................................................................................................... 44 2 section 16 ram .................................................................................................................. 443 16.1 overview....................................................................................................................... .... 443 16.1.1 block diagram ..................................................................................................... 444 16.1.2 register configuration......................................................................................... 444 rev.4.00 aug. 20, 2007 page xxvi of xliv rej09b0395-0400 16.2 system control register (syscr) ................................................................................... 445 16.3 operation ...................................................................................................................... .... 446 section 17 clock pulse generator .................................................................................. 447 17.1 overview....................................................................................................................... .... 447 17.1.1 block diagram..................................................................................................... 448 17.2 oscillator circuit............................................................................................................. .. 449 17.2.1 connecting a crystal resonator........................................................................... 449 17.2.2 external clock input............................................................................................ 451 17.3 duty adjustment circuit................................................................................................... 454 17.4 prescalers ..................................................................................................................... ..... 454 17.5 frequency divider ............................................................................................................ 4 54 17.5.1 register configuration......................................................................................... 454 17.5.2 division control regi ster (divcr) .................................................................... 455 17.5.3 usage notes ......................................................................................................... 456 section 18 power-down state ......................................................................................... 457 18.1 overview....................................................................................................................... .... 457 18.2 register configuration...................................................................................................... 45 9 18.2.1 system control register (syscr) ...................................................................... 459 18.2.2 module standby control re gister h (mstcrh)................................................ 461 18.2.3 module standby control re gister l (mstcrl)................................................. 462 18.3 sleep mode ..................................................................................................................... .. 464 18.3.1 transition to sleep mode..................................................................................... 464 18.3.2 exit from sleep mode.......................................................................................... 464 18.4 software sta ndby mode .................................................................................................... 464 18.4.1 transition to software standby mode ................................................................. 464 18.4.2 exit from software standby mode ...................................................................... 465 18.4.3 selection of waiting time for exit from software standby mode...................... 465 18.4.4 sample application of so ftware sta ndby mode .................................................. 467 18.4.5 note...................................................................................................................... 467 18.5 hardware standby mode .................................................................................................. 468 18.5.1 transition to hardware standby mode................................................................ 468 18.5.2 exit from hardware standby mode ..................................................................... 468 18.5.3 timing for hardware standby mode ................................................................... 468 18.6 module standby function................................................................................................. 469 18.6.1 module standby timing ...................................................................................... 469 18.6.2 read/write in m odule standb y............................................................................ 469 18.6.3 usage notes ......................................................................................................... 469 18.7 system clock output di sabling function......................................................................... 470 rev.4.00 aug. 20, 2007, page xxvii of xliv rej09b0395-0400 section 19 electrical characteristics .............................................................................. 471 19.1 absolute maximum ratings ............................................................................................. 471 19.2 dc character istics ............................................................................................................ 472 19.3 ac character istics ............................................................................................................ 479 19.4 a/d conversion characteristics........................................................................................ 485 19.5 d/a conversion characteristics........................................................................................ 487 19.6 operational timing ........................................................................................................... 4 88 19.6.1 clock timi ng ....................................................................................................... 488 19.6.2 control signal timing ......................................................................................... 489 19.6.3 bus timing .......................................................................................................... 491 19.6.4 tpc and i/o port timing..................................................................................... 495 19.6.5 timer input/output timing ................................................................................. 495 19.6.6 sci input/output timing ..................................................................................... 496 appendix a instruction set .............................................................................................. 497 a.1 instruction list ............................................................................................................... ... 497 a.2 operation code maps ....................................................................................................... 512 a.3 number of states required for execution ........................................................................ 515 appendix b internal i/o registers ................................................................................. 525 b.1 address list ................................................................................................................... ... 525 b.2 functions...................................................................................................................... ..... 540 appendix c i/o port block diagrams ........................................................................... 598 c.1 port 4 block diagram ....................................................................................................... 598 c.2 port 6 block diagrams...................................................................................................... 599 c.3 port 7 block diagrams...................................................................................................... 603 c.4 port 8 block diagrams...................................................................................................... 604 c.5 port 9 block diagrams...................................................................................................... 608 c.6 port a block diagrams ..................................................................................................... 614 c.7 port b block diagrams ..................................................................................................... 617 appendix d pin states ....................................................................................................... 623 d.1 port states in each mode .................................................................................................. 623 d.2 pin states at reset ............................................................................................................ . 626 appendix e timing of transition to and recovery from hardware standby mode ............................................................................................... 628 appendix f pr oduct code lineup .................................................................................. 629 rev.4.00 aug. 20, 2007 page xxviii of xliv rej09b0395-0400 appendix g package dimensions .................................................................................. 630 appendix h comparison of h8/ 300h series product specifications .................. 632 h.1 differences between h8/3067 and h8/3062 group, h8/3048 group, h8/3006 and h8/3007, and h8/ 3008 ................................................................................ 632 h.2 comparison of pin functions of 100-pin package products (fp-100b, tfp-100b) ....... 635 rev.4.00 aug. 20, 2007, page xxix of xliv rej09b0395-0400 figures section 1 overview figure 1.1 block diagram ................................................................................................... 5 figure 1.2 pin arrangement of h8/3008 (fp-100b or tfp-100b package, top view) ..... 7 section 2 cpu figure 2.1 cpu operating modes ....................................................................................... 18 figure 2.2 memory map...................................................................................................... 19 figure 2.3 cpu registers .................................................................................................... 20 figure 2.4 usage of general registers ................................................................................ 21 figure 2.5 stack ............................................................................................................... .... 22 figure 2.6 general register data formats (1)..................................................................... 24 figure 2.7 general register data formats (2)..................................................................... 25 figure 2.8 memory data formats........................................................................................ 26 figure 2.9 instruction formats............................................................................................. 39 figure 2.10 memory-indirect bran ch address specification ................................................ 43 figure 2.11 processing states ................................................................................................ 4 7 figure 2.12 classification of exception sources ................................................................... 48 figure 2.13 state transitions ................................................................................................. 49 figure 2.14 stack structure af ter exception handling .......................................................... 50 figure 2.15 on-chip memory access cycle......................................................................... 52 figure 2.16 pin states during on-chip memory access (address update mode 1)............. 52 figure 2.17 access cycle for on -chip supporting modules ................................................ 53 figure 2.18 pin states during access to on-chip suppor ting modules ................................ 53 section 3 mcu operating modes figure 3.1 memory map of h8/3008 in each operating mode........................................... 63 section 4 exception handling figure 4.1 exception sources .............................................................................................. 66 figure 4.2 reset sequence (modes 1 and 3)........................................................................ 69 figure 4.3 reset sequence (modes 2 and 4)........................................................................ 70 figure 4.4 interrupt sources and number of interrupts....................................................... 71 figure 4.5 stack after completion of exception handling.................................................. 72 figure 4.6 operation when sp value is odd ....................................................................... 74 section 5 interrupt controller figure 5.1 interrupt contro ller block diagram ................................................................... 76 figure 5.2 block diagram of interrupts irq 5 to irq 0 ......................................................... 87 rev.4.00 aug. 20, 2007 page xxx of xliv rej09b0395-0400 figure 5.3 timing of setting of irqnf ............................................................................... 88 figure 5.4 process up to interrupt acceptance when ue = 1 ............................................. 93 figure 5.5 interrupt masking stat e transitions (example) ................................................. 95 figure 5.6 process up to interrupt acceptance when ue = 0 ............................................. 96 figure 5.7 interrupt exception handling sequence............................................................. 97 figure 5.8 contention between interrupt a nd interrupt-disabling instruction .................... 99 section 6 bus controller figure 6.1 block diagram of bus controller....................................................................... 102 figure 6.2 access area map for each operating mode...................................................... 116 figure 6.3 memory map in 16-mbyte mode....................................................................... 117 figure 6.4 cs n signal output timing (n = 0 to 7) .............................................................. 120 figure 6.5 sample address output in each address update mode (basic bus interface, 3-state space) .................................................................. 120 figure 6.6 example of consecutive extern al space accesses in address update mode 2 ............................................................................................................... 121 figure 6.7 access sizes and data ali gnment control (8-bit access area) ........................ 122 figure 6.8 access sizes and data alignm ent control (16-bit access area) ...................... 123 figure 6.9 bus control signal timing for 8-bit, three-state-access area ........................ 125 figure 6.10 bus control signal timing fo r 8-bit, two-state-access area .......................... 126 figure 6.11 bus control signal timing for 16-bit, three-state-access area (1) (byte access to even address) .......................................................................... 127 figure 6.12 bus control signal timing for 16-bit, three-state-access area (2) (byte access to odd address) ........................................................................... 128 figure 6.13 bus control signal timing for 16-bit, three-state-access area (3) (word access).................................................................................................... 129 figure 6.14 bus control signal timing for 16-bit, two-state-access area (1) (byte access to even address) .......................................................................... 130 figure 6.15 bus control signal timing for 16-bit, two-state-access area (2) (byte access to odd address) ........................................................................... 131 figure 6.16 bus control signal timing for 16-bit, two-state-access area (3) (word access).................................................................................................... 132 figure 6.17 example of wait st ate insertion timing............................................................ 133 figure 6.18 example of idle cy cle operation (icis1 = 1).................................................... 134 figure 6.19 example of idle cy cle operation (icis0 = 1).................................................... 135 figure 6.20 example of idle cycle operation ....................................................................... 136 figure 6.21 example of external bus master operation....................................................... 138 figure 6.22 astcr write timing ........................................................................................ 139 figure 6.23 ddr write timing............................................................................................. 139 figure 6.24 brcr write timing .......................................................................................... 140 rev.4.00 aug. 20, 2007, page xxxi of xliv rej09b0395-0400 section 7 i/o ports figure 7.1 port 4 pin configuration..................................................................................... 144 figure 7.2 port 6 pin configuration..................................................................................... 148 figure 7.3 port 7 pin configuration..................................................................................... 151 figure 7.4 port 8 pin configuration..................................................................................... 153 figure 7.5 port 9 pin configuration..................................................................................... 156 figure 7.6 port a pin configuration.................................................................................... 162 figure 7.7 port b pin configuration .................................................................................... 172 section 8 16-bit timer figure 8.1 16-bit timer block diagram (overall) ................................................................ 179 figure 8.2 block diagram of channels 0 and 1................................................................... 180 figure 8.3 block diagram of channel 2.............................................................................. 181 figure 8.4 16tcnt access operation [cpu 16tcnt (word)] .................................... 206 figure 8.5 access to timer counter (cpu reads 16tcnt, word).................................... 206 figure 8.6 access to timer counter h (cpu writes to 16tcnth, upper byte)............... 207 figure 8.7 access to timer counter l (cpu writes to 16tcntl, lower byte) ............... 207 figure 8.8 access to timer counter h (cpu reads 16tcnth, upper byte).................... 207 figure 8.9 access to timer counter l (cpu reads 16tcntl, lower byte) .................... 208 figure 8.10 16tcr access (cpu writes to 16tcr) ............................................................ 208 figure 8.11 16tcr access (cpu reads 16tcr) ................................................................. 209 figure 8.12 counter setup pr ocedure (exa mple) .................................................................. 210 figure 8.13 free-running co unter operation ....................................................................... 211 figure 8.14 periodic count er operation................................................................................ 212 figure 8.15 count timing for in ternal clock sources .......................................................... 212 figure 8.16 count timing for external clock sources (when both edges are detected)..... 213 figure 8.17 setup procedure for waveform ou tput by compare match (example)............. 213 figure 8.18 0 and 1 output (toa = 1, tob = 0) .................................................................. 214 figure 8.19 toggle output (toa = 1, tob = 0) .................................................................. 214 figure 8.20 output compar e output timing......................................................................... 215 figure 8.21 setup procedure for input capture (example) ................................................... 216 figure 8.22 input capt ure (example) .................................................................................... 216 figure 8.23 input captur e signal ti ming .............................................................................. 217 figure 8.24 setup procedure for s ynchronization (example) ............................................... 218 figure 8.25 synchroniza tion (example) ................................................................................ 219 figure 8.26 setup procedure for pwm mode (example)...................................................... 220 figure 8.27 pwm mode (example 1) ................................................................................... 221 figure 8.28 pwm mode (example 2) ................................................................................... 222 figure 8.29 setup procedure for phas e counting mode (example) ...................................... 223 figure 8.30 operation in phase counting mode (example).................................................. 224 rev.4.00 aug. 20, 2007 page xxxii of xliv rej09b0395-0400 figure 8.31 phase difference, overlap, and pulse width in phase counting mode ............. 224 figure 8.32 timing for setting 16-bit timer output leve l by writing to tolr................. 225 figure 8.33 timing of setting of imfa and imfb by compare match ............................... 226 figure 8.34 timing of setting of imfa and imfb by input capture................................... 227 figure 8.35 timing of setting of ovf .................................................................................. 228 figure 8.36 timing of clearin g of status flags .................................................................... 228 figure 8.37 contention between 16tcnt write and clear .................................................. 230 figure 8.38 contention between 16tcnt word write and increment................................. 231 figure 8.39 contention between 16tcnt byte write and increment .................................. 232 figure 8.40 contention between general re gister write and compare match..................... 233 figure 8.41 contention between 16t cnt write and overflow............................................ 234 figure 8.42 contention between general re gister read and i nput capture ......................... 235 figure 8.43 contention between counter clearing by input capture and counter increment............................................................................................................ 236 figure 8.44 contention between general re gister write and i nput captur e ........................ 237 section 9 8-bit timers figure 9.1 block diagram of 8-bit timer unit (two channels: group 0) ......................... 245 figure 9.2 8tcnt access operation (cpu writes to 8tcnt, word)............................... 259 figure 9.3 8tcnt access operation (cpu reads 8tcnt, word).................................... 259 figure 9.4 8tcnt0 access operation (cpu writes to 8tcnt0, upper byte).................. 259 figure 9.5 8tcnt1 access operation (cpu writes to 8tcnt1, lower byte) ................. 260 figure 9.6 8tcnt0 access operation (c pu reads 8tcnt0, upper byte)....................... 260 figure 9.7 8tcnt1 access operation (cpu reads 8tcnt1, lower byte) ...................... 260 figure 9.8 count timing for in ternal clock input............................................................... 261 figure 9.9 count timing for external cl ock input (both-edge detection) ........................ 262 figure 9.10 timing of timer output ..................................................................................... 262 figure 9.11 timing of clear by compare match................................................................... 263 figure 9.12 timing of clear by input ca pture ...................................................................... 263 figure 9.13 timing of input capture input signal ................................................................ 264 figure 9.14 cmf flag setting timing when compare match occurs.................................. 264 figure 9.15 cmfb flag setting timing when input capture occurs ................................... 265 figure 9.16 timing of ovf setting....................................................................................... 265 figure 9.17 example of pulse output.................................................................................... 271 figure 9.18 contention between 8tcnt write and clear .................................................... 272 figure 9.19 contention between 8tcnt write and increment............................................. 273 figure 9.20 contention between tcor write and compare match..................................... 274 figure 9.21 contention between tcor read and input capture.......................................... 275 figure 9.22 contention between counter clearing by input capture and counter increment............................................................................................................ 276 rev.4.00 aug. 20, 2007, page xxxiii of xliv rej09b0395-0400 figure 9.23 contention between tcor write and input capture......................................... 277 figure 9.24 contention between 8tcnt byte write and increment in 16-bit count mode................................................................................................................... 278 section 10 programmable timi ng pattern controller (tpc) figure 10.1 tpc block diagram ........................................................................................... 284 figure 10.2 tpc output operation........................................................................................ 300 figure 10.3 timing of transfer of next data re gister contents and ou tput (example) ...... 301 figure 10.4 setup procedure for norm al tpc output (example)......................................... 302 figure 10.5 normal tpc ou tput example (five-phas e pulse output) ................................. 303 figure 10.6 setup procedure for non-ov erlapping tpc output (example) ......................... 304 figure 10.7 non-overlapping tpc output example (four-phase compleme ntary non-overlapping pulse output) ......................... 305 figure 10.8 tpc output tr iggering by input capture (example)......................................... 306 figure 10.9 non-overlapp ing tpc output............................................................................ 307 figure 10.10 non-overlapping oper ation and ndr write timing ........................................ 308 section 11 watchdog timer figure 11.1 wdt block diagram ......................................................................................... 310 figure 11.2 format of data written to tcnt and tcsr ..................................................... 315 figure 11.3 format of data written to rstcsr................................................................... 316 figure 11.4 operation in watchdog timer mode.................................................................. 317 figure 11.5 interval timer operation.................................................................................... 318 figure 11.6 timing of setting of ovf .................................................................................. 318 figure 11.7 timing of setting of wrst bit and internal reset............................................ 319 figure 11.8 contention between tc nt write and count up ................................................ 320 section 12 serial co mmunication interface figure 12.1 sci block diagram ............................................................................................ 323 figure 12.2 data format in asynchronous communication (example: 8-bit data with parity and 2 stop bits) ............................................ 353 figure 12.3 phase relationship between output clock and serial data (asynchronous mode) ........................................................................................ 355 figure 12.4 sample flowchart for sci initialization............................................................. 356 figure 12.5 sample flowchart fo r transmitting serial data ................................................. 357 figure 12.6 example of sci transmit operation in asynchronous mode (8-bit data with parity and one stop bit).......................................................... 358 figure 12.7 sample flowchart fo r receiving serial data ..................................................... 359 figure 12.8 example of sci receive operation (8-bit data with parity and one stop bit).......................................................... 362 rev.4.00 aug. 20, 2007 page xxxiv of xliv rej09b0395-0400 figure 12.9 example of communication among pr ocessors using multiprocessor format (sending data h'aa to r eceiving processor a)................................................ 363 figure 12.10 sample flowchart for tran smitting multiprocessor serial data........................ 364 figure 12.11 example of sci transmit operation (8-bit data with mu ltiprocessor bit and one stop bit) ..................................... 365 figure 12.12 sample flowchart for r eceiving multiprocessor serial data ............................ 366 figure 12.13 example of sci receive operation (8-bit data with mu ltiprocessor bit and one stop bit) ..................................... 368 figure 12.14 data format in synchronous comm unication ................................................... 369 figure 12.15 sample flowchart for sci initialization............................................................. 370 figure 12.16 sample flowchart for serial transmitting ......................................................... 371 figure 12.17 example of sci transmit operation .................................................................. 372 figure 12.18 sample flowchar t for serial receiving.............................................................. 373 figure 12.19 example of sci receive operation ................................................................... 375 figure 12.20 sample flowchart for simultane ous serial transmitti ng and receiving ........... 376 figure 12.21 receive data sampling timing in asynchr onous m ode ................................... 379 figure 12.22 example of sync hronous transmission ............................................................. 380 figure 12.23 operation when switching from sc k pin function to port pin function ......... 381 figure 12.24 operation when switching from sck pin function to port pin function (example of preventing low-level output)...................................................... 382 section 13 smart card interface figure 13.1 block diagram of smart card interface............................................................. 384 figure 13.2 smart card interface connection diagram ........................................................ 392 figure 13.3 smart card interface data format ..................................................................... 393 figure 13.4 timing of tend flag setting............................................................................ 399 figure 13.5 sample transmission processing flowchart ...................................................... 400 figure 13.6 relation between transmit oper ation and internal registers ........................... 401 figure 13.7 timing of tend flag setting............................................................................ 401 figure 13.8 sample reception processing flowchart ........................................................... 402 figure 13.9 timing for fi xing cock output.......................................................................... 403 figure 13.10 procedure for stoppi ng and restarting the clock .............................................. 405 figure 13.11 receive data sampling timing in smart card interface mode......................... 406 figure 13.12 retransmission in sci receive mode ................................................................ 408 figure 13.13 retransmission in sci transmit mode .............................................................. 408 section 14 a/d converter figure 14.1 a/d converter block diagram........................................................................... 412 figure 14.2 a/d data register acce ss operation (reading h'aa40).................................. 420 figure 14.3 example of a/d converter operation (single mode, channel 1 selected) ....... 422 rev.4.00 aug. 20, 2007, page xxxv of xliv rej09b0395-0400 figure 14.4 example of a/d converter operation (scan mode, channels an 0 to an 2 selected) .................................................... 424 figure 14.5 a/d conve rsion timi ng ..................................................................................... 426 figure 14.6 external trig ger input ti ming ........................................................................... 427 figure 14.7 example of analog in put protection circuit ...................................................... 429 figure 14.8 analog input pin equivalent circuit .................................................................. 429 figure 14.9 a/d converter accu racy definitions (1) ........................................................... 431 figure 14.10 a/d converter accu racy definitions (2) ........................................................... 432 figure 14.11 analog input circuit (example) ......................................................................... 433 section 15 d/a converter figure 15.1 d/a converter block diagram........................................................................... 436 figure 15.2 example of d/a converter operation................................................................ 441 section 16 ram figure 16.1 ram block diagram ......................................................................................... 444 section 17 clock pulse generator figure 17.1 block diagram of clock pulse generator .......................................................... 448 figure 17.2 connection of crystal resonator (example)...................................................... 449 figure 17.3 crystal resonator equivalent circuit ................................................................. 450 figure 17.4 oscillator circuit bl ock board design precautions ........................................... 451 figure 17.5 external cloc k input (exa mples) ....................................................................... 451 figure 17.6 external cl ock input timing.............................................................................. 453 figure 17.7 external clock outp ut settling delay timing ................................................... 453 section 18 power-down state figure 18.1 nmi timing for software standby mode (e xample) ........................................ 467 figure 18.2 hardware sta ndby mode ti ming ....................................................................... 469 figure 18.3 starting a nd stopping of system clock output.................................................. 470 section 19 electrical characteristics figure 19.1 darlington pair drive circuit (example) ........................................................... 478 figure 19.2 output load circuit............................................................................................ 484 figure 19.3 oscillator settling timing .................................................................................. 488 figure 19.4 reset i nput timi ng............................................................................................. 489 figure 19.5 reset output timing .......................................................................................... 489 figure 19.6 interrupt input timing........................................................................................ 490 figure 19.7 basic bus cycle: two-state access................................................................... 492 figure 19.8 basic bus cycle: three-state access................................................................. 493 rev.4.00 aug. 20, 2007 page xxxvi of xliv rej09b0395-0400 figure 19.9 basic bus cycle: three-stat e access with one wait state ............................... 494 figure 19.10 bus-release mode timing................................................................................. 494 figure 19.11 tpc and i/o port input/output timing.............................................................. 495 figure 19.12 timer inpu t/output timing................................................................................ 495 figure 19.13 timer external clock input timing ................................................................... 496 figure 19.14 sci input clock ti ming ..................................................................................... 496 figure 19.15 sci input/output timi ng in synchrono us mode ............................................... 496 appendix c i/o port block diagrams figure c.1 port 4 block diagram......................................................................................... 598 figure c.2 (a) port 6 block diagram (pin p6 0 ).......................................................................... 599 figure c.2 (b) port 6 block diagram (pin p6 1 ).......................................................................... 600 figure c.2 (c) port 6 block diagram (pin p6 2 ).......................................................................... 601 figure c.2 (d) port 6 block diagram (pin p6 7 ).......................................................................... 602 figure c.3 (a) port 7 block diagram (pins p7 0 to p7 5 ).............................................................. 603 figure c.3 (b) port 7 block diagram (pins p7 6 and p7 7 ) ........................................................... 603 figure c.4 (a) port 8 block diagram (pin p8 0 ).......................................................................... 604 figure c.4 (b) port 8 block diagram (pins p8 1 and p8 2 ) ........................................................... 605 figure c.4 (c) port 8 block diagram (pin p8 3 ).......................................................................... 606 figure c.4 (d) port 8 block diagram (pin p8 4 ).......................................................................... 607 figure c.5 (a) port 9 block diagram (pin p9 0 ).......................................................................... 608 figure c.5 (b) port 9 block diagram (pin p9 1 ).......................................................................... 609 figure c.5 (c) port 9 block diagram (pin p9 2 ).......................................................................... 610 figure c.5 (d) port 9 block diagram (pin p9 3 ).......................................................................... 611 figure c.5 (e) port 9 block diagram (pin p9 4 ).......................................................................... 612 figure c.5 (f) port 9 block diagram (pin p9 5 ).......................................................................... 613 figure c.6 (a) port a block diagram (pins pa 0 and pa 1 )......................................................... 614 figure c.6 (b) port a block diagram (pins pa 2 and pa 3 )......................................................... 615 figure c.6 (c) port a block diagram (pins pa 4 to pa 7 ) ........................................................... 616 figure c.7 (a) port b block diagram (pins pb 0 and pb 2 ) ......................................................... 617 figure c.7 (b) port b block diagram (pins pb 1 and pb 3 ) ......................................................... 618 figure c.7 (c) port b block diagram (pin pb 4 ) ........................................................................ 619 figure c.7 (d) port b block diagram (pin pb 5 ) ........................................................................ 620 figure c.7 (e) port b block diagram (pin pb 6 ) ........................................................................ 621 figure c.7 (f) port b block diagram (pin pb 7 ) ........................................................................ 622 appendix d pin states figure d.1 reset during memory access (modes 1 and 2).................................................. 626 figure d.2 reset during memory access (modes 3 and 4).................................................. 627 rev.4.00 aug. 20, 2007, page xxxvii of xliv rej09b0395-0400 appendix g package dimensions figure g.1 package dimensions (fp-100b)......................................................................... 630 figure g.2 package dimensions (tfp-100b) ...................................................................... 631 rev.4.00 aug. 20, 2007 page xxxviii of xliv rej09b0395-0400 rev.4.00 aug. 20, 2007, page xxxix of xliv rej09b0395-0400 tables section 1 overview table 1.1 features .............................................................................................................. 2 table 1.2 comparison of h8/3008 pin arrangements ....................................................... 6 table 1.3 pin functions...................................................................................................... 8 table 1.4 pin assignments in each mo de (fp-100b, t fp-100b) ..................................... 12 section 2 cpu table 2.1 instruction classification.................................................................................... 27 table 2.2 instructions and a ddressing m odes ................................................................... 28 table 2.3 data transfer instructions .................................................................................. 30 table 2.4 arithmetic operation instructions ...................................................................... 31 table 2.5 logic operation instructions .............................................................................. 33 table 2.6 shift instructions ................................................................................................ 33 table 2.7 bit manipulation instructions............................................................................. 34 table 2.8 branching instructions........................................................................................ 36 table 2.9 system control instructions ............................................................................... 37 table 2.10 block transfer instruction.................................................................................. 38 table 2.11 addressing modes.............................................................................................. 41 table 2.12 absolute address access ranges....................................................................... 42 table 2.13 effective address calculation ............................................................................ 44 table 2.14 exception handling types and priority ............................................................. 48 section 3 mcu operating modes table 3.1 operating mode selection.................................................................................. 55 table 3.2 registers ............................................................................................................. 56 table 3.3 pin functions in each mode............................................................................... 61 section 4 exception handling table 4.1 exception types and priority ............................................................................. 65 table 4.2 exception vector table...................................................................................... 67 section 5 interrupt controller table 5.1 interrupt pins ...................................................................................................... 77 table 5.2 interrupt controller registers............................................................................. 77 table 5.3 interrupt sources, vector addresses, and priority ............................................. 89 table 5.4 ue, i, and ui bit settings and interrupt handling ............................................. 92 table 5.5 interrupt res ponse time .................................................................................... 98 rev.4.00 aug. 20, 2007 page xl of xliv rej09b0395-0400 section 6 bus controller table 6.1 bus controller pins ............................................................................................ 103 table 6.2 bus controller registers .................................................................................... 104 table 6.3 bus specifications for each area (basic bus interface) .................................... 119 table 6.4 data buses used and valid strobes ................................................................... 124 table 6.5 pin states in idle cycle ...................................................................................... 136 section 7 i/o ports table 7.1 port functions .................................................................................................... 141 table 7.2 port 4 registers .................................................................................................. 145 table 7.3 input pull-up mos transist or states (port 4) ................................................... 147 table 7.4 port 6 registers .................................................................................................. 148 table 7.5 port 6 pin functions in modes 1 to 4 ................................................................. 150 table 7.6 port 7 data register ........................................................................................... 151 table 7.7 port 8 registers .................................................................................................. 153 table 7.8 port 8 pin functions in modes 1 to 4 ................................................................. 155 table 7.9 port 9 registers .................................................................................................. 157 table 7.10 port 9 pin functions ........................................................................................... 159 table 7.11 port a registers ................................................................................................. 162 table 7.12 port a pin functions (modes 1 a nd 2) ............................................................... 165 table 7.13 port a pin functions (modes 3 a nd 4) ............................................................... 167 table 7.14 port a pin functions (modes 1 to 4).................................................................. 169 table 7.15 port b registers.................................................................................................. 173 table 7.16 port b pin functions (modes 1 to 4) .................................................................. 175 section 8 16-bit timer table 8.1 16-bit timer functions ........................................................................................ 178 table 8.2 16-bit timer pins ................................................................................................. 182 table 8.3 16-bit timer registers ......................................................................................... 183 table 8.4 pwm output pins and registers........................................................................ 220 table 8.5 up/down counting conditions.......................................................................... 224 table 8.6 16-bit timer interrupt sources ............................................................................ 229 table 8.7 (a) 16-bit timer operating modes (channel 0) ........................................................ 239 table 8.7 (b) 16-bit timer operating modes (channel 1) ........................................................ 240 table 8.7 (c) 16-bit timer operating modes (channel 2) ........................................................ 241 section 9 8-bit timers table 9.1 8-bit timer pins ................................................................................................. 246 table 9.2 8-bit timer registers ......................................................................................... 247 table 9.3 operation of channels 0 and 1 when bit ice is set to 1 in 8tcsr1 register .. 257 rev.4.00 aug. 20, 2007, page xli of xliv rej09b0395-0400 table 9.4 operation of channels 2 and 3 when bit ice is set to 1 in 8tcsr3 register .. 257 table 9.5 types of 8-bit timer interrupt sources and priority order ............................... 269 table 9.6 8-bit timer interrupt sources............................................................................. 270 table 9.7 timer output priority order............................................................................... 279 table 9.8 internal clock switchover an d 8tcnt operation ............................................. 280 section 10 programmable timi ng pattern controller (tpc) table 10.1 tpc pins............................................................................................................. 285 table 10.2 tpc registers..................................................................................................... 286 table 10.3 tpc operating conditions ................................................................................. 300 section 11 watchdog timer table 11.1 wdt pin ............................................................................................................ 310 table 11.2 wdt registers ................................................................................................... 311 table 11.3 read addresses of tcnt, tcsr, and rstcsr ............................................... 316 section 12 serial co mmunication interface table 12.1 sci pins.............................................................................................................. 324 table 12.2 sci registers...................................................................................................... 325 table 12.3 examples of bit rates and brr settings in async hronous m ode..................... 343 table 12.4 examples of bit rates and brr settings in synchronous mode....................... 346 table 12.5 maximum bit rates for various fre quencies (asynchronous mode) ............... 348 table 12.6 maximum bit rates with external cl ock input (asynchronous mode) ............ 349 table 12.7 maximum bit rates with external cl ock input (synchronous mode)............... 350 table 12.8 smr settings and serial communication formats ............................................ 352 table 12.9 smr and scr settings and sci clock source selection .................................. 352 table 12.10 serial communication formats (asynchronous mode) ..................................... 354 table 12.11 receive error conditions ................................................................................... 361 table 12.12 sci interrupt sources ......................................................................................... 377 table 12.13 ssr status flags and transfer of receive data................................................. 378 section 13 smart card interface table 13.1 smart card interface pins................................................................................... 385 table 13.2 smart card interface registers........................................................................... 385 table 13.3 smart card interface register settings............................................................... 394 table 13.4 n-values of cks1 and cks0 settings ............................................................... 396 table 13.5 bit rates (bits/s) for various brr settings (when n = 0)................................. 396 table 13.6 brr settings for typical bit rates (bits/s) (when n = 0) ................................. 397 table 13.7 maximum bit rates for various frequenc ies (smart card interface mode) ..... 397 table 13.8 smart card interface mode operating states and interrupt sources.................. 404 rev.4.00 aug. 20, 2007 page xlii of xliv rej09b0395-0400 section 14 a/d converter table 14.1 a/d converter pins ............................................................................................ 413 table 14.2 a/d converter registers .................................................................................... 414 table 14.3 analog input channels and a/d data registers (addra to addrd) ........... 415 table 14.4 a/d conversion time (single mode) ................................................................ 426 table 14.5 analog input pin ratings ................................................................................... 429 section 15 d/a converter table 15.1 d/a converter pins ............................................................................................ 437 table 15.2 d/a converter registers .................................................................................... 437 section 16 ram table 16.1 h8/3008 on-chip ram specifications ............................................................. 443 table 16.2 system control register..................................................................................... 444 section 17 clock pulse generator table 17.1 (1) damping resistance value................................................................................. 449 table 17.1 (2) external capacitance values.............................................................................. 450 table 17.2 crystal resonator parameters............................................................................. 450 table 17.3 clock timing (preliminary) ............................................................................... 452 table 17.4 frequency division register .............................................................................. 454 section 18 power-down state table 18.1 power-down state and modul e standby function ............................................ 458 table 18.2 control register ................................................................................................. 459 table 18.3 clock frequency and waiting time for clock to settle .................................... 466 table 18.4 pin state in various operating states ............................................................. 470 section 19 electrical characteristics table 19.1 absolute maximum ratings............................................................................... 471 table 19.2 dc characteristics (1) ........................................................................................ 472 table 19.2 dc characteristics (2) ........................................................................................ 475 table 19.3 permissible output currents............................................................................... 477 table 19.4 clock timi ng...................................................................................................... 479 table 19.5 control signal timing........................................................................................ 480 table 19.6 bus timing......................................................................................................... 481 table 19.7 timing of on-chip su pporting m odules ........................................................... 483 table 19.8 a/d conversion characteristics ......................................................................... 485 table 19.9 d/a conversion characteristics ......................................................................... 487 rev.4.00 aug. 20, 2007, page xliii of xliv rej09b0395-0400 appendix a instruction set table a.1 instruction set..................................................................................................... 499 table a.2 operation code map (1)..................................................................................... 512 table a.2 operation code map (2)..................................................................................... 513 table a.2 operation code map (3)..................................................................................... 514 table a.3 number of states per cycle................................................................................ 516 table a.4 number of cycles per instruction ...................................................................... 517 appendix d pin states table d.1 port states........................................................................................................... 623 appendix f product code lineup table f.1 h8/3008 product code lineup ........................................................................... 629 appendix h comparison of h8/3 00h series produc t specifications table h.1 pin arrangement of each pro duct (fp-100b, t fp-100b) ................................. 635 rev.4.00 aug. 20, 2007 page xliv of xliv rej09b0395-0400 1. overview rev.4.00 aug. 20, 2007 page 1 of 638 rej09b0395-0400 section 1 overview 1.1 overview the h8/3008 is a microcontroller (mcu) that integrates system supporting functions together with an h8/300h cpu core having an original renesas technology architecture. the h8/300h cpu has a 32-bit inte rnal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. it can address a 16-mbyte linear address space. its instruction set is upward-compatible at the object-code level with the h8/300 cpu, enabling easy porting of software from the h8/300 series. the on-chip system supporting functions include ram, a 16-bit timer, an 8-bit timer, a programmable timing pattern controller (tpc), a watchdog timer (wdt), a serial communication interface (sci), an a/d converter, a d/a converter, i/o ports, and other facilities. four mcu operating modes offer a choice of bus width and address space size. the modes (modes 1 to 4) include four expanded modes. table 1.1 summarizes the features of the h8/3008. 1. overview rev.4.00 aug. 20, 2007 page 2 of 638 rej09b0395-0400 table 1.1 features feature description cpu upward-compatible with the h8/300 cpu at the object-code level general-register machine ? sixteen 16-bit general registers (also usable as sixteen 8-bit registers plus eight 16-bit registers, or as eight 32-bit registers) high-speed operation ? maximum clock rate: 25 mhz ? add/subtract: 80 ns ? multiply/divide: 560 ns 16-mbyte address space instruction features ? 8/16/32-bit data transfer, arithmetic, and logic instructions ? signed and unsigned multiply instructions (8 bits 8 bits, 16 bits 16 bits) ? signed and unsigned divide instructions (16 bits 8 bits, 32 bits 16 bits) ? bit accumulator function bit manipulation instructions with register-indirect specification of bit positions memory h8/3008 ? ram: 4 kbytes interrupt controller ? seven external interrupt pins: nmi, irq 0 to irq 5 ? 27 internal interrupts ? three selectable interrupt priority levels bus controller ? address space can be partitioned into eight areas, with independent bus specifications in each area ? chip select output available for areas 0 to 7 ? 8-bit access or 16-bit access selectable for each area ? two-state or three-state access selectable for each area ? selection of two wait modes ? number of program wait states selectable for each area ? bus arbitration function ? two address update modes 1. overview rev.4.00 aug. 20, 2007 page 3 of 638 rej09b0395-0400 feature description 16-bit timer, 3 channels ? three 16-bit timer channels, capable of processing up to six pulse outputs or six pulse inputs ? 16-bit timer counter (channels 0 to 2) ? two multiplexed output compare/input capture pins (channels 0 to 2) ? operation can be synchronized (channels 0 to 2) ? pwm mode available (channels 0 to 2) ? phase counting mode available (channel 2) 8-bit timer, 4 channels ? 8-bit up-counter (external event count capability) ? two time constant registers ? two channels can be connected programmable timing pattern controller (tpc) ? maximum 16-bit pulse output, using 16-bit timer as time base ? up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit groups) ? non-overlap mode available watchdog timer (wdt), 1 channel ? internal reset signal can be generated by overflow ? reset signal can be output externally ? usable as an interval timer serial communication interface (sci), 2 channels ? selection of asynchronous or synchronous mode ? full duplex: can transmit and receive simultaneously ? on-chip baud-rate generator ? smart card interface functions added a/d converter ? resolution: 10 bits ? eight channels, with selection of single or scan mode ? variable analog conversion voltage range ? sample-and-hold function ? a/d conversion can be started by an external trigger or 8-bit timer compare- match d/a converter ? resolution: 8 bits ? two channels ? d/a outputs can be sustained in software standby mode i/o ports ? 35 input/output pins ? 12 input-only pins 1. overview rev.4.00 aug. 20, 2007 page 4 of 638 rej09b0395-0400 feature description operating modes four mcu operating modes mode address space address pins initial bus width max. bus width mode 1 1 mbyte a 19 to a 0 8 bits 16 bits mode 2 1 mbyte a 19 to a 0 16 bits 16 bits mode 3 16 mbytes a 23 to a 0 8 bits 16 bits mode 4 16 mbytes a 23 to a 0 16 bits 16 bits ? on-chip rom is disabled in modes 1 to 4 power-down state ? sleep mode ? software standby mode ? hardware standby mode ? module standby function ? programmable system clock frequency division other features ? on-chip clock pulse generator product lineup product type model package (package code) h8/3008 5 v operation hd6413008f 100-pin qfp (fp-100b) hd6413008te 100-pin tqfp (tfp-100b) 3 v operation hd6413008vf 100-pin qfp (fp-100b) hd6413008vte 100-pin tqfp (tfp-100b) 1. overview rev.4.00 aug. 20, 2007 page 5 of 638 rej09b0395-0400 1.2 block diagram figure 1.1 shows an internal block diagram. v v v v v v v v v cl * cc cc ss ss ss ss ss ss d d d d d d d d p4 /d p4 /d p4 /d p4 /d p4 /d p4 /d p4 /d p4 /d 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 port 3 port 4 port 5 port 9 a a a a 19 18 17 16 a a a a a a a a p9 /sck / irq p9 /sck / irq p9 /rxd p9 /rxd p9 /txd p9 /txd 5 4 3 2 1 0 1 0 1 0 1 0 5 4 da 1 /an 7 /p7 7 da 0 /an 6 /p7 6 an 5 /p7 5 an 4 /p7 4 an 3 /p7 3 an 2 /p7 2 an 1 /p7 1 an 0 /p7 0 port 7 a 20 /tiocb 2 /tp 7 /pa 7 a 21 /tioca 2 /tp 6 /pa 6 a 22 /tiocb 1 /tp 5 /pa 5 a 23 /tioca 1 /tp 4 /pa 4 tclkd/tiocb 0 /tp 3 /pa 3 tclkc/tioca 0 /tp 2 /pa 2 tclkb/tp 1 /pa 1 tclka/tp 0 /pa 0 port a tp 15 /pb 7 tp 14 /pb 6 tp 13 /pb 5 tp 12 /pb 4 cs 4 /tmio 3 /tp 11 /pb 3 cs 5 /tmo 2 /tp 10 /pb 2 cs 6 /tmio 1 /tp 9 /pb 1 cs 7 /tmo 0 /tp 8 /pb 0 port 8 cs 0 /p8 4 adtrg / cs 1 / irq 3 /p8 3 cs 2 / irq 2 /p8 2 cs 3 / irq 1 /p8 1 irq 0 /p8 0 md md md extal xtal stby res reso nmi 2 1 0 h8/300h cpu clock pulse g enerator interrupt controller serial communication interface (sci) 2 channels watchdo g timer (wdt) 15 14 13 12 11 10 9 8 address bus data bus (upper) data bus (lower) 15 14 13 12 11 10 9 8 port 2 a a a a a a a a port 1 7 6 5 4 3 2 1 0 /p6 7 lwr hwr rd as back /p6 2 breq /p6 1 wait /p6 0 ram 16-bit timer unit 8-bit timer unit a/d converter d/a converter port 6 bus controller pro g rammable timin g pattern controller (tpc) port b v ref av cc av ss note: * the 5 v operation models have a v cl pin, and require the connection of an external capacitor. figure 1.1 block diagram 1. overview rev.4.00 aug. 20, 2007 page 6 of 638 rej09b0395-0400 1.3 pin description 1.3.1 pin arrangement the pin arrangement of the h8/3008 is shown in figures 1.2 and 1.3. differences in the h8/3008 pin arrangements are shown in table 1.2. except for the differences shown in table 1.2, the pin arrangements are the same. table 1.2 comparison of h8/3008 pin arrangements h8/3064 f-ztat b-mask version h8/3026 f-ztat h8/3062 f-ztat b-mask version h8/3024 f-ztat h8/3008 romless pin operation model package number 5 v 3 v 5 v 3 v 5 v 3 v 1 v cl v cc v cl v cc v cl v cc fp-100b (tfp-100b) 10 fwe fwe fwe fwe reso reso 1. overview rev.4.00 aug. 20, 2007 page 7 of 638 rej09b0395-0400 v cc /v cl * cs 7 /tmo 0 /tp 8 /pb 0 cs 6 / tmio 1 /tp 9 /pb 1 cs 5 /tmo 2 /tp 10 /pb 2 cs 4 / tmio 3 /tp 11 /pb 3 tp 12 /pb 4 tp 13 /pb 5 tp 14 /pb 6 tp 15 /pb 7 0 1 2 3 4 5 0 1 2 3 4 5 6 reso v ss txd /p9 txd /p9 rxd /p9 rxd /p9 irq /sck /p9 irq /sck /p9 d /p4 d /p4 d /p4 d /p4 d /p4 d /p4 d /p4 md md md lwr hwr rd as v xtal extal v nmi res stby p6 7 / p6 / back p6 / bre q p6 / wait v a 17 a 16 a 15 a 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 0 1 0 1 0 1 0 1 2 3 4 5 6 4 5 2 1 0 2 1 0 cs 2 / irq 2 /p8 2 adtrg / cs 1 / irq 3 /p8 3 cs 0 /p8 4 v ss tclka/tp 0 /pa 0 tclkb/tp 1 /pa 1 tclkc/tioca 0 /tp 2 /pa 2 tclkd/tiocb 0 /tp 3 /pa 3 a 23 /tioca 1 /tp 4 /pa 4 a 22 /tiocb 1 /tp 5 /pa 5 a 21 /tioca 2 /tp 6 /pa 6 a 20 /tiocb 2 /tp 7 /pa 7 /p8 / irq cs /p8 irq av p7 /an /da p7 /an /da p7 /an p7 /an p7 /an p7 /an p7 /an p7 /an v av 1 0 7 6 5 4 3 2 1 0 1 0 7 6 5 4 3 2 1 0 top view (fp-100b, tfp-100b) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 cc ss ss 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ss ref cc 1 0 v ss 3 note: * v cl pin in 5 v operation models, v cc pin in 3 v operation models. an external capacitor must be connected to the v cl pin. 1 0.1 f a 13 a 12 a 11 a 10 a 9 a 8 v ss a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 v cc d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 /p4 7 a 19 a 18 figure 1.2 pin arrangement of h8/3008 (fp-100b or tfp-100b package, top view) 1. overview rev.4.00 aug. 20, 2007 page 8 of 638 rej09b0395-0400 1.3.2 pin functions table 1.3 summarizes the pin functions. the 5 v operation models have a v cl pin, and require the connection of an external capacitor. table 1.3 pin functions pin no. type symbol fp-100b tfp-100b i/o name and function power v cc 1 * , 35, 68 input power: for connection to the power supply. connect all v cc pins to the system power supply. v ss 11, 22, 44, 57, 65, 92 input ground: for connection to ground (0 v). connect all v ss pins to the 0-v system power supply. internal step-down pin v cl 1 * output connect an external capacitor between this pin and gnd (0 v). do not connect to v cc . 0.1 f v cl clock xtal 67 input for connection to a crystal resonator. for examples of crystal resonator and external clock input, see section 20, clock pulse generator. extal 66 input for connection to a crystal resonator or input of an external clock signal. for examples of crystal resonator and external clock input, see section 20, clock pulse generator. 61 output system clock: supplies the system clock to external devices. operating mode control md 2 to md 0 75 to 73 input mode 2 to mode 0: for setting the operating mode, as follows. inputs at these pins must not be changed during operation. md 2 md 1 md 0 operating mode 0 0 0 setting prohibited 0 0 1 mode 1 0 1 0 mode 2 0 1 1 mode 3 1 0 0 mode 4 1 0 1 setting prohibited 1 1 0 setting prohibited 1 1 1 setting prohibited 1. overview rev.4.00 aug. 20, 2007 page 9 of 638 rej09b0395-0400 pin no. type symbol fp-100b tfp-100b i/o name and function res 63 input reset input: when driven low, this pin resets the chip. this pin must be driven low at power-up. system control reso 10 output reset output: outputs the reset signal generated by the watchdog timer to external devices stby 62 input standby: when driven low, this pin forces a transition to hardware standby mode breq 59 input bus request: used by an external bus master to request the bus right back 60 output bus request acknowledge: indicates that the bus has been granted to an external bus master interrupts nmi 64 input nonmaskable interrupt: requests a nonmaskable interrupt irq 5 to irq 0 17, 16, 90 to 87 input interrupt request 5 to 0: maskable interrupt request pins address bus a 23 to a 0 97 to 100, 56 to 45, 43 to 36 output address bus: outputs address signals data bus d 15 to d 0 34 to 23, 21 to 18 input/ output data bus: bidirectional data bus bus control cs 7 to cs 0 2 to 5, 88 to 91 output chip select: select signals for areas 7 to 0 as 69 output address strobe: goes low to indicate valid address output on the address bus rd 70 output read: goes low to indicate reading from the external address space hwr 71 output high write: goes low to indicate writing to the external address space; indicates valid data on the upper data bus (d 15 to d 8 ). lwr 72 output low write: goes low to indicate writing to the external address space; indicates valid data on the lower data bus (d 7 to d 0 ). wait 58 input wait: requests insertion of wait states in bus cycles during access to the external address space 1. overview rev.4.00 aug. 20, 2007 page 10 of 638 rej09b0395-0400 pin no. type symbol fp-100b tfp-100b i/o name and function 16-bit timer tclkd to tclka 96 to 93 input clock input d to a: external clock inputs tioca 2 to tioca 0 99, 97, 95 input/ output input capture/output compare a2 to a0: gra2 to gra0 output compare or input capture, or pwm output tiocb 2 to tiocb 0 100, 98, 96 input/ output input capture/output compare b2 to b0: grb2 to grb0 output compare or input capture 8-bit timer tmo 0 , tmo 2 2, 4 output compare match output: compare match output pins tmio 1 , tmio 3 3, 5 input/ output input capture input/compare match output: input capture input or compare match output pins tclkd to tclka 96 to 93 input counter external clock input: these pins input an external clock to the counters. program- mable timing pattern controller (tpc) tp 15 to tp 0 9 to 2, 100 to 93 output tpc output 15 to 0: pulse output txd 1 , txd 0 13, 12 output transmit data (channels 0, 1): sci data output rxd 1 , rxd 0 15, 14 input receive data (channels 0, 1): sci data input serial com- munication interface (sci) sck 1 , sck 0 17, 16 input/ output serial clock (channels 0, 1): sci clock input/output a/d converter an 7 to an 0 85 to 78 input analog 7 to 0: analog input pins adtrg 90 input a/d conversion external trigger input: external trigger input for starting a/d conversion d/a converter da 1 , da 0 85, 84 output analog output: analog output from the d/a converter 1. overview rev.4.00 aug. 20, 2007 page 11 of 638 rej09b0395-0400 pin no. type symbol fp-100b tfp-100b i/o name and function analog power supply av cc 76 input power supply pin for the a/d and d/a converters. connect to the system power supply when not using the a/d and d/a converters. av ss 86 input ground pin for the a/d and d/a converters. connect to system ground (0 v). v ref 77 input reference voltage input pin for the a/d and d/a converters. connect to the system power supply when not using the a/d and d/a converters. i/o ports p4 7 to p4 0 26 to 23, 21 to 18 input/ output port 4: eight input/output pins. the direction of each pin can be selected in the port 4 data direction register (p4ddr). p6 7 , p6 5 to p6 0 61, 60 to 58 input/ output port 6: eight input/output pins. the direction of each pin can be selected in the port 6 data direction register (p6ddr). p7 7 to p7 0 85 to 78 input port 7: eight input pins p8 4 to p8 0 91 to 87 input/ output port 8: five input/output pins. the direction of each pin can be selected in the port 8 data direction register (p8ddr). p9 5 to p9 0 17 to 12 input/ output port 9: six input/output pins. the direction of each pin can be selected in the port 9 data direction register (p9ddr). pa 7 to pa 0 100 to 93 input/ output port a: eight input/output pins. the direction of each pin can be selected in the port a data direction register (paddr). pb 7 to pb 0 9 to 2 input/ output port b: eight input/output pins. the direction of each pin can be selected in the port b data direction register (pbddr). note: * in 5 v operation models. this is a v cc pin in 3 v operation models. 1. overview rev.4.00 aug. 20, 2007 page 12 of 638 rej09b0395-0400 1.3.3 pin assignments in each mode table 1.4 lists the pin assignments in each mode. table 1.4 pin assignments in each mode (fp-100b, tfp-100b) pin no. pin name fp-100b tfp-100b mode 1 mode 2 mode 3 mode 4 1 v cc (v cl ) * 3 v cc (v cl ) * 3 v cc (v cl ) * 3 v cc (v cl ) * 3 2 pb 0 /tp 8 /tmo 0 / cs 7 pb 0 /tp 8 /tmo 0 / cs 7 pb 0 /tp 8 /tmo 0 / cs 7 pb 0 /tp 8 /tmo 0 / cs 7 3 pb 1 /tp 9 /tmio 1 / cs 6 pb 1 /tp 9 /tmio 1 / cs 6 pb 1 /tp 9 /tmio 1 / cs 6 pb 1 /tp 9 /tmio 1 / cs 6 4 pb 2 /tp 10 /tmo 2 / cs 5 pb 2 /tp 10 /tmo 2 / cs 5 pb 2 /tp 10 /tmo 2 / cs 5 pb 2 /tp 10 /tmo 2 / cs 5 5 pb 3 /tp 11 /tmio 3 / cs 4 pb 3 /tp 11 /tmio 3 / cs 4 pb 3 /tp 11 /tmio 3 / cs 4 pb 3 /tp 11 /tmio 3 / cs 4 6 pb 4 /tp 12 pb 4 /tp 12 pb 4 /tp 12 pb 4 /tp 12 7 pb 5 /tp 13 pb 5 /tp 13 pb 5 /tp 13 pb 5 /tp 13 8 pb 6 /tp 14 pb 6 /tp 14 pb 6 /tp 14 pb 6 /tp 14 9 pb 7 /tp 15 pb 7 /tp 15 pb 7 /tp 15 pb 7 /tp 15 10 reso reso reso reso 11 v ss v ss v ss v ss 12 p9 0 /txd 0 p9 0 /txd 0 p9 0 /txd 0 p9 0 /txd 0 13 p9 1 /txd 1 p9 1 /txd 1 p9 1 /txd 1 p9 1 /txd 1 14 p9 2 /rxd 0 p9 2 /rxd 0 p9 2 /rxd 0 p9 2 /rxd 0 15 p9 3 /rxd 1 p9 3 /rxd 1 p9 3 /rxd 1 p9 3 /rxd 1 16 p9 4 /sck 0 / irq 4 p9 4 /sck 0 / irq 4 p9 4 /sck 0 / irq 4 p9 4 /sck 0 / irq 4 17 p9 5 /sck 1 / irq 5 p9 5 /sck 1 / irq 5 p9 5 /sck 1 / irq 5 p9 5 /sck 1 / irq 5 18 p4 0 /d 0 * 1 p4 0 /d 0 * 2 p4 0 /d 0 * 1 p4 0 /d 0 * 2 19 p4 1 /d 1 * 1 p4 1 /d 1 * 2 p4 1 /d 1 * 1 p4 1 /d 1 * 2 20 p4 2 /d 2 * 1 p4 2 /d 2 * 2 p4 2 /d 2 * 1 p4 2 /d 2 * 2 21 p4 3 /d 3 * 1 p4 3 /d 3 * 2 p4 3 /d 3 * 1 p4 3 /d 3 * 2 22 v ss v ss v ss v ss 23 p4 4 /d 4 * 1 p4 4 /d 4 * 2 p4 4 /d 4 * 1 p4 4 /d 4 * 2 24 p4 5 /d 5 * 1 p4 5 /d 5 * 2 p4 5 /d 5 * 1 p4 5 /d 5 * 2 25 p4 6 /d 6 * 1 p4 6 /d 6 * 2 p4 6 /d 6 * 1 p4 6 /d 6 * 2 26 p4 7 /d 7 * 1 p4 7 /d 7 * 2 p4 7 /d 7 * 1 p4 7 /d 7 * 2 27 d 8 d 8 d 8 d 8 1. overview rev.4.00 aug. 20, 2007 page 13 of 638 rej09b0395-0400 pin no. pin name fp-100b tfp-100b mode 1 mode 2 mode 3 mode 4 28 d 9 d 9 d 9 d 9 29 d 10 d 10 d 10 d 10 30 d 11 d 11 d 11 d 11 31 d 12 d 12 d 12 d 12 32 d 13 d 13 d 13 d 13 33 d 14 d 14 d 14 d 14 34 d 15 d 15 d 15 d 15 35 v cc v cc v cc v cc 36 a 0 a 0 a 0 a 0 37 a 1 a 1 a 1 a 1 38 a 2 a 2 a 2 a 2 39 a 3 a 3 a 3 a 3 40 a 4 a 4 a 4 a 4 41 a 5 a 5 a 5 a 5 42 a 6 a 6 a 6 a 6 43 a 7 a 7 a 7 a 7 44 v ss v ss v ss v ss 45 a 8 a 8 a 8 a 8 46 a 9 a 9 a 9 a 9 47 a 10 a 10 a 10 a 10 48 a 11 a 11 a 11 a 11 49 a 12 a 12 a 12 a 12 50 a 13 a 13 a 13 a 13 51 a 14 a 14 a 14 a 14 52 a 15 a 15 a 15 a 15 53 a 16 a 16 a 16 a 16 54 a 17 a 17 a 17 a 17 55 a 18 a 18 a 18 a 18 56 a 19 a 19 a 19 a 19 57 v ss v ss v ss v ss 58 p6 0 / wait p6 0 / wait p6 0 / wait p6 0 / wait 1. overview rev.4.00 aug. 20, 2007 page 14 of 638 rej09b0395-0400 pin no. pin name fp-100b tfp-100b mode 1 mode 2 mode 3 mode 4 59 p6 1 / breq p6 1 / breq p6 1 / breq p6 1 / breq 60 p6 2 / back p6 2 / back p6 2 / back p6 2 / back 61 62 stby stby stby stby 63 res res res res 64 nmi nmi nmi nmi 65 v ss v ss v ss v ss 66 extal extal extal extal 67 xtal xtal xtal xtal 68 v cc v cc v cc v cc 69 as as as as 70 rd rd rd rd 71 hwr hwr hwr hwr 72 lwr lwr lwr lwr 73 md 0 md 0 md 0 md 0 74 md 1 md 1 md 1 md 1 75 md 2 md 2 md 2 md 2 76 av cc av cc av cc av cc 77 v ref v ref v ref v ref 78 p7 0 /an 0 p7 0 /an 0 p7 0 /an 0 p7 0 /an 0 79 p7 1 /an 1 p7 1 /an 1 p7 1 /an 1 p7 1 /an 1 80 p7 2 /an 2 p7 2 /an 2 p7 2 /an 2 p7 2 /an 2 81 p7 3 /an 3 p7 3 /an 3 p7 3 /an 3 p7 3 /an 3 82 p7 4 /an 4 p7 4 /an 4 p7 4 /an 4 p7 4 /an 4 83 p7 5 /an 5 p7 5 /an 5 p7 5 /an 5 p7 5 /an 5 84 p7 6 /an 6 /da 0 p7 6 /an 6 /da 0 p7 6 /an 6 /da 0 p7 6 /an 6 /da 0 85 p7 7 /an 7 /da 1 p7 7 /an 7 /da 1 p7 7 /an 7 /da 1 p7 7 /an 7 /da 1 86 av ss av ss av ss av ss 87 p8 0 / irq 0 p8 0 / irq 0 p8 0 / irq 0 p8 0 / irq 0 88 p8 1 / irq 1 / cs 3 p8 1 / irq 1 / cs 3 p8 1 / irq 1 / cs 3 p8 1 / irq 1 / cs 3 89 p8 2 / irq 2 / cs 2 p8 2 / irq 2 / cs 2 p8 2 / irq 2 / cs 2 p8 2 / irq 2 / cs 2 1. overview rev.4.00 aug. 20, 2007 page 15 of 638 rej09b0395-0400 pin no. pin name fp-100b tfp-100b mode 1 mode 2 mode 3 mode 4 90 p8 3 / irq 3 / cs 1 / adtrg p8 3 / irq 3 / cs 1 / adtrg p8 3 / irq 3 / cs 1 / adtrg p8 3 / irq 3 / cs 1 / adtrg 91 p8 4 / cs 0 p8 4 / cs 0 p8 4 / cs 0 p8 4 / cs 0 92 v ss v ss v ss v ss 93 pa 0 /tp 0 /tclka pa 0 /tp 0 /tclka pa 0 /tp 0 /tclka pa 0 /tp 0 /tclka 94 pa 1 /tp 1 /tclkb pa 1 /tp 1 /tclkb pa 1 /tp 1 /tclkb pa 1 /tp 1 /tclkb 95 pa 2 /tp 2 /tioca 0 / tclkc pa 2 /tp 2 /tioca 0 / tclkc pa 2 /tp 2 /tioca 0 / tclkc pa 2 /tp 2 /tioca 0 / tclkc 96 pa 3 /tp 3 /tiocb 0 / tclkd pa 3 /tp 3 /tiocb 0 / tclkd pa 3 /tp 3 /tiocb 0 / tclkd pa 3 /tp 3 /tiocb 0 / tclkd 97 pa 4 /tp 4 /tioca 1 pa 4 /tp 4 /tioca 1 pa 4 /tp 4 /tioca 1 /a 23 pa 4 /tp 4 /tioca 1 /a 23 98 pa 5 /tp 5 /tiocb 1 pa 5 /tp 5 /tiocb 1 pa 5 /tp 5 /tiocb 1 /a 22 pa 5 /tp 5 /tiocb 1 /a 22 99 pa 6 /tp 6 /tioca 2 pa 6 /tp 6 /tioca 2 pa 6 /tp 6 /tioca 2 /a 21 pa 6 /tp 6 /tioca 2 /a 21 100 pa 7 /tp 7 /tiocb 2 pa 7 /tp 7 /tiocb 2 a 20 a 20 notes: 1. in modes 1 and 3 the p4 0 to p4 7 functions of pins p4 0 /d 0 to p4 7 /d 7 are selected after a reset, but they can be changed by software. 2. in modes 2 and 4 the d 0 to d 7 functions of pins p4 0 /d 0 to p4 7 /d 7 are selected after a reset, but they can be changed by software. 3. this pin functions as v cl in 5 v operation models, and as v cc in 3 v operation models. 1. overview rev.4.00 aug. 20, 2007 page 16 of 638 rej09b0395-0400 2. cpu rev.4.00 aug. 20, 2007 page 17 of 638 rej09b0395-0400 section 2 cpu 2.1 overview the h8/300h cpu is a high-speed cen tral processing unit with an internal 32-bit architecture that is upward-compatible with the h8/300 cpu. the h8/300h cpu has sixteen 16-bit general registers, can address a 16-mbyte linear addr ess space, and is ideal for realtime control. 2.1.1 features the h8/300h cpu has th e following features. ? upward compatibility with h8/300 cpu can execute h8/300 series object programs ? general-register architecture sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) ? 64 basic instructions ? 8/16/32-bit arithmetic and logic instructions ? multiply and divide instructions ? powerful bit-manipulation instructions ? eight addressing modes ? register direct [rn] ? register indirect [@ern] ? register indirect with displacemen t [@(d:16, ern) or @(d:24, ern)] ? register indirect with post-increment or pre-decrement [@ern+ or @?ern] ? absolute address [@aa:8, @aa:16, or @aa:24] ? immediate [#xx:8, #xx:16, or #xx:32] ? program-counter relative [@(d:8, pc) or @(d:16, pc)] ? memory indirect [@@aa:8] ? 16-mbyte linear address space ? high-speed operation ? all frequently-used instructions execute in two to four states ? maximum clock frequency: 25 mhz ? 8/16/32-bit register-register add/subtract: 80 ns@25 mhz ? 8 8-bit register-register multiply: 560 ns@25 mhz ? 16 8-bit register-register divide: 560 ns@25 mhz ? 16 16-bit register-register multiply: 880 ns@25 mhz 2. cpu rev.4.00 aug. 20, 2007 page 18 of 638 rej09b0395-0400 ? 32 16-bit register-register divide: 880 ns@25 mhz ? two cpu operating modes ? normal mode ? advanced mode ? low-power mode transition to power-down state by sleep instruction 2.1.2 differences from h8/300 cpu in comparison to the h8/300 cpu, the h8/300h cpu has the following enhancements. ? more general registers eight 16-bit registers have been added. ? expanded address space ? advanced mode supports a maximum 16-mbyte address space. ? normal mode supports the same 64-kbyt e address space as the h8/300 cpu. ? enhanced addressing the addressing modes have been enhanced to make effective use of the 16-mbyte address space. ? enhanced instructions ? data transfer, arithmetic, and logic instructions can operate on 32-bit data. ? signed multiply/divide instructions and other instructions have been added. 2.2 cpu operating modes the h8/300h cpu has two operating modes: normal and advanced. normal mode supports a maximum 64-kbyte address space. advanced mode supports up to 16 mbytes. cpu operatin g modes normal mode advanced mode maximum 64 kbytes, pro g ram and data areas combined maximum 16 mbytes, pro g ram and data areas combined figure 2.1 cpu operating modes 2. cpu rev.4.00 aug. 20, 2007 page 19 of 638 rej09b0395-0400 2.3 address space figure 2.2 shows a simple memory map for the h8/3008. the h8/300h cpu can address a linear address space with a maximum size of 64 kbytes in normal mode, and 16 mbytes in advanced mode. for further details see section 3.6, memory map in each operating mode. the 1-mbyte operating modes use 20-bit addressing. the upper 4 bits of effective addresses are ignored. h'00000 h'fffff h'000000 h'ffffff a. 1-mbyte mode b. 16-mbyte mode h'0000 h'ffff advanced mode normal mode figure 2.2 memory map 2. cpu rev.4.00 aug. 20, 2007 page 20 of 638 rej09b0395-0400 2.4 register configuration 2.4.1 overview the h8/300h cpu has the internal registers shown in figure 2.3. there are two types of registers: general registers and control registers. er0 er1 er2 er3 er4 er5 er6 er7 e0 e1 e2 e3 e4 e5 e6 e7 r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l 0 7 0 7 0 15 (sp) 23 0 pc 7 ccr 6543210 iuihunzvc general registers (ern) control registers (cr) le g end: sp: pc: ccr: i: ui: h: u: n: z: v: c: stack pointer pro g ram counter condition code re g ister interrupt mask bit user bit or interrupt mask bit half-carry fla g user bit ne g ative fla g zero fla g overflow fla g carry fla g figure 2.3 cpu registers 2. cpu rev.4.00 aug. 20, 2007 page 21 of 638 rej09b0395-0400 2.4.2 general registers the h8/300h cpu has eight 32-bit general registers. these general registers are all functionally alike and can be used without distinction between data registers and address registers. when a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. when the general registers are used as 32-bit regist ers or as address registers, they are designated by the letters er (er0 to er7). the er registers divide into 16-bit general registers designated by the letters e (e0 to e7) and r (r0 to r7). these registers are functionally equivalent, providing a maximum sixteen 16-bit registers. the e registers (e0 to e7) are also referred to as extended registers. the r registers divide into 8-bit general register s designated by the letters rh (r0h to r7h) and rl (r0l to r7l). these registers are functionally equivalent, providing a maximum sixteen 8-bit registers. figure 2.4 illustrates the usage of the general registers. the usage of each register can be selected independently. ? address re g isters ? 32-bit re g isters ? 16-bit re g isters ? 8-bit re g isters er re g isters er0 to er7 e re g isters (extended re g isters) e0 to e7 r re g isters r0 to r7 rh re g isters r0h to r7h rl re g isters r0l to r7l figure 2.4 usage of general registers general register er7 has the function of stack poi nter (sp) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. figure 2.5 shows the stack. 2. cpu rev.4.00 aug. 20, 2007 page 22 of 638 rej09b0395-0400 free area stack area sp (er7) figure 2.5 stack 2.4.3 control registers the control registers are the 24-bit program coun ter (pc) and the 8-bit condition code register (ccr). program counter (pc): this 24-bit counter indicates the address of the next instruction the cpu will execute. the length of all cpu instructions is 2 bytes (one word), so the least significant pc bit is ignored. when an instruction is fetched, the least significant pc bit is regarded as 0. condition code register (ccr): this 8-bit register contains internal cpu status information, including the interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. bit 7?interrupt mask bit (i): masks interrupts other than nmi when set to 1. nmi is accepted regardless of the i bit setting. the i bit is set to 1 at the start of an exception-handling sequence. bit 6?user bit or interrupt mask bit (ui): can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. this bit can also be used as an interrupt mask bit. for details see section 5, interrupt controller. bit 5?half-carry flag (h): when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is executed, this flag is set to 1 if th ere is a carry or borrow at bit 3, and cleared to 0 otherwise. when the add.w, sub.w, cmp.w, or neg.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. when the add.l, sub.l, cmp.l, or neg.l instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. bit 4?user bit (u): can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. bit 3?negative flag (n): stores the value of the most significant bit of data, regarded as the sign bit. 2. cpu rev.4.00 aug. 20, 2007 page 23 of 638 rej09b0395-0400 bit 2?zero flag (z): set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. bit 1?overflow flag (v): set to 1 when an arithmetic overflo w occurs, and cleared to 0 at other times. bit 0?carry flag (c): set to 1 when a carry is generated by execution of an operation, and cleared to 0 otherwise. used by: ? add instructions, to indicate a carry ? subtract instructions , to indicate a borrow ? shift and rotate instructions the carry flag is also used as a bit accumulator by bit manipulation instructions. some instructions leave flag bits unchanged. operations can be performed on ccr by the ldc, stc, andc, orc, and xorc instructions. the n, z, v, and c flags are used by conditional branch (bcc) instructions. for the action of each instruction on the flag bits , see appendix a.1, instruction list. for the i and ui bits, see section 5, interrupt controller. 2.4.4 initial cpu register values in reset exception handling, pc is initialized to a value loaded from the vector table, and the i bit in ccr is set to 1. the other ccr bits and the general registers are not initialized. in particular, the initial value of the stack pointer (er7) is also undefined. the stack pointer (er7) must therefore be initialized by an mov.l instruction executed immediately after a reset. 2. cpu rev.4.00 aug. 20, 2007 page 24 of 638 rej09b0395-0400 2.5 data formats the h8/300h cpu can process 1-bit, 4-bit (bcd), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. bit-manipul ation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ?, 7) of byte operand data. the daa and das decimal-adjust instructions treat byte data as two digits of 4-bit bcd data. 2.5.1 general register data formats figures 2.6 and 2.7 show the data formats in general registers. 7 rnh rnl rnh rnl rnh rnl 1-bit data 1-bit data 4-bit bcd data 4-bit bcd data byte data byte data 6543210 70 don't care 76543210 70 don't care don't care 70 43 lower di g it upper di g it 7 43 lower di g it upper di g it don't care 0 70 don't care msb lsb don't care 70 msb lsb data type data format general register le g end: rnh: general re g ister rh rnl: general re g ister rl msb: most si g nificant bit lsb: least si g nificant bit figure 2.6 general re gister data formats (1) 2. cpu rev.4.00 aug. 20, 2007 page 25 of 638 rej09b0395-0400 rn en ern word data word data lon g word data 15 0 msb lsb general register data type data format 15 0 msb lsb 31 16 msb 15 0 lsb le g end: ern: en: rn: msb: lsb: general re g ister general re g ister e general re g ister r most si g nificant bit least si g nificant bit figure 2.7 general re gister data formats (2) 2.5.2 memory data formats figure 2.8 shows the data formats on memory . the h8/300h cpu can access word data and longword data on memory, but word or longword data must begin at an even address. if an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at th e preceding address. this also applies to instruction fetches. 2. cpu rev.4.00 aug. 20, 2007 page 26 of 638 rej09b0395-0400 76543210 address l address l lsb msb msb lsb 70 msb lsb 1-bit data byte data word data lon g word data address data type data format address 2m address 2m + 1 address 2n address 2n + 1 address 2n + 2 address 2n + 3 figure 2.8 memory data formats when er7 (sp) is used as an address register to access the stack, the operand size should be word size or longword size. 2. cpu rev.4.00 aug. 20, 2007 page 27 of 638 rej09b0395-0400 2.6 instruction set 2.6.1 instruction set overview the h8/300h cpu has 64 types of instructions, which are classified in table 2.1. table 2.1 instructio n classification function instruction types data transfer mov, push * 1 , pop * 1 , movtpe * 2 , movfpe * 2 5 arithmetic operations add, sub, addx, su bx, inc, dec, adds, subs, daa, das, mulxu, mulxs, divxu, divxs, cmp, neg, exts, extu 18 logic operations and, or, xor, not 4 shift operations shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr 8 bit manipulation bset, bclr, bnot, btst , band, biand, bor, bior, bxor, bixor, bld, bild, bst, bist 14 branch bcc * 3 , jmp, bsr, jsr, rts 5 system control trapa, rte, sleep, ldc, stc, andc, orc, xorc, nop 9 block data transfer eepmov 1 total 64 types notes: 1. pop.w rn is identical to mov.w @sp+, rn. push.w rn is identical to mov.w rn, @?sp. pop.l ern is identical to mov.l @sp+, rn. push.l ern is identical to mov.l rn, @?sp. 2. not available in the h8/3008. 3. bcc is a generic branching instruction. 2. cpu rev.4.00 aug. 20, 2007 page 28 of 638 rej09b0395-0400 2.6.2 instructions and addressing modes table 2.2 indicates the instructions available in the h8/300h cpu. table 2.2 instructions and addressing modes addressing modes function instruction #xx rn @ern @ (d:16, ern) @ (d:24, ern) @ern+/ @?ern @ aa:8 @ aa:16 @ aa:24 @ (d:8, pc) @ (d:16, pc) @@ aa:8 ? mov bwl bwl bwl bwl bwl bwl b bwl bwl ? ? ? ? data transfer pop, push ? ? ? ? ? ? ? ? ? ? ? ? wl movfpe, ? ? ? ? ? ? ? ? ? ? ? ? ? movtpe add, cmp bwl bwl ? ? ? ? ? ? ? ? ? ? ? arithmetic operations sub wl bwl ? ? ? ? ? ? ? ? ? ? ? addx, subx b b ? ? ? ? ? ? ? ? ? ? ? adds, subs ? l ? ? ? ? ? ? ? ? ? ? ? inc, dec ? bwl ? ? ? ? ? ? ? ? ? ? ? daa, das ? b ? ? ? ? ? ? ? ? ? ? ? mulxu, ? bw ? ? ? ? ? ? ? ? ? ? ? mulxs, divxu, divxs neg ? bwl ? ? ? ? ? ? ? ? ? ? ? extu, exts ? wl ? ? ? ? ? ? ? ? ? ? ? logic operations and, or, xor ? bwl ? ? ? ? ? ? ? ? ? ? ? not ? bwl ? ? ? ? ? ? ? ? ? ? ? shift instructions ? bwl ? ? ? ? ? ? ? ? ? ? ? bit manipulation ? b b ? ? ? b ? ? ? ? ? ? branch bcc, bsr ? ? ? ? ? ? ? ? ? ? ? ? ? jmp, jsr ? ? ? ? ? ? ? ? ? ? rts ? ? ? ? ? ? ? ? ? ? ? trapa ? ? ? ? ? ? ? ? ? ? ? ? system control rte ? ? ? ? ? ? ? ? ? ? ? ? sleep ? ? ? ? ? ? ? ? ? ? ? ? ldc b b w w w w ? w w ? ? ? stc ? b w w w w ? w w ? ? ? ? andc, orc, xorc b ? ? ? ? ? ? ? ? ? ? ? ? nop ? ? ? ? ? ? ? ? ? ? ? ? block data transfer ? ? ? ? ? ? ? ? ? ? ? ? bw 2. cpu rev.4.00 aug. 20, 2007 page 29 of 638 rej09b0395-0400 2.6.3 tables of instructions classified by function tables 2.3 to 2.10 summarize the instructions in each functional category. the operation notation used in these tables is defined next. operation notation rd general register (destination) * rs general register (source) * rn general register * ern general register (32-bit register or address register) * (ead) destination operand (eas) source operand ccr condition code register n n (negative) flag of ccr z z (zero) flag of ccr v v (overflow) flag of ccr c c (carry) flag of ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition ? subtraction multiplication division and logical or logical exclusive or logical move ? not (logical complement) :3/:8/:16/:24 3-, 8-, 16-, or 24-bit length note: * general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit data or address registers (er0 to er7). 2. cpu rev.4.00 aug. 20, 2007 page 30 of 638 rej09b0395-0400 table 2.3 data transfer instructions instruction size * function mov b/w/l (eas) rd, rs (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. movfpe b (eas) rd cannot be used in the h8/3008. movtpe b rs (eas) cannot be used in the h8/3008. pop w/l @sp+ rn pops a general register from the stack. pop.w rn is identical to mov.w @sp+, rn. similarly, pop.l ern is identical to mov.l @sp+, ern. push w/l rn @ ? sp pushes a general register onto the stack. push.w rn is identical to mov.w rn, @ ? sp. similarly, push.l ern is identical to mov.l ern, @ ? sp. note: * size refers to the operand size. b: byte w: word l: longword 2. cpu rev.4.00 aug. 20, 2007 page 31 of 638 rej09b0395-0400 table 2.4 arithmetic operation instructions instruction size * function add,sub b/w/l rd rs rd, rd #imm rd performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (immediate byte data cannot be subtracted from data in a general register. use the subx or add instruction.) addx, subx b rd rs c rd, rd #imm c rd performs addition or subtraction with carry or borrow on data in two general registers, or on immediate data and data in a general register. inc, dec b/w/l rd 1 rd, rd 2 rd increments or decrements a general register by 1 or 2. (byte operands can be incremented or decremented by 1 only.) adds, subs l rd 1 rd, rd 2 rd, rd 4 rd adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. daa, das b rd decimal adjust rd decimal-adjusts an addition or subtracti on result in a general register by referring to ccr to produce 4-bit bcd data. mulxu b/w rd rs rd performs unsigned multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. mulxs b/w rd rs rd performs signed multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. 2. cpu rev.4.00 aug. 20, 2007 page 32 of 638 rej09b0395-0400 instruction size * function divxu b/w rd rs rd performs unsigned division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16-bit remainder divxs b/w rd rs rd performs signed division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder, or 32 bits 16 bits 16-bit quotient and 16-bit remainder cmp b/w/l rd ? rs, rd ? #imm compares data in a general register with data in another general register or with immediate data, and sets ccr according to the result. neg b/w/l 0 ? rd rd takes the two's complement (arithmetic complement) of data in a general register. exts w/l rd (sign extension) rd extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by extending the sign bit. extu w/l rd (zero extension) rd extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by padding with zeros. note: * size refers to the operand size. b: byte w: word l: longword 2. cpu rev.4.00 aug. 20, 2007 page 33 of 638 rej09b0395-0400 table 2.5 logic opera tion instructions instruction size * function and b/w/l rd rs rd, rd #imm rd performs a logical and operation on a general register and another general register or immediate data. or b/w/l rd rs rd, rd #imm rd performs a logical or operation on a general register and another general register or immediate data. xor b/w/l rd rs rd, rd #imm rd performs a logical exclusive or operation on a general register and another general register or immediate data. not b/w/l ? rd rd takes the one's complement (logical complement) of general register contents. note: * size refers to the operand size. b: byte w: word l: longword table 2.6 shift instructions instruction size * function shal, shar b/w/l rd (shift) rd performs an arithmetic shift on general register contents. shll, shlr b/w/l rd (shift) rd performs a logical shift on general register contents. rotl, rotr b/w/l rd (rotate) rd rotates general register contents. rotxl, rotxr b/w/l rd (rotate) rd rotates general register contents, including the carry bit. note: * size refers to the operand size. b: byte w: word l: longword 2. cpu rev.4.00 aug. 20, 2007 page 34 of 638 rej09b0395-0400 table 2.7 bit manipulation instructions instruction size * function bset b 1 ( 2. cpu rev.4.00 aug. 20, 2007 page 35 of 638 rej09b0395-0400 instruction size * function bor b c ( 2. cpu rev.4.00 aug. 20, 2007 page 36 of 638 rej09b0395-0400 table 2.8 branching instructions instruction size function bcc ? branches to a specified address if address specified condition is met. the branching conditions are listed below. mnemonic description condition bra (bt) always (true) always brn (bf) never (false) never bhi high c z = 0 bls low or same c z = 1 bcc (bhs) carry clear (high or same) c = 0 bcs (blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n v = 0 blt less than n v = 1 bgt greater than z (n v) = 0 ble less or equal z (n v) = 1 jmp ? branches unconditionally to a specified address bsr ? branches to a subroutine at a specified address jsr ? branches to a subroutine at a specified address rts ? returns from a subroutine 2. cpu rev.4.00 aug. 20, 2007 page 37 of 638 rej09b0395-0400 table 2.9 system co ntrol instructions instruction size * function trapa ? starts trap-instruction exception handling rte ? returns from an exception-handling routine sleep ? causes a transition to the power-down state ldc b/w (eas) ccr moves the source operand contents to the condition code register. the condition code register size is one byte, but in transfer from memory, data is read by word access. stc b/w ccr (ead) transfers the ccr contents to a destination location. the condition code register size is one byte, but in transfe r to memory, data is written by word access. andc b ccr #imm ccr logically ands the condition code register with immediate data. orc b ccr #imm ccr logically ors the condition code register with immediate data. xorc b ccr #imm ccr logically exclusive-ors the condition code register with immediate data. nop ? pc + 2 pc only increments the program counter. note: * size refers to the operand size. b: byte w: word 2. cpu rev.4.00 aug. 20, 2007 page 38 of 638 rej09b0395-0400 table 2.10 block transfer instruction instruction size function eepmov.b ? if r4l 0 then repeat @er5+ @er6+, r4l ? 1 r4l until r4l = 0 else next; eepmov.w ? if r4 0 then repeat @er5+ @er6+, r4 ? 1 r4 until r4 = 0 else next; block transfer instruction. this instruction transfers the number of data bytes specified by r4l or r4, starting from the address indicated by er5, to the location starting at the address indicated by er6. at the end of the transfer, the next instruction is executed. 2.6.4 basic instruction formats the h8/300h instructions consist of 2-byte (word) units. an instruction consists of an operation field (op field), a register field (r field), an effective address ex tension (ea field), and a condition field (cc). operation field: indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. the operation field always includes the first 4 bits of the instruction. some instructions have two operation fields. register field: specifies a general register. address regist ers are specified by 3 bits, data registers by 3 bits or 4 bits. some instructions have two register fields. some have no register field. effective address extension: eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. a 24-bit address or di splacement is treated as 32-bit data in which the first 8 bits are 0 (h'00). condition field: specifies the branching condition of bcc instructions. figure 2.9 shows examples of instruction formats. 2. cpu rev.4.00 aug. 20, 2007 page 39 of 638 rej09b0395-0400 op nop, rts, etc. op rn rm op rn rm ea (disp) operation field only add.b rn, rm, etc. operation field and re g ister fields mov.b @(d:16, rn), rm operation field, re g ister fields, and effective address extension bra d:8 operation field, effective address extension, and condition field op cc ea (disp) figure 2.9 instruction formats 2.6.5 notes on use of bit manipulation instructions the bset, bclr, bnot, bst, and bist instructions read a byte of data, modify a bit in the byte, then write the byte back. care is required wh en these instructions are used to access registers with write-only bits, or to access ports. step description 1 read read one data byte at the specified address 2 modify modify one bit in the data byte 3 write write the modified data byte back to the specified address example 1: bclr is executed to clear bit 0 in the port 4 data direction register (p4ddr) under the following conditions. p4 7 , p4 6 : input pins p4 5 ? p4 0 : output pins the intended purpose of this bclr instruction is to switch p4 0 from output to input. 2. cpu rev.4.00 aug. 20, 2007 page 40 of 638 rej09b0395-0400 before execution of bclr instruction p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 input/output input input output output output output output output ddr 0 0 1 1 1 1 1 1 execution of bclr instruction bclr #0, @p4ddr ; execute bclr instruction on ddr after execution of bclr instruction p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 input/output output output output output output output output input ddr 1 1 1 1 1 1 1 0 explanation: to execute the bclr instruction, the cpu begins by reading p4ddr. since p4ddr is a write-only register, it is read as h'ff, even though its true value is h'3f. next the cpu clears bit 0 of the read data, changing the value to h'fe. finally, the cpu writes this value (h'fe) back to p4ddr to complete the bclr instruction. as a result, p4 0 ddr is cleared to 0, making p4 0 an input pin. in addition, p4 7 ddr and p4 6 ddr are set to 1, making p4 7 and p4 6 output pins. the bclr instruction can be used to clear flags in the on-chip registers to 0. in the case of the irq status register (isr), for example, a flag mu st be read as a condition for clearing it, but when using the bclr instruction, if it is known that a flag has been set to 1 in an interrupt-handling routine, for instance, it is not necessa ry to read the fl ag ahead of time. 2. cpu rev.4.00 aug. 20, 2007 page 41 of 638 rej09b0395-0400 2.7 addressing modes and eff ective address calculation 2.7.1 addressing modes the h8/300h cpu supports the eight addressing modes listed in table 2.11. each instruction uses a subset of these addressing modes. arithmetic and logic instructions can use the register direct and immediate modes. data transfer instructi ons can use all addressing modes except program- counter relative and memory indirect. bit manipulation instructions use register direct, register indirect, or absolute (@aa:8) addressing mode to specify an operand, and register direct (bset, bclr, bnot, and btst instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. table 2.11 addressing modes no. addressing mode symbol 1 register direct rn 2 register indirect @ern 3 register indirect with displacement @(d:16, ern)/@(d:24, ern) 4 register indirect with post-increment register indirect with pre-decrement @ern+ @ ? ern 5 absolute address @aa:8/@aa:16/@aa:24 6 immediate #xx:8/#xx:16/#xx:32 7 program-counter relative @(d:8, pc)/@(d:16, pc) 8 memory indirect @@aa:8 register direct?rn: the register field of the instruction code specifies an 8-, 16-, or 32-bit register containing the operand. r0h to r7h and r0l to r7l can be specified as 8-bit registers. r0 to r7 and e0 to e7 can be specified as 16-bit registers. er0 to er7 can be specified as 32-bit registers. register indirect?@ern: the register field of the instructi on code specifies an address register (ern), the lower 24 bits of which contain the address of the operand. register indirect with displacement? @(d:16, ern) or @(d:24, ern): a 16-bit or 24-bit displacement contained in the inst ruction code is added to the contents of an address register (ern) specified by the register field of the instruction, and the lower 24 bits of the sum specify the address of a memory operand. a 16-bit displacement is sign-extended when added. 2. cpu rev.4.00 aug. 20, 2007 page 42 of 638 rej09b0395-0400 register indirect with po st-increment or pre-decrem ent?@ern+ or @?ern: ? register indirect with post-increment?@ern+ the register field of the instru ction code specifies an address register (ern) the lower 24 bits of which contain the address of a memory operand. after the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register. the value added is 1 for byte access, 2 for word access, or 4 for longword access. for word or longword access, the register value should be even. ? register indirect with pre-decrement?@?ern the value 1, 2, or 4 is subtracted from an address register (ern) specified by the register field in the instruction code, and the lower 24 bits of the result become the address of a memory operand. the result is also stored in the addre ss register. the value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. for word or longword access, the resulting register value should be even. absolute address?@aa:8, @aa:16, or @aa:24: the instruction code contains the absolute address of a memory operand. the absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), or 24 bits long (@aa:24). for an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (h 'ffff). for a 16-bit absolute address th e upper 8 bits are a sign extension. a 24-bit absolute address can acce ss the entire address space. table 2.12 indicates the accessible address ranges. table 2.12 absolute address access ranges absolute address 1-mbyte modes 16-mbyte modes 8 bits (@aa:8) h'fff00 to h'fffff (1048320 to 1048575) h'ffff00 to h'ffffff (16776960 to 16777215) 16 bits (@aa:16) h'00000 to h'07fff, h'f8000 to h'fffff (0 to 32767, 1015808 to 1048575) h'000000 to h'007fff, h'ff8000 to h'ffffff (0 to 32767, 16744448 to 16777215) 24 bits (@aa:24) h'00000 to h'fffff (0 to 1048575) h'000000 to h'ffffff (0 to 16777215) immediate?#xx:8, #xx:16, or #xx:32: the instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. the instruction codes of the adds, subs, inc, and dec instructions contain immediate data implicitly. the instruction codes of some bit manipulation instructions contain 3-bit immediate data specifying a bit number. the trapa instruction code contains 2-bit immediate data specifying a vector address. 2. cpu rev.4.00 aug. 20, 2007 page 43 of 638 rej09b0395-0400 program-counter relative?@(d:8, pc) or @(d:16, pc): this mode is used in the bcc and bsr instructions. an 8-bit or 16-bit displacement contained in the instruction code is sign- extended to 24 bits and added to the 24-bit pc contents to generate a 24-bit branch address. the pc value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is ?126 to +128 bytes (?63 to +64 words) or ?32766 to +32768 bytes (?16383 to +16384 words) from the branch instruction. the resulting value should be an even number. memory indirect?@@aa:8: this mode can be used by the jmp and jsr instructions. the instruction code contains an 8-bit absolute address specifying a memory operand. this memory operand contains a branch address. the memory operand is accessed by longword access. the first byte of the memory operand is ignored, generating a 24-bit branch address. see figure 2.10. the upper bits of the 8-bit absolute address are assume d to be 0 (h'0000), so the address range is 0 to 255 (h'000000 to h'0000ff). note that the first part of this range is also the exception vector area. for further details see section 5, interrupt controller. specified by @aa:8 reserved branch address figure 2.10 memory-indirect branch address specification when a word-size or longword-size memory operand is specified, or when a branch address is specified, if the specified memory address is odd, the least significant bit is regarded as 0. the accessed data or instruction code therefore begins at the preceding address. see section 2.5.2, memory data formats. 2.7.2 effective address calculation table 2.13 explains how an effective address is calculated in each addressing mode. in the 1-mbyte operating modes the upper 4 bits of the calculated address are ignored in order to generate a 20-bit effective address. 2. cpu rev.4.00 aug. 20, 2007 page 44 of 638 rej09b0395-0400 table 2.13 effective address calculation addressing mode and instru c tion format no. effe c tive address cal c ulation effe c tive address re g ister direct (rn) 1 operand is g eneral re g ister contents op rm rn re g ister indirect (@ern) 2 op r general re g ister contents 31 0 23 0 re g ister indirect with displacement @(d:16, ern)/@(d:24, ern) 3 op r general re g ister contents 31 0 23 0 si g n extension disp re g ister indirect with post-increment or pre-decrement 4 general re g ister contents 31 0 23 0 1, 2, or 4 op r general re g ister contents 31 0 23 0 1, 2, or 4 op r re g ister indirect with post-increment @ern+ re g ister indirect with pre-decrement @?ern 1 for a byte operand, 2 for a word operand, 4 for a lon g word operand 2. cpu rev.4.00 aug. 20, 2007 page 45 of 638 rej09b0395-0400 addressing mode and instru c tion format no. effe c tive address cal c ulation effe c tive address absolute address @aa:8 5 op pro g ram-counter relative @(d:8, pc) or @(d:16, pc) 7 0 23 0 abs 23 0 87 @aa:16 @aa:24 op abs 23 0 16 15 h'ffff si g n extension op 23 0 abs immediate #xx:8, #xx:16, or #xx:32 6 operand is immediate data op disp 23 0 pc contents disp op imm si g n extension 2. cpu rev.4.00 aug. 20, 2007 page 46 of 638 rej09b0395-0400 addressing mode and instru c tion format no. effe c tive address cal c ulation effe c tive address 8 le g end: r, rm, rn: op: disp: imm: abs: re g ister field operation field displacement immediate data absolute address memory indirect @@aa:8 8 op 23 0 abs 23 0 87 h'0000 15 0 abs 16 15 normal mode op 23 0 abs 23 0 87 h'0000 0 abs advanced mode 31 h'00 memory contents memory contents 2. cpu rev.4.00 aug. 20, 2007 page 47 of 638 rej09b0395-0400 2.8 processing states 2.8.1 overview the h8/300h cpu has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-rel eased state. the power-down state includes sleep mode, software standby mode, and hardware stan dby mode. figure 2.11 classifies the processing states. figure 2.13 indicates the state transitions. processin g states pro g ram execution state bus-released state reset state power-down state the cpu executes pro g ram instructions in sequence a transient state in which the cpu executes a hardware sequence (savin g pc and ccr, fetchin g a vector, etc.) in response to a reset, interrupt, or other exception the external bus has been released in response to a bus request si g nal from a bus master other than the cpu the cpu and all on-chip supportin g modules are initialized and halted the cpu is halted to conserve power sleep mode software standby mode hardware standby mode exception-handlin g state figure 2.11 processing states 2.8.2 program execution state in this state the cpu executes program instructions in normal sequence. 2. cpu rev.4.00 aug. 20, 2007 page 48 of 638 rej09b0395-0400 2.8.3 exception-handling state the exception-handling state is a transient state that occurs when the cp u alters the normal program flow due to a reset, interrupt, or trap instruction. the cpu fetches a starting address from the exception vector table and bran ches to that address. in inte rrupt and trap exception handling the cpu references the stack pointer (er7) a nd saves the program counter and condition code register. types of exception handling and their priority: exception handling is performed for resets, interrupts, and trap instructions. table 2.14 indicates the types of exception handling and their priority. trap instruc tion exceptions are accepted at all tim es in the program execution state. table 2.14 exception handling types and priority priority type of exception detection timing start of exception handling high reset synchronized with clock exception handling starts immediately when res changes from low to high interrupt end of instruction execution or end of exception handling * when an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence low trap instruction when trapa instruction is executed exception handling starts when a trap (trapa) instruction is executed note: * interrupts are not detected at the end of the andc, orc, xorc, and ldc instructions, or immediately after reset exception handling. figure 2.12 classifies the exception sources. for further details about exception sources, vector numbers, and vector addresses, see section 4, exception handling, and section 5, interrupt controller. exception sources reset interrupt trap instruction external interrupts internal interrupts (from on-chip supportin g modules) figure 2.12 classificati on of exception sources 2. cpu rev.4.00 aug. 20, 2007 page 49 of 638 rej09b0395-0400 bus-released state exception-handlin g state reset state * 1 pro g ram execution state sleep mode software standby mode hardware standby mode * 2 power-down state bus request end of bus release end of bus release bus request end of exception handlin g exception handlin g source interrupt source sleep instruction with ssby = 0 sleep instruction with ssby = 1 nmi, irq , irq , or irq interrupt stby = "hi g h", res = "low" res = "hi g h" 01 2 notes: 1. 2. from any state except hardware standby mode, a transition to the reset state occurs whenever res g oes low. from any state, a transition to hardware standby mode occurs when stby g oes low. figure 2.13 state transitions 2.8.4 exception handling operation reset exception handling: reset exception handling has the highest priority. the reset state is entered when the res signal goes low. reset exception handling starts after that, when res changes from low to high. when reset exception handling starts the cpu fetches a start address from the exception vector table and starts program execution from that address. all interrupts, including nmi, are disabled during the reset exception-handling sequence and immediately after it ends. interrupt exception handling and trap instruction exception handling: when these exception-handling sequences begin, the cpu references the stack pointer (er7) and pushes the program counter and condition code register on the stack. next, if the ue bit in the system control register (syscr) is set to 1, the cpu sets the i bit in the condition code register to 1. if the ue bit is cleared to 0, the cpu sets both the i bit and the ui bit in the condition code register to 1. then 2. cpu rev.4.00 aug. 20, 2007 page 50 of 638 rej09b0395-0400 the cpu fetches a start address from the exception vector table and execu tion branches to that address. figure 2.14 shows the stack afte r the exception-handling sequence. sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp (er7) before exception handlin g starts sp (er7) sp+1 sp+2 sp+3 sp+4 after exception handlin g ends stack area ccr pc even address pushed on stack le g end: ccr: sp: condition code re g ister stack pointer notes: 1. 2. pc is the address of the first instruction executed after the return from the exception-handlin g routine. re g isters must be saved and restored by word access or lon g word access, startin g at an even address. figure 2.14 stack structu re after exception handling 2.8.5 bus-released state in this state the bus is released to a bus master other than the cpu, in response to a bus request. the bus masters other than the cpu is an external bus master. while the bus is released, the cpu halts except for internal operations. interrupt reque sts are not accepted. for details see section 6.6, bus arbiter. 2.8.6 reset state when the res input goes low all current processing stops and the cpu enters the reset state. the i bit in the condition code register is set to 1 by a reset. all interrupts are masked in the reset state. reset exception handling starts when the res signal changes from low to high. 2. cpu rev.4.00 aug. 20, 2007 page 51 of 638 rej09b0395-0400 the reset state can also be entered by a watc hdog timer overflow. for details see section 11, watchdog timer. 2.8.7 power-down state in the power-down state the cpu stops operating to conserve power. there are three modes: sleep mode, software standby mode, and hardware standby mode. sleep mode: a transition to sleep mode is made if the sleep instruction is executed while the ssby bit is cleared to 0 in the system control register (syscr). cpu operations stop immediately after execu tion of the sleep instruction, but the contents of cpu registers are retained. software standby mode: a transition to software standby mode is made if the sleep instruction is executed while the ssby bit is set to 1 in syscr. the cpu and clock halt and all on-chip supporting modules stop operating. the on-chip supporting modules are reset, but as long as a specified voltage is supplied the contents of cpu registers and on-chip ram are retained. the i/o ports also remain in their existing states. hardware standby mode: a transition to hardware standby mode is made when the stby input goes low. as in software standby mode, the cpu and all clocks halt and the on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip ram contents are retained. for further information see section 18, power-down state. 2.9 basic operational timing 2.9.1 overview the h8/300h cpu operates accord ing to the system clock ( ). the interval from one rise of the system clock to the next rise is referred to as a ?state.? a memory cycle or bus cycle consists of two or three states. the cpu uses different methods to access on-chip memory, the on-chip supporting modules, and the external address space. access to the external address space can be controlled by the bus controller. 2.9.2 on-chip memory access timing on-chip memory is accessed in two states. the data bus is 16 bits wide, permitting both byte and word access. figure 2.15 shows the on-chip memory access cycle. figure 2. 16 indicates the pin states. the h8/3008 has a function for changing the method of outputting addresses from the address pins. for details see section 6.3.5, address output method. 2. cpu rev.4.00 aug. 20, 2007 page 52 of 638 rej09b0395-0400 t state bus cycle internal address bus internal read si g nal internal data bus (read access) internal write si g nal internal data bus (write access) 1 t state 2 read data address write data figure 2.15 on-chip memory access cycle t , , , as 1 t 2 address bus d to d 15 0 rd hwr lwr hi g h address hi g h impedance figure 2.16 pin states during on-chip memory access (address update mode 1) 2.9.3 on-chip supporting module access timing the on-chip supporting modules are accessed in thr ee states. the data bus is 8 or 16 bits wide, depending on the internal i/o register being accessed. figure 2. 17 shows the on-chip supporting module access timing. figure 2. 18 indicates the pin states. 2. cpu rev.4.00 aug. 20, 2007 page 53 of 638 rej09b0395-0400 address bus internal read si g nal internal data bus internal write si g nal address internal data bus t state bus cycle 1 t state 2 t state 3 read access write access write data read data figure 2.17 access cycle fo r on-chip supporting modules t , , , as 1 t 2 address bus d to d 15 0 rd hwr lwr hi g h hi g h impedance t 3 address figure 2.18 pin states during access to on-chip supporting modules 2.9.4 access to external address space the external address space is divided into eight areas (areas 0 to 7). bus-controller settings determine whether each area is accessed via an 8-b it or 16-bit data bus, and whether it is accessed in two or three states. for details see section 6, bus controller. 2. cpu rev.4.00 aug. 20, 2007 page 54 of 638 rej09b0395-0400 3. mcu operating modes rev.4.00 aug. 20, 2007 page 55 of 638 rej09b0395-0400 section 3 mcu operating modes 3.1 overview 3.1.1 operating mode selection the h8/3008 has four operating modes (modes 1 to 4) that are selected by the mode pins (md 2 to md 0 ) as indicated in table 3.1. the input at these pins determines the size of the address space and the initial bus mode. table 3.1 operating mode selection description mode pins operating mode md 2 md 1 md 0 address space initial bus mode * 1 on-chip rom on-chip ram ? 0 0 0 setting prohibited setting prohibited setting prohibited setting prohibited mode 1 0 0 1 expanded mode 8 bits disabled enabled * 2 mode 2 0 1 0 expanded mode 16 bits disabled enabled * 2 mode 3 0 1 1 expanded mode 8 bits disabled enabled * 2 mode 4 1 0 0 expanded mode 16 bits disabled enabled * 2 ? 1 0 1 setting prohibited setting prohibited setting prohibited setting prohibited ? 1 1 0 setting prohibited setting prohibited setting prohibited setting prohibited ? 1 1 1 setting prohibited setting prohibited setting prohibited setting prohibited notes: 1. in modes 1 to 4, an 8-bit or 16-bit data bus can be selected on a per-area basis by settings made in the area bus width control register (abwcr). for details see section 6, bus controller. 2. if the rame bit in syscr is cleared to 0, these addresses become external addresses. for the address space size there are two choices: 1 mbyte or 16 mbyte. the external data bus is either 8 or 16 bits wide depending on abwcr sett ings. 8-bit bus mode is used only if 8-bit access is selected for all areas. for details see section 6, bus controller. 3. mcu operating modes rev.4.00 aug. 20, 2007 page 56 of 638 rej09b0395-0400 modes 1 to 4 are externally expanded modes that enable access to external memory and peripheral devices and disable access to the on-chip rom. modes 1 and 2 support a maximum address space of 1 mbyte. modes 3 and 4 support a maximum address space of 16 mbytes. the h8/3008 can be used only in modes 1 to 4. the inputs at the mode pins must select one of these four modes. the inputs at the mode pins must not be changed during operation. set the reset state before changing the inputs at these pins. 3.1.2 register configuration the h8/3008 has a mode control register (mdcr) that indicates the inputs at the mode pins (md 2 to md 0 ), and a system control register (syscr ). table 3.2 summarizes these registers. table 3.2 registers address * name abbreviation r/w initial value h'ee011 mode control register mdcr r undetermined h'ee012 system control register syscr r/w h'09 note: * lower 20 bits of the address in advanced mode. 3.2 mode control register (mdcr) mdcr is an 8-bit read-only register that indicates the current operating mode of the h8/3008. bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 0 ? 4 ? 0 ? 3 ? 0 ? 0 mds0 ? r * 2 mds2 ? r 1 mds1 ? r ** mode sele c t 2 to 0 bits indicatin g the current operatin g mode reserved bits note: determined by pins md to md . * 20 bits 7 and 6?reserved: these bits can not be modified and are always read as 1. bits 5 to 3?reserved: these bits can not be modified and are always read as 0. bits 2 to 0?mode select 2 to 0 (mds2 to mds0): these bits indicate the logic levels at pins md 2 to md 0 (the current operating mode). mds2 to mds0 correspond to md 2 to md 0 . mds2 to 3. mcu operating modes rev.4.00 aug. 20, 2007 page 57 of 638 rej09b0395-0400 mds0 are read-only bits. the mode pin (md 2 to md 0 ) levels are latched into these bits when mdcr is read. 3.3 system control register (syscr) syscr is an 8-bit register that controls the operation of the h8/3008. bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ue 1 r/w 0 rame 1 r/w 2 nmieg 0 r/w 1 ssoe 0 r/w software standby enables transition to software standby mode user bit enable selects whether to use the ui bit in ccr as a user bit or an interrupt mask bit nmi edge sele c t selects the valid ed g e of the nmi input ram enable enables or disables on-chip ram standby timer sele c t 2 to 0 these bits select the waitin g time at recovery from software standby mode selects the output state of the address bus and bus control si g nals in software standby mode software standby output port enable 3. mcu operating modes rev.4.00 aug. 20, 2007 page 58 of 638 rej09b0395-0400 bit 7?software standby (ssby): enables transition to software standby mode. (for further information about software standby mode see section 18, power-down state.) when software standby mode is exited by an external interrupt, and a transition is made to normal operation, this bit remains set to 1. to clear this bit, write 0. bit 7 ssby description 0 sleep instruction causes transition to sleep mode (initial value) 1 sleep instruction causes transition to software standby mode bits 6 to 4?standby timer select 2 to 0 (sts2 to sts0): these bits select the length of time the cpu and on-chip supporting modules wait for the internal clock oscillator to settle when software standby mode is exited by an external interrupt. when using a crystal oscillator, set these bits so that the waiting time will be at least 7 ms at the system clock rate. for further information about wa iting time selection, see secti on 18.4.3, selection of waiting time for exit from software standby mode. bit 6 sts2 bit 5 sts1 bit 4 sts0 description 0 0 0 waiting time = 8,192 states (initial value) 0 0 1 waiting time = 16,384 states 0 1 0 waiting time = 32,768 states 0 1 1 waiting time = 65,536 states 1 0 0 waiting time = 131,072 states 1 0 1 waiting time = 262,144 states 1 1 0 waiting time = 1,024 states 1 1 1 illegal setting 3. mcu operating modes rev.4.00 aug. 20, 2007 page 59 of 638 rej09b0395-0400 bit 3?user bit enable (ue): selects whether to use the ui bit in the condition code register as a user bit or an interrupt mask bit. bit 3 ue description 0 ui bit in ccr is used as an interrupt mask bit 1 ui bit in ccr is used as a user bit (initial value) bit 2?nmi edge select (nmieg): selects the valid edge of the nmi input. bit 2 nmieg description 0 an interrupt is requested at the falling edge of nmi (initial value) 1 an interrupt is requested at the rising edge of nmi bit 1?software standby output port enable (ssoe): specifies whether the address bus and bus control signals ( cs 0 to cs 7 , as , rd , hwr , lwr ) are kept as outputs or fixed high, or placed in the high-impedance state in software standby mode. bit 1 ssoe description 0 in software standby mode, the address bus and bus control signals are all high- impedance (initial value) 1 in software standby mode, the address bus retains its output state and bus control signals are fixed high bit 0?ram enable (rame): enables or disables the on-chip ram. the rame bit is initialized by the rising edge of the res signal. it is not initialized in software standby mode. bit 0 rame description 0 on-chip ram is disabled 1 on-chip ram is enabled (initial value) 3. mcu operating modes rev.4.00 aug. 20, 2007 page 60 of 638 rej09b0395-0400 3.4 operating mode descriptions 3.4.1 mode 1 ports 1, 2, and 5 function as address pins a 19 to a 0 , permitting access to a maximum 1-mbyte address space. the initial bus mode after a reset is 8 bits, with 8-bit access to all areas. if at least one area is designated for 16-bit access in ab wcr, the bus mode switches to 16 bits. 3.4.2 mode 2 ports 1, 2, and 5 function as address pins a 19 to a 0 , permitting access to a maximum 1-mbyte address space. the initial bus mode after a reset is 16 bits, with 16-bit access to all areas. if all areas are designated for 8-bit access in ab wcr, the bus mode switches to 8 bits. 3.4.3 mode 3 ports 1, 2, and 5 and part of port a function as address pins a 23 to a 0 , permitting access to a maximum 16-mbyte address space. the initial bus mode after a reset is 8 bits, with 8-bit access to all areas. if at least one area is designated for 16-bit access in abwcr, the bus mode switches to 16 bits. a 23 to a 21 are valid when 0 is written in bits 7 to 5 of the bus release control register (brcr). (in this mode a 20 is always used for address output.) 3.4.4 mode 4 ports 1, 2, and 5 and part of port a function as address pins a 23 to a 0 , permitting access to a maximum 16-mbyte address space. the initial bus mode after a reset is 16 bits, with 16-bit access to all areas. if all areas are designated for 8-b it access in abwcr, the bus mode switches to 8 bits. a 23 to a 21 are valid when 0 is written in bits 7 to 5 of brcr. (in this mode a 20 is always used for address output.) 3.4.5 modes 5 to 7 these modes cannot be used in the h8/3008. pin settings must not be made for these modes. 3. mcu operating modes rev.4.00 aug. 20, 2007 page 61 of 638 rej09b0395-0400 3.5 pin functions in each operating mode the pin functions of ports 1 to 5 and port a va ry depending on the operating mode. table 3.3 indicates their functions in each operating mode. table 3.3 pin functions in each mode port mode 1 mode 2 mode 3 mode 4 port 1 a 7 to a 0 a 7 to a 0 a 7 to a 0 a 7 to a 0 port 2 a 15 to a 8 a 15 to a 8 a 15 to a 8 a 15 to a 8 port 3 d 15 to d 8 d 15 to d 8 d 15 to d 8 d 15 to d 8 port 4 p4 7 to p4 0 * 1 d 7 to d 0 * 1 p4 7 to p4 0 * 1 d 7 to d 0 * 1 port 5 a 19 to a 16 a 19 to a 16 a 19 to a 16 a 19 to a 16 port a pa 7 to pa 4 pa 7 to pa 4 pa 6 to pa 4 , a 20 * 2 pa 6 to pa 4 , a 20 * 2 notes: 1. initial state. the bus mode can be switched by settings in abwcr. these pins function as p4 7 to p4 0 in 8-bit bus mode, and as d 7 to d 0 in 16-bit bus mode. 2. initial state. a 20 is always an address output pin. pa 6 to pa 4 are switched over to a 23 to a 21 output by writing 0 in bits 7 to 5 of brcr. 3. mcu operating modes rev.4.00 aug. 20, 2007 page 62 of 638 rej09b0395-0400 3.6 memory map in each operating mode figure 3.1 shows memory map of the h8/3008. in the expanded modes, the address space is divided into eight areas. the initial bus mode differs between modes 1 and 2, and also between modes 3 and 4. the address locations of the on-chip ram and on-chip registers differ between the 1-mbyte modes (modes 1 and 2) and the 16-mbyte modes (modes 3 and 4). the address range specifiable by the cpu in the 8- and 16-bit absolute addressing modes (@aa:8 and @aa:16) also differs. 3.6.1 reserved areas the h8/3008 memory map includes reserved areas to which access (reading or writing) is prohibited. normal operation cannot be guaranteed if the following reserved areas are accessed. reserved area in internal i/o register space: the h8/3008 internal i/ o register space includes a reserved area to which access is prohibited. for details see appendix b, internal i/o registers. 3. mcu operating modes rev.4.00 aug. 20, 2007 page 63 of 638 rej09b0395-0400 h'00000 h'000ff h'07fff memory-indirect branch addresses 16-bit absolute addresses modes 1 and 2 (1-mbyte expanded modes with on-chip rom disabled) h'1ffff h'20000 h'3ffff h'40000 h'5ffff h'60000 h'7ffff h'80000 h'9ffff h'a0000 h'bffff h'c0000 h'dffff h'e0000 area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 external address space external address space vector area on-chip ram * on-chip ram * 8-bit absolute addresses 16-bit absolute addresses h'f8000 h'fef1f h'fef20 h'fff00 h'fff1f h'fff20 h'fffe9 h'fffea h'fffff modes 3 and 4 (16-mbyte expanded modes with on-chip rom disabled) h'000000 h'0000ff h'007fff memory-indirect branch addresses 16-bit absolute addresses h'1fffff h'200000 area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 external address space vector area external address space 8-bit absolute addresses 16-bit absolute addresses h'ff8000 h'ffef1f h'ffef20 h'ffff1f h'ffff20 h'ffff00 h'ffffe9 h'ffffea h'ffffff h'3fffff h'400000 h'5fffff h'600000 h'7fffff h'800000 h'9fffff h'a00000 h'bfffff h'c00000 h'dfffff h'e00000 h'fee000 h'fee0ff note: * external addresses can be accessed by disablin g on-chip ram. internal i/o re g isters (1) internal i/o re g isters (1) internal i/o re g isters (2) internal i/o re g isters (2) external address space h'ee000 h'ee0ff external address space figure 3.1 memory map of h8/3008 in each operating mode 3. mcu operating modes rev.4.00 aug. 20, 2007 page 64 of 638 rej09b0395-0400 4. exception handling rev.4.00 aug. 20, 2007 page 65 of 638 rej09b0395-0400 section 4 exception handling 4.1 overview 4.1.1 exception handling types and priority as table 4.1 indicates, exception handling may be caused by a reset, interrupt, or trap instruction. exception handling is prioritized as shown in table 4.1. if two or more exceptions occur simultaneously, they are accepted and processed in pr iority order. trap in struction exceptions are accepted at all times in the program execution state. table 4.1 exception types and priority priority exception type start of exception handling high reset starts immediately after a low-to-high transition at the res pin interrupt interrupt requests are handled when execution of the current instruction or handling of the current exception is completed low trap instruction (trapa) started by ex ecution of a trap instruction (trapa) 4.1.2 exception handling operation exceptions originate from various sources. trap instructions and interrupts are handled as follows. 1. the program counter (pc) and condition code register (ccr) are pushed onto the stack. 2. the ccr interrupt mask bit is set to 1. 3. a vector address corresponding to the exception source is generated, and program execution starts from that address. note: for a reset exception, steps 2 and 3 above are carried out. 4. exception handling rev.4.00 aug. 20, 2007 page 66 of 638 rej09b0395-0400 4.1.3 exception vector table the exception sources are classified as shown in figure 4.1. different vectors are assigned to different exception sources. table 4.2 lists the exception sources and their vector addresses. exception sources ? reset ? interrupts ? trap instruction external interrupts: internal interrupts: nmi, irq to irq 27 interrupts from on-chip supportin g modules 0 5 figure 4.1 exception sources 4. exception handling rev.4.00 aug. 20, 2007 page 67 of 638 rej09b0395-0400 table 4.2 exception vector table vector address * 1 exception source vector number advanced mode normal mode reset 0 h'0000 to h'0003 h'0000 to h'0001 reserved for system use 1 h'0004 to h'0007 h'0002 to h'0003 2 h'0008 to h'000b h'0004 to h'0005 3 h'000c to h'000f h'0006 to h'0007 4 h'0010 to h'0013 h'0008 to h'0009 5 h'0014 to h'0017 h'000a to h'000b 6 h'0018 to h'001b h'000c to h'000d external interrupt (nmi) 7 h'001c to h'001f h'000e to h'000f trap instruction (4 sources) 8 h'0020 to h'0023 h'0010 to h'0011 9 h'0024 to h'0027 h'0012 to h'0013 10 h'0028 to h'002b h'0014 to h'0015 11 h'002c to h'002f h'0016 to h'0017 external interrupt irq 0 12 h'0030 to h'0033 h'0018 to h'0019 external interrupt irq 1 13 h'0034 to h'0037 h'001a to h'001b external interrupt irq 2 14 h'0038 to h'003b h'001c to h'001d external interrupt irq 3 15 h'003c to h'003f h'001e to h'001f external interrupt irq 4 16 h'0040 to h'0043 h'0020 to h'0021 external interrupt irq 5 17 h'0044 to h'0047 h'0022 to h'0023 reserved for system use 18 h'0048 to h'004b h'0024 to h'0025 19 h'004c to h'004f h'0026 to h'0027 internal interrupts * 2 20 to 63 h'0050 to h'0053 to h'00fc to h'00ff h'0028 to h'0029 to h'007e to h'007f notes: 1. lower 16 bits of the address. 2. for the internal interrupt vectors, see section 5.3.3, interrupt vector table. 4. exception handling rev.4.00 aug. 20, 2007 page 68 of 638 rej09b0395-0400 4.2 reset 4.2.1 overview a reset is the highest-priority exception. when the res pin goes low, all processing halts and the chip enters the reset state. a reset initializes the internal state of the cpu and the registers of the on-chip supporting modules. reset exception handling begins when the res pin changes from low to high. the chip can also be reset by overflow of the watchdog timer. for details see section 11, watchdog timer. 4.2.2 reset sequence the chip enters the reset state when the res pin goes low. to ensure that the chip is reset, hold the res pin low for at least 20 ms at power-up. to reset the chip during operation, hold the res pin low for at least 10 system clock ( ) cycles. in the versions with on-chip flash memory, the res pin must be held low for at least 20 system clock cycles. see appendix d.2, pin states at reset, for the states of the pins in the reset state. when the res pin goes high after being held low for the necessary time, the chip starts reset exception handling as follows. ? the internal state of the cpu and the registers of the on-chip supporting modules are initialized, and the i bit is set to 1 in ccr. ? the contents of the reset vector address (h'0000 to h'0003 in advanced mode, h'0000 to h'0001 in normal mode) are read, and program execution starts from the address indicated in the vector address. figure 4.2 shows the reset sequence in modes 1 and 3. figure 4.3 shows the reset sequence in modes 2 and 4. 4. exception handling rev.4.00 aug. 20, 2007 page 69 of 638 rej09b0395-0400 address bus res rd hwr d to d 15 8 vector fetch internal processin g prefetch of first pro g ram instruction (1), (3), (5), (7) (2), (4), (6), (8) (9) (10) note: after a reset, the wait-state controller inserts three wait states in every bus cycle. address of reset exception handlin g vector: (1) = h'000000, (3) = h'000001, (5) = h'000002, (7) = h'000003 start address (contents of reset exception handlin g vector address) start address first instruction of pro g ram hi g h (1) (3) (5) (7) (9) (2) (4) (6) (8) (10) lwr , figure 4.2 reset sequence (modes 1 and 3) 4. exception handling rev.4.00 aug. 20, 2007 page 70 of 638 rej09b0395-0400 address bus res rd hwr d to d 15 0 vector fetch internal processin g prefetch of first pro g ram instruction (1), (3) (2), (4) (5) (6) note: after a reset, the wait-state controller inserts three wait states in every bus cycle. hi g h lwr , address of reset exception handlin g vector: (1) = h'000000, (3) = h'000002 start address (contents of reset exception handlin g vector address) start address first instruction of pro g ram (2) (4) (3) (1) (5) (6) figure 4.3 reset sequence (modes 2 and 4) 4.2.3 interrupts after reset if an interrupt is accepted after a reset but before the stack pointer (sp) is initialized, pc and ccr will not be saved correctly, leading to a program crash. to prevent this, all interrupt requests, including nmi, are disabled immediately after a reset exception handling. the first instruction of the program is always executed i mmediately after the reset state ends. this instruction should initialize the stack pointer (example: mov.l #xx:32, sp). 4. exception handling rev.4.00 aug. 20, 2007 page 71 of 638 rej09b0395-0400 4.3 interrupts interrupt exception handling can be requested by seven external sources (nmi, irq 0 to irq 5 ), and 27 internal sources in the on-chip supporting modules. figure 4.4 classifies the interrupt sources and indicates the number of interrupts of each type. the on-chip supporting modules that can request interrupts are the watchdog timer (wdt), 16-bit timer, 8-bit timer, serial communication interface (sci), and a/d converter. each interrupt source has a separate vector address. nmi is the highest-priority interrupt and is al ways accepted. interrupts are controlled by the interrupt controller. the interrupt controller can assign interrupts other than nmi to two priority levels, and arbitrate between simultaneous interrupts. interrupt priorities are assigned in interrupt priority registers a and b (ipra and iprb) in the interrupt controller. for details on interrupts see section 5, interrupt controller. interrupts external interrupts internal interrupts nmi (1) irq to irq (6) wdt * (1) 16-bit timer (9) 8-bit timer (8) sci (8) a/d converter (1) notes: numbers in parentheses are the number of interrupt sources. * when the watchdo g timer is used as an interval timer, it g enerates an interrupt request at every counter overflow. 0 5 figure 4.4 interrupt sou rces and number of interrupts 4.4 trap instruction trap instruction exception handling starts when a trapa instruction is executed. if the ue bit is set to 1 in the system control register (syscr), the exception handling sequence sets the i bit to 1 in ccr. if the ue bit is 0, the i and ui bits are both set to 1 in ccr. the trapa instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, which is specified in the instruction code. 4. exception handling rev.4.00 aug. 20, 2007 page 72 of 638 rej09b0395-0400 4.5 stack status after exception handling figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp (er7) sp (er7) sp+1 sp+2 sp+3 sp+4 sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp (er7) sp (er7) sp+1 sp+2 sp+3 sp+4 before exception handlin g before exception handlin g after exception handlin g stack area stack area ccr ccr pc pc ccr pc pc pc h l e h l * after exception handlin g even address even address pushed on stack pushed on stack a. normal mode b. advanced mode le g end: pc e : pc h : pc l : ccr: sp: notes: pc indicates the address of the first instruction that will be executed after return. re g isters must be saved in word or lon g word size at even addresses. * i g nored at return. bits 23 to 16 of pro g ram counter (pc) bits 15 to 8 of pro g ram counter (pc) bits 7 to 0 of pro g ram counter (pc) condition code re g ister stack pointer figure 4.5 stack after completion of exception handling 4. exception handling rev.4.00 aug. 20, 2007 page 73 of 638 rej09b0395-0400 4.6 notes on stack usage when accessing word data or longword data, the h8/3 008 regards the lowest address bit as 0. the stack should always be accessed by word access or longword access, and the value of the stack pointer (sp:er7) should always be kept even. use the following instructions to save registers: push.w rn (or mov.w rn, @?sp) push.l ern (or mov.l ern, @?sp) use the following instructions to restore registers: pop.w rn (or mov.w @sp+, rn) pop.l ern (or mov.l @sp+, ern) setting sp to an odd value may lead to a malfunction. figure 4.6 shows an example of what happens when the sp value is odd. 4. exception handling rev.4.00 aug. 20, 2007 page 74 of 638 rej09b0395-0400 trapa instruction executed ccr le g end: ccr: pc: r1l: sp: sp pc r1l pc sp sp mov. b r1l, @-er7 sp set to h'fffeff data saved above sp ccr contents lost condition code re g ister pro g ram counter general re g ister r1l stack pointer note: the dia g ram illustrates modes 3 and 4. h'fffefa h'fffefb h'fffefc h'fffefd h'fffefe h'fffeff figure 4.6 operation when sp value is odd 5. interrupt controller rev.4.00 aug. 20, 2007 page 75 of 638 rej09b0395-0400 section 5 interrupt controller 5.1 overview 5.1.1 features the interrupt controller has the following features: ? interrupt priority registers (iprs) for setting interrupt priorities interrupts other than nmi can be assigned to two priority levels on a module-by-module basis in interrupt priority registers a and b (ipra and iprb). ? three-level enabling/disabling by the i and ui bits in the cpu's condition code register (ccr) and the ue bit in the system control register (syscr) ? seven external interrupt pins nmi has the highest priority and is always accepted; either the rising or falling edge can be selected. for each of irq 5 to irq 0 , sensing of the falling edge or level sensing can be selected independently. 5. interrupt controller rev.4.00 aug. 20, 2007 page 76 of 638 rej09b0395-0400 5.1.2 block diagram figure 5.1 shows a block diagram of the interrupt controller. iscr ier ipra, iprb . . . ovf tme tei teie . . . . . . . cpu ccr i ui ue syscr nmi input irq input irq input section isr interrupt controller priority decision lo g ic interrupt request vector number irq sense control re g ister irq enable re g ister irq status re g ister interrupt priority re g ister a interrupt priority re g ister b system control re g ister le g end: iscr: ier: isr: ipra: iprb: syscr: figure 5.1 interrupt controller block diagram 5. interrupt controller rev.4.00 aug. 20, 2007 page 77 of 638 rej09b0395-0400 5.1.3 pin configuration table 5.1 lists the interrupt pins. table 5.1 interrupt pins name abbreviation i/o function nonmaskable interrupt nmi input nonmaskable interrupt, rising edge or falling edge selectable external interrupt request 5 to 0 irq 5 to irq 0 input maskable interrupts, falling edge or level sensing selectable 5.1.4 register configuration table 5.2 lists the registers of the interrupt controller. table 5.2 interrupt controller registers address * 1 name abbreviation r/w initial value h'ee012 system control register syscr r/w h'09 h'ee014 irq sense control register iscr r/w h'00 h'ee015 irq enable register ier r/w h'00 h'ee016 irq status register isr r/(w) * 2 h'00 h'ee018 interrupt priority register a ipra r/w h'00 h'ee019 interrupt priority register b iprb r/w h'00 notes: 1. lower 20 bits of the address in advanced mode. 2. only 0 can be written, to clear flags. 5. interrupt controller rev.4.00 aug. 20, 2007 page 78 of 638 rej09b0395-0400 5.2 register descriptions 5.2.1 system control register (syscr) syscr is an 8-bit readable/writable register that controls software standby mode, selects the action of the ui bit in ccr, selects the nmi edge, and enables or disables the on-chip ram. only bits 3 and 2 are described here. for the other bits, see section 3.3, system control register (syscr). syscr is initialized to h'09 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ue 1 r/w 0 rame 1 r/w 2 nmieg 0 r/w 1 ssoe 0 r/w software standby standby timer sele c t 2 to 0 user bit enable selects whether to use the ui bit in ccr as a user bit or interrupt mask bit nmi edge sele c t selects the nmi input ed g e software standby output port enable ram enable 5. interrupt controller rev.4.00 aug. 20, 2007 page 79 of 638 rej09b0395-0400 bit 3?user bit enable (ue): selects whether to use the ui b it in ccr as a user bit or an interrupt mask bit. bit 3 ue description 0 ui bit in ccr is used as interrupt mask bit 1 ui bit in ccr is used as user bit (initial value) bit 2?nmi edge select (nmieg): selects the nmi input edge. bit 2 nmieg description 0 interrupt is requested at falling edge of nmi input (initial value) 1 interrupt is requested at rising edge of nmi input 5.2.2 interrupt priority registers a and b (ipra, iprb) ipra and iprb are 8-bit readable/writable registers that control interrupt priority. 5. interrupt controller rev.4.00 aug. 20, 2007 page 80 of 638 rej09b0395-0400 interrupt priority register a (ipra): ipra is an 8-bit readable/writable register in which interrupt priority levels can be set. bit initial value read/write 7 ipra7 0 r/w 6 ipra6 0 r/w 5 ipra5 0 r/w 4 ipra4 0 r/w 3 ipra3 0 r/w 0 ipra0 0 r/w 2 ipra2 0 r/w 1 ipra1 0 r/w priority level a7 selects the priority level of irq interrupt requests priority level a3 selects the priority level of wdt, and a/d converter interrupt requests priority level a2 selects the priority level of 16-bit timer channel 0 interrupt requests priority level a1 selects the priority level of 16-bit timer channel 1 interrupt requests priority level a0 selects the priority level of 16-bit timer channel 2 interrupt requests selects the priority level of irq interrupt requests priority level a6 selects the priority level of irq and irq interrupt requests priority level a5 selects the priority level of irq and irq interrupt requests priority level a4 0 1 23 45 ipra is initialized to h'00 by a reset and in hardware standby mode. 5. interrupt controller rev.4.00 aug. 20, 2007 page 81 of 638 rej09b0395-0400 bit 7?priority level a7 (ipra7): selects the priority level of irq 0 interrupt requests. bit 7 ipra7 description 0 irq 0 interrupt requests have priority level 0 (low priority) (initial value) 1 irq 0 interrupt requests have priority level 1 (high priority) bit 6?priority level a6 (ipra6): selects the priority level of irq 1 interrupt requests. bit 6 ipra6 description 0 irq 1 interrupt requests have priority level 0 (low priority) (initial value) 1 irq 1 interrupt requests have priority level 1 (high priority) bit 5?priority level a5 (ipra5): selects the priority level of irq 2 and irq 3 interrupt requests. bit 5 ipra5 description 0 irq 2 and irq 3 interrupt requests have priority level 0 (low priority) (initial value) 1 irq 2 and irq 3 interrupt requests have priority level 1 (high priority) bit 4?priority level a4 (ipra4): selects the priority level of irq 4 and irq 5 interrupt requests. bit 4 ipra4 description 0 irq 4 and irq 5 interrupt requests have priority level 0 (low priority) (initial value) 1 irq 4 and irq 5 interrupt requests have priority level 1 (high priority) bit 3?priority level a3 (ipra3): selects the priority level of wdt, and a/d converter interrupt requests. bit 3 ipra3 description 0 wdt, and a/d converter interrupt requests have priority level 0 (low priority) (initial value) 1 wdt, and a/d converter interrupt requests have priority level 1 (high priority) 5. interrupt controller rev.4.00 aug. 20, 2007 page 82 of 638 rej09b0395-0400 bit 2?priority level a2 (ipra2): selects the priority level of 16-bit timer channel 0 interrupt requests. bit 2 ipra2 description 0 16-bit timer channel 0 interrupt requests have priority level 0 (low priority) (initial value) 1 16-bit timer channel 0 interrupt requests have priority level 1 (high priority) bit 1?priority level a1 (ipra1): selects the priority level of 16-bit timer channel 1 interrupt requests. bit 1 ipra1 description 0 16-bit timer channel 1 interrupt requests have priority level 0 (low priority) (initial value) 1 16-bit timer channel 1 interrupt requests have priority level 1 (high priority) bit 0?priority level a0 (ipra0): selects the priority level of 16-bit timer channel 2 interrupt requests. bit 0 ipra0 description 0 16-bit timer channel 2 interrupt requests have priority level 0 (low priority) (initial value) 1 16-bit timer channel 2 interrupt requests have priority level 1 (high priority) 5. interrupt controller rev.4.00 aug. 20, 2007 page 83 of 638 rej09b0395-0400 interrupt priority register b (iprb): iprb is an 8-bit readable/writable register in which interrupt priority levels can be set. bit initial value read/write 7 iprb7 0 r/w 6 iprb6 0 r/w 5 ? 0 r/w 4 ? 0 r/w 3 iprb3 0 r/w 0 ? 0 r/w 2 iprb2 0 r/w 1 ? 0 r/w priority level b7 selects the priority level of 8-bit timer channel 0, 1 interrupt requests priority level b3 selects the priority level of sci channel 0 interrupt requests priority level b2 selects the priority level of sci channel 1 interrupt requests reserved bit reserved bits selects the priority level of 8-bit timer channel 2, 3 interrupt requests priority level b6 iprb is initialized to h'00 by a reset and in hardware standby mode. bit 7?priority level b7 (iprb7): selects the priority level of 8-bit timer channel 0, 1 interrupt requests. bit 7 iprb7 description 0 8-bit timer channel 0 and 1 interrupt requests have priority level 0 (low priority) (initial value) 1 8-bit timer channel 0 and 1 interrupt requests have priority level 1 (high priority) 5. interrupt controller rev.4.00 aug. 20, 2007 page 84 of 638 rej09b0395-0400 bit 6?priority level b6 (iprb6): selects the priority level of 8-bit timer channel 2, 3 interrupt requests. bit 6 iprb6 description 0 8-bit timer channel 2 and 3 interrupt requests have priority level 0 (low priority) (initial value) 1 8-bit timer channel 2 and 3 interrupt requests have priority level 1 (high priority) bits 5 and 4?reserved: these bits can be written and read, but they do not affect interrupt priority. bit 3?priority level b3 (iprb3): selects the priority level of sci channel 0 interrupt requests. bit 3 iprb3 description 0 sci channel 0 interrupt requests have priority level 0 (low priority) (initial value) 1 sci channel 0 interrupt requests have priority level 1 (high priority) bit 2?priority level b2 (iprb2): selects the priority level of sci channel 1 interrupt requests. bit 2 iprb2 description 0 sci channel 1 interrupt requests have priority level 0 (low priority) (initial value) 1 sci channel 1 interrupt requests have priority level 1 (high priority) bits 1 and 0?reserved: these bits can be written and read, but they do not affect interrupt priority. 5.2.3 irq status register (isr) isr is an 8-bit readable/writable regist er that indicates the status of irq 5 to irq 0 interrupt requests. 5. interrupt controller rev.4.00 aug. 20, 2007 page 85 of 638 rej09b0395-0400 bit initial value read/write 7 ? 0 ? these bits indicate irq to irq fla g interrupt request status note: only 0 can be written, to clear fla g s. * 6 ? 0 ? 5 irq5f 0 r/(w) * 4 irq4f 0 r/(w) * 3 irq3f 0 r/(w) * 2 irq2f 0 r/(w) * 1 irq1f 0 r/(w) * 0 irq0f 0 r/(w) * 50 irq to irq flags 50 reserved bits isr is initialized to h'00 by a reset and in hardware standby mode. bits 7 and 6?reserved: these bits can not be modified and are always read as 0. bits 5 to 0?irq 5 to irq 0 flags (irq5f to irq0f): these bits indicate the status of irq 5 to irq 0 interrupt requests. bits 5 to 0 irq5f to irq0f description 0 [clearing conditions] (initial value) 0 is written in irqnf after reading the irqnf flag when irqnf = 1. irqnsc = 0, irqn input is high, and interrupt exception handling is carried out. irqnsc = 1 and irqn interrupt exception handling is carried out. 1 [setting conditions] irqnsc = 0 and irqn input is low. irqnsc = 1 and irqn input changes from high to low. note: n = 5 to 0 5.2.4 irq enable register (ier) ier is an 8-bit readable/writable regi ster that enables or disables irq 5 to irq 0 interrupt requests. bit initial value read/write 7 ? 0 r/w these bits enable or disable irq to irq interrupts 6 ? 0 r/w 5 irq5e 0 r/w 4 irq4e 0 r/w 3 irq3e 0 r/w 2 irq2e 0 r/w 1 irq1e 0 r/w 0 irq0e 0 r/w 50 irq to irq enable 50 reserved bits ier is initialized to h'00 by a reset and in hardware standby mode. 5. interrupt controller rev.4.00 aug. 20, 2007 page 86 of 638 rej09b0395-0400 bits 7 and 6?reserved: these bits can be written and read, but they do not enable or disable interrupts. bits 5 to 0?irq 5 to irq 0 enable (irq5e to irq0e): these bits enable or disable irq 5 to irq 0 interrupts. bits 5 to 0 irq5e to irq0e description 0 irq 5 to irq 0 interrupts are disabled (initial value) 1 irq 5 to irq 0 interrupts are enabled 5.2.5 irq sense control register (iscr) iscr is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the inputs at pins irq 5 to irq 0 . bit initial value read/write 7 ? 0 r/w these bits select level sensin g or fallin g -ed g e sensin g for irq to irq interrupts 6 ? 0 r/w 5 irq5sc 0 r/w 4 irq4sc 0 r/w 3 irq3sc 0 r/w 2 irq2sc 0 r/w 1 irq1sc 0 r/w 0 irq0sc 0 r/w 50 irq to irq sense c ontrol 50 reserved bits iscr is initialized to h'00 by a reset and in hardware standby mode. bits 7 and 6?reserved: these bits can be written and read, but they do not select level or falling-edge sensing. bits 5 to 0?irq 5 to irq 0 sense control (irq5sc to irq0sc): these bits select whether interrupts irq 5 to irq 0 are requested by level sensing of pins irq 5 to irq 0 , or by falling-edge sensing. bits 5 to 0 irq5sc to irq0sc description 0 interrupts are requested when irq 5 to irq 0 inputs are low (initial value) 1 interrupts are requested by falling-edge input at irq 5 to irq 0 5. interrupt controller rev.4.00 aug. 20, 2007 page 87 of 638 rej09b0395-0400 5.3 interrupt sources the interrupt sources include external interrupts (nmi, irq 5 to irq 0 ) and 27 internal interrupts. 5.3.1 external interrupts there are seven external interrupts: nmi, and irq 5 to irq 0 . of these, nmi, irq 2 , irq 1 , and irq 0 can be used to exit software standby mode. nmi: nmi is the highest-priority interrupt and is always accepted, regardless of the states of the i and ui bits in ccr. the nmieg bit in syscr selects whether an interrupt is requested by the rising or falling edge of the input at the nmi pin. nmi interrupt exception handling has vector number 7. irq 5 to irq 0 interrupts: these interrupts are requested by input signals at pins irq 5 to irq 0 . the irq 5 to irq 0 interrupts have the following features. ? iscr settings can select whether an interrupt is requested by the low level of the input at pins irq 5 to irq 0 , or by the falling edge. ? ier settings can enable or disable the irq 5 to irq 0 interrupts. interrupt priority levels can be assigned by four bits in ipra (ipra7 to ipra4). ? the status of irq 5 to irq 0 interrupt requests is indicated in isr. the isr flags can be cleared to 0 by software. figure 5.2 shows a block diagram of interrupts irq 5 to irq 0 . input ed g e/level sense circuit irqnsc irqnf s r q irqne irqn interrupt request clear si g nal irqn note: n = 5 to 0 figure 5.2 block diagram of interrupts irq 5 to irq 0 5. interrupt controller rev.4.00 aug. 20, 2007 page 88 of 638 rej09b0395-0400 figure 5.3 shows the timing of the setting of the interrupt flags (irqnf). irqn irqnf input pin note: n = 5 to 0 figure 5.3 timing of setting of irqnf interrupts irq 0 to irq 5 have vector numbers 12 to 17. these interrupts are detected regardless of whether the corresponding pin is set for input or output. when using a pin for external interrupt input, clear its ddr bit to 0 and do not use the pin for chip select output, sci input/output, or a/d external trigger input. 5.3.2 internal interrupts twenty-seven internal interrupts are requested from the on-chip supporting modules. ? each on-chip supporting module has status flags for indicating interrupt status, and enable bits for enabling or disabling interrupts. ? interrupt priority levels can be assigned in ipra and iprb. 5.3.3 interrupt exception handling vector table table 5.3 lists the interrupt exception handling sources, their vector addresses, and their default priority order. in the default priority order, smaller vector numbers have higher priority. the priority of interrupts other than nmi can be changed in ipra and iprb. the priority order after a reset is the default order shown in table 5.3. 5. interrupt controller rev.4.00 aug. 20, 2007 page 89 of 638 rej09b0395-0400 table 5.3 interrupt sources, v ector addresses, and priority vector address * interrupt source origin vector number advanced mode normal mode ipr priority nmi 7 h'001c to h'001f h'000e to h'000f ? high irq 0 external pins 12 h'0030 to h'0033 h'0018 to h'0019 ipra7 irq 1 13 h'0034 to h0037 h'001a to h'001b ipra6 irq 2 irq 3 14 15 h'0038 to h'003b h'003c to h'003f h'001c to h'001d h'001e to h'001f ipra5 irq 4 irq 5 16 17 h'0040 to h'0043 h'0044 to h'0047 h'0020 to h'0021 h'0022 to h'0023 ipra4 reserved ? 18 19 h'0048 to h'004b h'004c to h'004f h'0024 to h'0025 h'0026 to h'0027 wovi (interval timer) watchdog timer 20 h'0050 to h'0053 h'0028 to h'0029 ipra3 reserved ? 21 22 h'0054 to h'0057 h'0058 to h'005b h'002a to h'002b h'002c to h'002d adi (a/d end) a/d 23 h'005c to h'005f h'002e to h'002f imia0 (compare match/ input capture a0) 16-bit timer channel 0 24 h'0060 to h'0063 h'0030 to h'0031 ipra2 imib0 (compare match/ input capture b0) 25 h'0064 to h'0067 h'0032 to h'0033 ovi0 (overflow 0) 26 h'0068 to h'006b h'0034 to h'0035 reserved ? 27 h'006c to h'006f h'0036 to h'0037 imia1 (compare match/ inputcapture a1) 16-bit timer channel 1 28 h'0070 to h'0073 h'0038 to h'0039 ipra1 imib1 (compare match/ input capture b1) 29 h'0074 to h'0077 h'003a to h'003b ovi1 (overflow 1) 30 h'0078 to h'007b h'003c to h'003d reserved ? 31 h'007c to h'007f h'003e to h'003f low 5. interrupt controller rev.4.00 aug. 20, 2007 page 90 of 638 rej09b0395-0400 vector address * interrupt source origin vector number advanced mode normal mode ipr priority imia2 (compare match/ input capture a2) 16-bit timer channel 2 32 h'0080 to h'0083 h'0040 to h'0041 ipra0 high imib2 (compare match/ input capture b2) 33 h'0084 to h'0087 h'0042 to h'0043 ovi2 (overflow 2) 34 h'0088 to h'008b h'0044 to h'0045 reserved ? 35 h'008c to h'008f h'0046 to h'0047 cmia0 (compare match a0) 36 h'0090 to h'0093 h'0048 to h'0049 iprb7 cmib0 (compare match b0) 37 h'0094 to h'0097 h'004a to h'004b cmia1/cmib1 (compare match a1/b1) 38 h'0098 to h'009b h'004c to h'004d tovi0/tovi1 (overflow 0/1) 8-bit timer channel 0/1 39 h'009c to h'009f h'004e to h'004f cmia2 (compare match a2) 40 h'00a0 to h'00a3 h'0050 to h'0051 iprb6 cmib2 (compare match b2) 41 h'00a4 to h'00a7 h'0052 to h'0053 cmia3/cmib3 (compare match a3/b3) 42 h'00a8 to h'00ab h'0054 to h'0055 tovi2/tovi3 (overflow 2/3) 8-bit timer channel 2/3 43 h'00ac to h'00af h'0056 to h'0057 reserved ? 44 45 46 47 48 49 50 51 h'00b0 to h'00b3 h'00b4 to h'00b7 h'00b8 to h'00bb h'00bc to h'00bf h'00c0 to h'00c3 h'00c4 to h'00c7 h'00c8 to h'00cb h'00cc to h'00cf h'0058 to h'0059 h'005a to h'005b h'005c to h'005d h'005e to h'005f h'0060 to h'0061 h'0062 to h'0063 h'0064 to h'0065 h'0066 to h'0067 ? low 5. interrupt controller rev.4.00 aug. 20, 2007 page 91 of 638 rej09b0395-0400 vector address * interrupt source origin vector number advanced mode normal mode ipr priority eri0 (receive error 0) sci channel 0 52 h'00d0 to h'00d3 h'0068 to h'0069 iprb3 high rxi0 (receive data full 0) 53 h'00d4 to h'00d7 h'006a to h'006b txi0 (transmit data empty 0) 54 h'00d8 to h'00db h'006c to h'006d tei0 (transmit end 0) 55 h'00dc to h'00df h'006e to h'006f eri1 (receive error 1) sci channel 1 56 h'00e0 to h'00e3 h'0070 to h'0071 iprb2 rxi1 (receive data full 1) 57 h'00e4 to h'00e7 h'0072 to h'0073 txi1 (transmit data empty 1) 58 h'00e8 to h'00eb h'0074 to h'0075 tei1 (transmit end 1) 59 h'00ec to h'00ef h'0076 to h'0077 reserved ? 60 61 62 63 h'00f0 to h'00f3 h'00f4 to h'00f7 h'00f8 to h'00fb h'00fc to h'00ff h'0078 to h'0079 h'007a to h'007b h'007c to h'007d h'007e to h'007f ? low note: * lower 16 bits of the address. 5. interrupt controller rev.4.00 aug. 20, 2007 page 92 of 638 rej09b0395-0400 5.4 interrupt operation 5.4.1 interrupt handling process the h8/3008 handles interrupts differently depending on the setting of the ue bit. when ue = 1, interrupts are controlled by the i bit. when ue = 0, interrupts are controlled by the i and ui bits. table 5.4 indicates how interrupts are handled for all setting combinations of the ue, i, and ui bits. nmi interrupts are always accepted except in the reset and hardware standby states. irq interrupts and interrupts from the on-chip supporting modules have their own enable bits. interrupt requests are ignored when the enable bits are cleared to 0. table 5.4 ue, i, and ui bit settings and interrupt handling syscr ccr ue i ui description 1 0 ? all interrupts are accepted. interrupts with priority level 1 have higher priority. 1 ? no interrupts are accepted except nmi. 0 0 ? all interrupts are accepted. interrupts with priority level 1 have higher priority. 1 0 nmi and interrupts with priority level 1 are accepted. 1 no interrupts are accepted except nmi. ue = 1: interrupts irq 5 to irq 0 and interrupts from the on-chip supporting modules can all be masked by the i bit in the cpu's ccr. interrupts are masked when the i bit is set to 1, and unmasked when the i bit is cleared to 0. interrupts with priority level 1 have higher priority. figure 5.4 is a flowchart showing how interrupts are accepted when ue = 1. 5. interrupt controller rev.4.00 aug. 20, 2007 page 93 of 638 rej09b0395-0400 pro g ram execution state interrupt requested? nmi no ye s no ye s no priority level 1? no irq 0 ye s no irq 1 ye s tei1 ye s no irq 0 ye s no irq 1 ye s tei1 ye s no i = 0 ye s save pc and ccr i 1 branch to interrupt service routine pendin g ye s read vector address figure 5.4 process up to in terrupt acceptance when ue = 1 5. interrupt controller rev.4.00 aug. 20, 2007 page 94 of 638 rej09b0395-0400 ? if an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. ? when the interrupt controller receives one or mo re interrupt requests, it selects the highest- priority request, following the ipr interrupt priority settings, and holds other requests pending. if two or more interrupts with the same ipr setting are requested simultaneously, the interrupt controller follows the priority order shown in table 5.3. ? the interrupt controller checks the i bit. if the i b it is cleared to 0, the selected interrupt request is accepted. if the i bit is set to 1, only nmi is accepted; other interrupt requests are held pending. ? when an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. ? in interrupt exception handling, pc and ccr are saved to the stack area. the pc value that is saved indicates the address of the first instruction that will be executed after the return from the interrupt service routine. ? next the i bit is set to 1 in ccr, masking all interrupts except nmi. ? the vector address of the accepted interrupt is generated, and the interrupt service routine starts executing from the address indicated by the contents of the vector address. ue = 0: the i and ui bits in the cpu's ccr and the ipr bits enable three-level masking of irq 0 to irq 5 interrupts and interrupts from the on-chip supporting modules. ? interrupt requests with priority level 0 are masked when the i bit is set to 1, and are unmasked when the i bit is cleared to 0. ? interrupt requests with priority level 1 are masked when the i and ui bits are both set to 1, and are unmasked when either the i bit or the ui bit is cleared to 0. for example, if the interrupt enable bits of all interrupt requests are set to 1, ipra is set to h'20, and iprb is set to h'00 (giving irq 2 and irq 3 interrupt requests priority over other interrupts), interrupts are masked as follows: a. if i = 0, all interrupts are unmasked (priority order: nmi > irq 2 > irq 3 >irq 0 ?). b. if i = 1 and ui = 0, only nmi, irq 2 , and irq 3 are unmasked. c. if i = 1 and ui = 1, all interrupts are masked except nmi. figure 5.5 shows the transitions among the above states. 5. interrupt controller rev.4.00 aug. 20, 2007 page 95 of 638 rej09b0395-0400 all interrupts are unmasked only nmi, irq , and irq are unmasked exception handlin g , or i 1, ui 1 a. b. 2 3 all interrupts are masked except nmi c. ui 0 i 0 exception handlin g , or ui 1 i 0 i 1, ui 0 figure 5.5 interrupt masking state transitions (example) figure 5.6 is a flowchart showing how interrupts are accepted when ue = 0. ? if an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. ? when the interrupt controller receives one or mo re interrupt requests, it selects the highest- priority request, following the ipr interrupt priority settings, and holds other requests pending. if two or more interrupts with the same ipr setting are requested simultaneously, the interrupt controller follows the priority order shown in table 5.3. ? the interrupt controller checks the i bit. if the i bit is cleared to 0, the selected interrupt request is accepted regardless of its ipr setting, and regardless of the ui bit. if the i bit is set to 1 and the ui bit is cleared to 0, only interrupts with priority level 1 are accepted; interrupt requests with priority level 0 are held pending. if the i bit and ui bit are both set to 1, all other interrupt requests are held pending. ? when an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. ? in interrupt exception handling, pc and ccr are saved to the stack area. the pc value that is saved indicates the address of the first instruction that will be executed after the return from the interrupt service routine. ? the i and ui bits are set to 1 in ccr, masking all interrupts except nmi. ? the vector address of the accepted interrupt is generated, and the interrupt service routine starts executing from the address indicated by the contents of the vector address. 5. interrupt controller rev.4.00 aug. 20, 2007 page 96 of 638 rej09b0395-0400 pro g ram execution state interrupt requested? nmi no ye s no ye s no priority level 1? no irq 0 ye s no irq 1 ye s tei1 ye s no irq 0 ye s no irq 1 ye s tei1 ye s no i = 0 ye s no i = 0 ye s ui = 0 ye s no save pc and ccr i 1, ui 1 pendin g branch to interrupt service routine ye s read vector address figure 5.6 process up to in terrupt acceptance when ue = 0 5. interrupt controller rev.4.00 aug. 20, 2007 page 97 of 638 rej09b0395-0400 5.4.2 interrupt exception handling sequence figure 5.7 shows the interrupt exception handling sequence in mode 2 when the program code and stack are in an external memory area accessed in two states via a 16-bit bus. address bus interrupt request si g nal rd hwr d to d 15 8 (1) (2), (4) (3) (5) (7) note: mode 2, with pro g ram code and stack in external memory area accessed in two states via 16-bit bus. lwr , interrupt level decision and wait for end of instruction interrupt accepted instruction prefetch internal processin g stack vector fetch internal processin g prefetch of interrupt service routine instruction hi g h instruction prefetch address (not executed; return address, same as pc contents) instruction code (not executed) instruction prefetch address (not executed) sp ? 2 sp ? 4 (6), (8) (9), (11) (10), (12) (13) (14) pc and ccr saved to stack vector address startin g address of interrupt service routine (contents of vector address) startin g address of interrupt service routine; (13) = (10), (12) first instruction of interrupt service routine (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) figure 5.7 interrupt ex ception handling sequence 5. interrupt controller rev.4.00 aug. 20, 2007 page 98 of 638 rej09b0395-0400 5.4.3 interrupt response time table 5.5 indicates the interrupt response time from the occurrence of an in terrupt request until the first instruction of the interrupt service routine is executed. table 5.5 interrupt response time external memory 8-bit bus 16-bit bus no. item on-chip memory 2 states 3 states 2 states 3 states 1 interrupt priority decision 2 * 1 2 * 1 2 * 1 2 * 1 2 * 1 2 maximum number of states until end of current instruction 1 to 23 1 to 27 1 to 31 * 4 1 to 23 1 to 25 * 4 3 saving pc and ccr to stack 4 8 12 * 4 4 6 * 4 4 vector fetch 4 8 12 * 4 4 6 * 4 5 instruction fetch * 2 4 8 12 * 4 4 6 * 4 6 internal processing * 3 4 4 4 4 4 total 19 to 41 31 to 57 43 to 73 19 to 41 25 to 49 notes: 1. 1 state for internal interrupts. 2. prefetch after the interrupt is accepted and prefetch of the first instruction in the interrupt service routine. 3. internal processing after the interrupt is accepted and internal processing after vector fetch. 4. the number of states increases if wait states are inserted in external memory access. 5. interrupt controller rev.4.00 aug. 20, 2007 page 99 of 638 rej09b0395-0400 5.5 usage notes 5.5.1 contention between interrupt and interrupt-disabling instruction when an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not disabled until after execution of the instruction is completed. if an interrupt occurs while a bclr, mov, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant when execution of the instruction ends the interrupt is still enabled, so its interrupt exception handling is carried out. if a higher-priority interrupt is also requested, however, interrupt exception handling for the higher-priority interrupt is carried out, and the lower-priority interrupt is ignored. this also applies to the clearing of an interrupt flag to 0. figure 5.8 shows an example in which an imiea b it is cleared to 0 in the 16-bit timer's tisra register. imia exception handlin g tisra write cycle by cpu tisra address internal address bus internal write si g nal imiea imia imfa interrupt si g nal figure 5.8 contention between interrupt and int errupt-disabling instruction this type of contention will not occur if the interrupt is masked when the interrupt enable bit or flag is cleared to 0. 5. interrupt controller rev.4.00 aug. 20, 2007 page 100 of 638 rej09b0395-0400 5.5.2 instructions that inhibit interrupts the ldc, andc, orc, and xorc instructions inhibit interrupts. when an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a cpu interrupt. if the cpu is currently executing one of these interrupt-inhibiting instructions, however, when the instruction is completed the cpu always continues by executing the next instruction. 5.5.3 interrupts during eepmov instruction execution the eepmov.b and eepmov.w instructions differ in their reaction to interrupt requests. when the eepmov.b instruction is executing a transfer, no interrupts are accepted until the transfer is completed, not even nmi. when the eepmov.w instruction is executing a transfer, interrupt requests other than nmi are not accepted until the transfer is completed. if nmi is requested, nmi exception handling starts at a transfer cycle boundary. the pc value saved on the stack is the address of the next instruction. programs should be coded as follows to allow for nmi interrupts during eepmov.w execution: l1: eepmov.w mov.w r4,r4 bne l1 6. bus controller rev.4.00 aug. 20, 2007 page 101 of 638 rej09b0395-0400 section 6 bus controller 6.1 overview the h8/3008 has an on-chip bus controller (bsc) that manages the extern al address space divided into eight areas. the bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multip le memories to be connected easily. the bus controller also has a bus arbitration function that controls the operation of the internal bus masters ? the cpu can release the bus to an external device. 6.1.1 features the features of the bus controller are listed below. ? manages external address space in area units ? manages the external space as eight areas (0 to 7) of 128 kbytes in 1m-byte modes, or 2 mbytes in 16-mbyte modes ? bus specifications can be set independently for each area ? basic bus interface ? chip select ( cs 0 to cs 7 ) can be output for areas 0 to 7 ? 8-bit access or 16-bit access can be selected for each area ? two-state access or three-state access can be selected for each area ? program wait states can be inserted for each area ? pin wait insertion capability is provided ? idle cycle insertion ? an idle cycle can be inserted in case of an external read cycle between different areas ? an idle cycle can be inserted when an external read cycle is immediately followed by an external write cycle ? bus arbitration function ? a built-in bus arbiter grants the bus right to the cpu, or an external bus master ? other features ? choice of two address update modes 6. bus controller rev.4.00 aug. 20, 2007 page 102 of 638 rej09b0395-0400 6.1.2 block diagram figure 6.1 shows a block diagram of the bus controller. internal address bus abwcr astcr bcr cscr adrcr area decoder chip select control si g nals cs 0 to cs 7 bus control circuit wcrh wcrl brcr le g end: wait state controller wait back breq internal data bus cpu bus request si g nal cpu bus acknowled g e si g nal bus arbiter bus mode control si g nal internal si g nals internal si g nals bus size control si g nal access state control si g nal wait request si g nal bus width control re g ister access state control re g ister wait control re g ister h wait control re g ister l bus release control re g ister chip select control re g ister astcr: wcrh: wcrl: brcr: cscr: address control re g ister adrcr: abwcr: bcr: bus control re g ister figure 6.1 block diagram of bus controller 6. bus controller rev.4.00 aug. 20, 2007 page 103 of 638 rej09b0395-0400 6.1.3 pin configuration table 6.1 summarizes the input/output pins of the bus controller. table 6.1 bus controller pins name abbreviation i/o function chip select 0 to 7 cs 0 to cs 7 output strobe signals selecting areas 0 to 7 address strobe as output strobe signal indicating valid address output on the address bus read rd output strobe signal indicating reading from the external address space high write hwr output strobe signal indicating writing to the external address space, with valid data on the upper data bus (d 15 to d 8 ) low write lwr output strobe signal indicating writing to the external address space, with valid data on the lower data bus (d 7 to d 0 ) wait wait input wait request signal for access to external three-state access areas bus request breq input request signal for releasing the bus to an external device bus acknowledge back output acknowledge signal indicating release of the bus to an external device 6. bus controller rev.4.00 aug. 20, 2007 page 104 of 638 rej09b0395-0400 6.1.4 register configuration table 6.2 summarizes the bus controller's registers. table 6.2 bus controller registers address * 1 name abbreviation r/w initial value h'ee020 bus width control register abwcr r/w h'ff * 2 h'ee021 access state control register astcr r/w h'ff h'ee022 wait control register h wcrh r/w h'ff h'ee023 wait control register l wcrl r/w h'ff h'ee013 bus release control register brcr r/w h'fe * 3 h'ee01f chip select control register cscr r/w h'0f h'ee01e address control register adrcr r/w h'ff h'ee024 bus control register bcr r/w h'c6 notes: 1. lower 20 bits of the address in advanced mode. 2. in modes 2 and 4, the initial value is h'00. 3. in modes 3 and 4, the initial value is h'ee. 6.2 register descriptions 6.2.1 bus width control register (abwcr) abwcr is an 8-bit readable/wr itable register that selects 8- bit or 16-bit access for each area. 7 abw7 1 r/w 0 r/w 6 abw6 1 r/w 0 r/w 5 abw5 1 r/w 0 r/w 4 abw4 1 r/w 0 r/w 3 abw3 1 r/w 0 r/w 2 abw2 1 r/w 0 r/w 1 abw1 1 r/w 0 r/w 0 abw0 1 r/w 0 r/w bit modes 1 and 3 initial value read/write initial value read/write modes 2 and 4 when abwcr contains h'ff (selecting 8-bit access fo r all areas), the chip operates in 8-bit bus mode: the upper data bus (d 15 to d 8 ) is valid, and port 4 is an input/output port. when at least one bit is cleared to 0 in abwcr, the chip operates in 16-bit bus mode with a 16-bit data bus (d 15 to d 0 ). in modes 1 and 3, abwcr is initialized to h'ff by a reset and in hardware standby mode. in modes 2 and 4, abwcr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. 6. bus controller rev.4.00 aug. 20, 2007 page 105 of 638 rej09b0395-0400 bits 7 to 0?area 7 to 0 bus width control (abw7 to abw0): these bits select 8-bit access or 16-bit access for the corresponding areas. bits 7 to 0 abw7 to abw0 description 0 areas 7 to 0 are 16-bit access areas 1 areas 7 to 0 are 8-bit access areas abwcr specifies the data bus width of external memory areas. the data bus width of on-chip memory and registers is fixed, and does not depend on abwcr settings. 6.2.2 access state control register (astcr) astcr is an 8-bit readable/wr itable register that selects wh ether each area is accessed in two states or three states. ast3 ast2 ast1 ast0 1 initial value 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w 76543210 bits selectin g number of states for access to each area ast7 ast6 ast5 ast4 bit astcr is initialized to h'ff by a reset and in ha rdware standby mode. it is not initialized in software standby mode. bits 7 to 0?area 7 to 0 access state control (ast7 to ast0): these bits select whether the corresponding area is accessed in two or three states. bits 7 to 0 ast7 to ast0 description 0 areas 7 to 0 are accessed in two states 1 areas 7 to 0 are accessed in three states (initial value) astcr specifies the number of states in which external areas are accessed. on-chip memory and registers are accessed in a fixed number of stat es that does not depend on astcr settings. 6. bus controller rev.4.00 aug. 20, 2007 page 106 of 638 rej09b0395-0400 6.2.3 wait control registers h and l (wcrh, wcrl) wcrh and wcrl are 8-bit readable/writable regi sters that select the number of program wait states for each area. on-chip memory and registers are accessed in a fi xed number of states th at does not depend on wcrh/wcrl settings. wcrh and wcrl are initialized to h'ff by a reset and in hardware standby mode. they are not initialized in software standby mode. wcrh w51 w50 w41 w40 1 initial value 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w 76543210 w71 w70 w61 w60 bit bits 7 and 6?area 7 wait control 1 and 0 (w71, w70): these bits select the number of program wait states when area 7 in external space is accessed while the ast7 bit in astcr is set to 1. bit 7 w71 bit 6 w70 description 0 0 program wait not inserted when external space area 7 is accessed 1 1 program wait state inserted when external space area 7 is accessed 1 0 2 program wait states inserted when external space area 7 is accessed 1 3 program wait states inserted when external space area 7 is accessed (initial value) 6. bus controller rev.4.00 aug. 20, 2007 page 107 of 638 rej09b0395-0400 bits 5 and 4?area 6 wait control 1 and 0 (w61, w60): these bits select the number of program wait states when area 6 in external space is accessed while the ast6 bit in astcr is set to 1. bit 5 w61 bit 4 w60 description 0 0 program wait not inserted when external space area 6 is accessed 1 1 program wait state inserted when external space area 6 is accessed 1 0 2 program wait states inserted when external space area 6 is accessed 1 3 program wait states inserted when external space area 6 is accessed (initial value) bits 3 and 2?area 5 wait control 1 and 0 (w51, w50): these bits select the number of program wait states when area 5 in external space is accessed while the ast5 bit in astcr is set to 1. bit 3 w51 bit 2 w50 description 0 0 program wait not inserted when external space area 5 is accessed 1 1 program wait state inserted when external space area 5 is accessed 1 0 2 program wait states inserted when external space area 5 is accessed 1 3 program wait states inserted when external space area 5 is accessed (initial value) bits 1 and 0?area 4 wait control 1 and 0 (w41, w40): these bits select the number of program wait states when area 4 in external space is accessed while the ast4 bit in astcr is set to 1. bit 1 w41 bit 0 w40 description 0 0 program wait not inserted when external space area 4 is accessed 1 1 program wait state inserted when external space area 4 is accessed 1 0 2 program wait states inserted when external space area 4 is accessed 1 3 program wait states inserted when external space area 4 is accessed (initial value) 6. bus controller rev.4.00 aug. 20, 2007 page 108 of 638 rej09b0395-0400 wcrl w11 w10 w01 w00 1 initial value 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w 76543210 w31 w30 w21 w20 bit bits 7 and 6?area 3 wait control 1 and 0 (w31, w30): these bits select the number of program wait states when area 3 in external space is accessed while the ast3 bit in astcr is set to 1. bit 7 w31 bit 6 w30 description 0 0 program wait not inserted when external space area 3 is accessed 1 1 program wait state inserted when external space area 3 is accessed 1 0 2 program wait states inserted when external space area 3 is accessed 1 3 program wait states inserted when external space area 3 is accessed (initial value) bits 5 and 4?area 2 wait control 1 and 0 (w21, w20): these bits select the number of program wait states when area 2 in external space is accessed while the ast2 bit in astcr is set to 1. bit 5 w21 bit 4 w20 description 0 0 program wait not inserted when external space area 2 is accessed 1 1 program wait state inserted when external space area 2 is accessed 1 0 2 program wait states inserted when external space area 2 is accessed 1 3 program wait states inserted when external space area 2 is accessed (initial value) 6. bus controller rev.4.00 aug. 20, 2007 page 109 of 638 rej09b0395-0400 bits 3 and 2?area 1 wait control 1 and 0 (w11, w10): these bits select the number of program wait states when area 1 in external space is accessed while the ast1 bit in astcr is set to 1. bit 3 w11 bit 2 w10 description 0 0 program wait not inserted when external space area 1 is accessed 1 1 program wait state inserted when external space area 1 is accessed 1 0 2 program wait states inserted when external space area 1 is accessed 1 3 program wait states inserted when external space area 1 is accessed (initial value) bits 1 and 0?area 0 wait control 1 and 0 (w01, w00): these bits select the number of program wait states when area 0 in external space is accessed while the ast0 bit in astcr is set to 1. bit 1 w01 bit 0 w00 description 0 0 program wait not inserted when external space area 0 is accessed 1 1 program wait state inserted when external space area 0 is accessed 1 0 2 program wait states inserted when external space area 0 is accessed 1 3 program wait states inserted when external space area 0 is accessed (initial value) 6. bus controller rev.4.00 aug. 20, 2007 page 110 of 638 rej09b0395-0400 6.2.4 bus release control register (brcr) brcr is an 8-bit readable/writable register that enables address output on bus lines a 23 to a 20 and enables or disables release of the bus to an external device. 7 a23e 1 ? 1 r/w address 23 to 20 enable these bits enable pa 7 to pa 4 to be used for a 23 to a 20 address output 6 a22e 1 ? 1 r/w 5 a21e 1 ? 1 r/w 4 a20e 1 ? 0 ? 3 ? 1 ? 1 ? 2 ? 1 ? 1 ? 1 ? 1 ? 1 ? 0 brle 0 r/w 0 r/w bit modes 1 and 2 initial value read/write initial value read/write modes 3 and 4 reserved bits bus release enable enables or disables release of the bus to an external device brcr is initialized to h'fe in modes 1 and 2, and to h'ee in modes 3 and 4, by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7?address 23 enable (a23e): enables pa 4 to be used as the a 23 address output pin. writing 0 in this bit enables a 23 output from pa 4 . in modes other than 3 and 4, this bit cannot be modified and pa 4 has its ordinary port functions. bit 7 a23e description 0 pa 4 is the a 23 address output pin 1 pa 4 is an input/output pin (initial value) bit 6?address 22 enable (a22e): enables pa 5 to be used as the a 22 address output pin. writing 0 in this bit enables a 22 output from pa 5 . in modes other than 3 and 4, this bit cannot be modified and pa 5 has its ordinary port functions. bit 6 a22e description 0 pa 5 is the a 22 address output pin 1 pa 5 is an input/output pin (initial value) 6. bus controller rev.4.00 aug. 20, 2007 page 111 of 638 rej09b0395-0400 bit 5?address 21 enable (a21e): enables pa 6 to be used as the a 21 address output pin. writing 0 in this bit enables a 21 output from pa 6 . in modes other than 3 and 4, this bit cannot be modified and pa 6 has its ordinary port functions. bit 5 a21e description 0 pa 6 is the a 21 address output pin 1 pa 6 is an input/output pin (initial value) bit 4?address 20 enable (a20e): enables pa 7 to be used as an address output pin. when 0 is written to this bit, pa 7 functions as address output a 20 . in modes 3 and 4, pa 7 functions as an address output pin, and in modes 1 and 2, as a normal port pin. bit 4 a20e description 0 pa 7 is the a 20 address output pin (in mode 3 or 4) 1 pa 7 is an input/output pin (in mode 1 or 2) bits 3 to 1?reserved: these bits cannot be modified and are always read as 1. bit 0?bus release enable (brle): enables or disables release of the bus to an external device. bit 0 brle description 0 the bus cannot be released to an external device breq and back can be used as input/output pins (initial value) 1 the bus can be released to an external device 6.2.5 bus control register (bcr) ? ? rdea waite 1 initial value 1 0 * 1 0 * 1 0 * 1 1 * 2 10 read/write ?? r/w r/w r/w r/w ? ? 76543210 icis1 icis0 ?? bit notes: 1. 1 must not be written in bits 5 to 3. 2. 0 must not be written in bit 2. 6. bus controller rev.4.00 aug. 20, 2007 page 112 of 638 rej09b0395-0400 bcr is an 8-bit readable/writable re gister that enables or disables idle cycle insertion, selects the area division unit, selects the extended memory map, and enables or disables wait pin input. bcr is initialized to h'c6 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7?idle cycle insertion 1 (icis1): selects whether one idle cycl e state is to be inserted between bus cycles in case of consecutive ex ternal read cycles for different areas. bit 7 icis1 description 0 no idle cycle inserted in case of consecutive external read cycles for different areas 1 idle cycle inserted in case of consecutive external read cycles for different areas (initial value) bit 6?idle cycle insertion 0 (icis0): selects whether one idle cycl e state is to be inserted between bus cycles in case of consecu tive external read and write cycles. bit 6 icis0 description 0 no idle cycle inserted in case of consecutive external read and write cycles 1 idle cycle inserted in case of consecutive external read and write cycles (initial value) bits 5 to 3?reserved (must not be set to 1): these bits can be read and written, but must not be set to 1. normal operation cannot be guaranteed if 1 is written in these bits. bit 2? reserved (must not be set to 0): this bit can be read and written, but must not be set to 0. normal operation cannot be guaranteed if 0 is written in this bit. 6. bus controller rev.4.00 aug. 20, 2007 page 113 of 638 rej09b0395-0400 bit 1?area division unit select (rdea): selects the memory map area division units. this bit is valid in modes 3 and 4, and is invalid in modes 1 and 2. bit 1 rdea description 0 area divisions are as follows: area 0: 2 mbytes area 4: 1.93 mbytes area 1: 2 mbytes area 5: 4 kbytes area 2: 8 mbytes area 6: 23.75 kbytes area 3: 2 mbytes area 7: 22 bytes 1 areas 0 to 7 are the same size (2 mbytes) (initial value) bit 0?wait pin enable (waite): enables or disables wait insertion by means of the wait pin. bit 0 waite description 0 wait pin wait input is disabled, and the wait pin can be used as an input/output port (initial value) 1 wait pin wait input is enabled 6. bus controller rev.4.00 aug. 20, 2007 page 114 of 638 rej09b0395-0400 6.2.6 chip select control register (cscr) cscr is an 8-bit readable/writable register that enables or disables output of chip select signals ( cs 7 to cs 4 ). if output of a chip select signal cs 7 to cs 4 is enabled by a setting in this register, the corresponding pin functions a chip select signal ( cs 7 to cs 4 ) output regardless of any other settings. ???? 0 initial value 0 0 0 1 1 1 1 read/write ???? r/w r/w r/w r/w 76543210 reserved bits cs7e cs6e cs5e cs4e chip sele c t 7 to 4 enable these bits enable or disable chip select si g nal output bit cscr is initialized to h'0f by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 4?chip select 7 to 4 enable (cs7e to cs4e): these bits enable or disable output of the corresponding chip select signal. bit n csne description 0 output of chip select signal csn is disabled (initial value) 1 output of chip select signal csn is enabled note: n = 7 to 4 bits 3 to 0?reserved: these bits cannot be modified and are always read as 1. 6. bus controller rev.4.00 aug. 20, 2007 page 115 of 638 rej09b0395-0400 6.2.7 address control register (adrcr) adrcr is an 8-bit readable/writable register that selects either address update mode 1 or address update mode 2 as the address output method. ??? adrctl 1 initial value 1 1 1 1 1 1 1 read/write ??? r/w ???? 76543210 reserved bits ???? address c ontrol selects address update mode 1 or address update mode 2 bit adrcr is initialized to h'ff by a reset and in ha rdware standby mode. it is not initialized in software standby mode. bits 7 to 1?reserved: read-only bits, always read as 1. bit 0?address control (adrctl): selects the address output method. bit 0 adrctl description 0 address update mode 2 is selected 1 address update mode 1 is selected (initial value) 6. bus controller rev.4.00 aug. 20, 2007 page 116 of 638 rej09b0395-0400 6.3 operation 6.3.1 area division the external address space is divided into areas 0 to 7. each area has a size of 128 kbytes in the 1- mbyte modes, or 2 mbytes in the 16-mbyte modes. figure 6.2 shows a general view of the memory map. h'00000 h'1ffff h'20000 h'3ffff h'40000 h'5ffff h'60000 h'7ffff h'80000 h'9ffff h'a0000 h'bffff h'c0000 h'dffff h'e0000 h'fffff area 0 (128 kbytes) area 1 (128 kbytes) area 2 (128 kbytes) area 3 (128 kbytes) area 4 (128 kbytes) area 5 (128 kbytes) area 6 (128 kbytes) area 7 (128 mbytes) h'000000 h'1fffff h'200000 h'3fffff h'400000 h'5fffff h'600000 h'7fffff h'800000 h'9fffff h'a00000 h'bfffff h'c00000 h'dfffff h'e00000 h'ffffff area 0 (2 mbytes) area 1 (2 mbytes) area 2 (2 mbytes) area 3 (2 mbytes) area 4 (2 mbytes) area 5 (2 mbytes) area 6 (2 mbytes) area 7 (2 mbytes) (a) 1-mbyte modes (modes 1 and 2) (b) 16-mbyte modes (modes 3 and 4) figure 6.2 access area ma p for each operating mode chip select signals ( cs 0 to cs 7 ) can be output for areas 0 to 7. the bus specifications for each area are selected in abwcr, astcr, wcrh, and wcrl. in 16-mbyte mode, the area division units can be selected with the rdea bit in bcr. 6. bus controller rev.4.00 aug. 20, 2007 page 117 of 638 rej09b0395-0400 h'000000 h'1fffff h'200000 h'3fffff h'400000 h'5fffff h'600000 h'7fffff h'800000 h'9fffff h'a00000 h'bfffff h'c00000 h'dfffff h'e00000 h'fee000 h'fee0ff h'fee100 h'ff7fff h'ff8000 h'ff8fff h'ff9000 h'ffef1f h'ffef20 h'fffeff h'ffff00 h'ffff1f h'ffff20 h'ffffe9 h'ffffea h'ffffff area 0 2 mbytes area 1 2 mbytes area 2 2 mbytes area 3 2 mbytes area 4 2 mbytes area 5 2 mbytes area 6 2 mbytes area 7 1.93 mbytes internal i/o re g isters (1) area 7 67.5 kbytes on-chip ram 4 kbytes internal i/o re g isters (2) area 7 22 bytes area 0 2 mbytes area 1 2 mbytes area 2 8 mbytes area 3 2 mbytes area 4 1.93 mbytes area 5 4 kbytes on-chip ram 4 kbytes * internal i/o re g isters (2) area 7 22 bytes area 6 23.75 kbytes internal i/o re g isters (1) 2 mbytes 2 mbytes 2 mbytes 2 mbytes 2 mbytes 2 mbytes 2 mbytes 2 mbytes absolute address 16 bits absolute address 8 bits (a) memory map when rdea = 1 note: * area 6 when the rame bit is cleared. (b) memory map when rdea = 0 reserved 39.75 kbytes figure 6.3 memory map in 16-mbyte mode 6. bus controller rev.4.00 aug. 20, 2007 page 118 of 638 rej09b0395-0400 6.3.2 bus specifications the external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. the bus width and number of access states for on- chip memory and internal i/o registers are fixed, and are not affected by the bus controller. bus width: a bus width of 8 or 16 bits can be selected with abwcr. an area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space. if all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit access, 16-bit bus mode is set. number of access states: two or three access states can be se lected with astcr. an area for which two-state access is selected functions as a two-state access space, and an area for which three-state access is selected func tions as a three-state access space. when two-state access space is designated, wait insertion is disabled. number of program wait states: when three-state access space is designated in astcr, the number of program wait states to be inserted automatically is selected with wcrh and wcrl. from 0 to 3 program wait states can be selected. table 6.3 shows the bus specifications for each basic bus interface area. 6. bus controller rev.4.00 aug. 20, 2007 page 119 of 638 rej09b0395-0400 table 6.3 bus specificati ons for each area (basic bus interface) abwcr astcr wcrh/wcrl bus specifications (basic bus interface) abwn astn wn1 wn0 bus width access states program wait states 0 0 ? ? 16 2 0 1 0 0 3 0 1 1 1 0 2 1 3 1 0 ? ? 8 2 0 1 0 0 3 0 1 1 1 0 2 1 3 note: n = 0 to 7 6.3.3 memory interfaces as its memory interface, the h8/3008 has only a ba sic bus interface that allows direct connection of rom, sram, and so on. it is not possible to select a dram interface that allows direct connection of dram, or a burst rom interface th at allows direct connection of burst rom. 6.3.4 chip select signals for each of areas 0 to 7, the h8/3008 can output a chip select signal ( cs 0 to cs 7 ) that goes low when the corresponding area is selected in expanded mode. figure 6.4 shows the output timing of a cs n signal. output of cs 0 to cs 3 : output of cs 0 to cs 3 is enabled or disabled in the data direction register (ddr) of the corresponding port. in the expanded modes with on-chip rom disabled, a reset leaves pin cs 0 in the output state and pins cs 1 to cs 3 in the input state. to output chip select signals cs 1 to cs 3 , the corresponding ddr bits must be set to 1. in the expanded modes with on-chip rom enabled, a reset leaves pins cs 0 to cs 3 in the input state. to output chip select signals cs 0 to cs 3 , the corresponding ddr bits must be set to 1. for details, see section 7, i/o ports. 6. bus controller rev.4.00 aug. 20, 2007 page 120 of 638 rej09b0395-0400 output of cs 4 to cs 7 : output of cs 4 to cs 7 is enabled or disabled in the chip select control register (cscr). a reset leaves pins cs 4 to cs 7 in the input state. to output chip select signals cs 4 to cs 7 , the corresponding cscr bits must be set to 1. for details, see section 7, i/o ports. address bus external address in area n cs n figure 6.4 cs n signal output timing (n = 0 to 7) when the on-chip rom, on-chip ram, a nd internal i/o registers are accessed, cs 0 to cs 7 remain high. the cs n signals are decoded from the address signa ls. they can be used as chip select signals for sram and other devices. 6.3.5 address output method the h8/3008 provides a choice of two address update methods: either the same method as in the previous h8/300h series (address update mode 1), or a method in which address updating is restricted to external space acc esses (address update mode 2). figure 6.5 shows examples of address output in these two update modes. on-chip memory cycle on-chip memory cycle external read cycle on-chip memory cycle external read cycle address bus (address update mode 1) address bus (address update mode 2) rd figure 6.5 sample address output in each address update mode (basic bus interface, 3-state space) 6. bus controller rev.4.00 aug. 20, 2007 page 121 of 638 rej09b0395-0400 address update mode 1: address update mode 1 is compatible with the previous h8/300h series. addresses are always updated between bus cycles. address update mode 2: in address update mode 2, address updating is performed only in external space accesses. in this mode, the address can be retained between an external space read cycle and an instruction fetch cycle (on-chip memory) by placing the program in on-chip memory. address update mode 2 is therefore useful when connecting a device that requires address hold time with respect to the rise of the rd strobe. switching between address update modes 1 and 2 is performed by means of the adrctl bit in adrcr. the initial value of adrcr is the a ddress update mode 1 setting, providing compatibility with the previous h8/300h series. cautions: the address output methods are designed so that the initial state w ith the bit selection method is compatible with the h8/3062f-ztat (hd64f3062) (i.e. address update mode 1). however, the following points should be noted. ? adrcr is allocated to address h'fee01e. in the h8/3062f-ztat, the corresponding address is empty space, but it is necessary to confirm that no accesses are made to h'fee01e in the program. ? when address update mode 2 is selected, the addr ess in an internal space (on-chip memory or internal i/o) access cycle is not output externally. ? in order to secure address holding with respect to the rise of rd , when address update mode 2 is used an external space read access must be completed within a single access cycle. for example, in a word access to 8-bit access space, the bus cycle is split into two as shown in figure 6.6, and so there is not a single access cy cle. in this case, address holding is not guaranteed at the rise of rd between the first (even address) and second (odd address) access cycles (area inside the ellipse in the figure). on-chip memory cycle on-chip memory cycle external read cycle (8-bit space word access) address update mode 2 rd even address odd address figure 6.6 example of consecutive external space accesses in address update mode 2 6. bus controller rev.4.00 aug. 20, 2007 page 122 of 638 rej09b0395-0400 6.4 basic bus interface 6.4.1 overview the basic bus interface enables direct connection of rom, sram, and so on. the bus specifications can be selected with abwcr, astcr, wcrh, and wcrl (see table 6.3). 6.4.2 data size and data alignment data sizes for the cpu and other internal bus masters are byte, word, and longword. the bus controller has a data alignment function, and when accessing extern al space, controls whether the upper data bus (d 15 to d 8 ) or lower data bus (d 7 to d 0 ) is used according to the bus specifications for the area being accessed (8-bit access area or 16-bit access area) and the data size. 8-bit access areas: figure 6.7 illustrates data alignment control for 8-bit access space. with 8-bit access space, the upper data bus (d 15 to d 8 ) is always used for accesses. the amount of data that can be accessed at one time is one byte: a word access is performed as two byte accesses, and a longword access, as four byte accesses. d 15 d 8 d 7 d 0 upper data bus lower data bus 1st bus cycle 2nd bus cycle 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle byte size word size lon g word size figure 6.7 access sizes and data a lignment control (8 -bit access area) 16-bit access areas: figure 6.8 illustrates data alignment control for 16-bit access areas. with 16-bit access areas, the upper data bus (d 15 to d 8 ) and lower data bus (d 7 to d 0 ) are used for accesses. the amount of data that can be accesse d at one time is one byte or one word, and a longword access is executed as two word accesses. 6. bus controller rev.4.00 aug. 20, 2007 page 123 of 638 rej09b0395-0400 in byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. the upper data bus is used for an even address, and the lower data bus for an odd address. d 15 d 8 d 7 d 0 upper data bus lower data bus 1st bus cycle 2nd bus cycle byte size lon g word size ? even address ? odd address word size byte size figure 6.8 access sizes and data a lignment control (16-bit access area) 6.4.3 valid strobes table 6.4 shows the data buses used, and the valid strobes, for the access spaces. in a read, the rd signal is valid for both the upper and the lower half of the data bus. in a write, the hwr signal is valid for the upper half of the data bus, and the lwr signal for the lower half. 6. bus controller rev.4.00 aug. 20, 2007 page 124 of 638 rej09b0395-0400 table 6.4 data buses used and valid strobes area access size read/ write address valid strobe upper data bus (d 15 to d 8 ) lower data bus (d 7 to d 0 ) 8-bit access byte read ? rd valid invalid area write ? hwr undetermined data 16-bit access byte read even rd valid invalid area odd invalid valid write even hwr valid undetermined data odd lwr undetermined data valid word read ? rd valid valid write ? hwr , lwr valid valid notes: 1. undetermined data means that unpredictable data is output. 2. invalid means that the bus is in the input state and the input is ignored. 6.4.4 memory areas the initial state of each area is basic bus interface, three-state access space. the initial bus width is selected according to the operating mode. areas 0 to 6: in the h8/3008, the entire space of areas 0 to 6 is external space. when area 0 to 6 external space is accessed, the cs 0 to cs 6 pin signals respectively can be output. the size of areas 0 to 6 is 128 kbytes in modes 1 and 2, and 2 mbytes in modes 3 and 4. area 7: area 7 includes the on-chip ram and internal i/o registers. in the h8/3008, the space excluding the on-chip ram and i/o registers is external space. the on-chip ram is enabled when the rame bit in the system control register (syscr) is set to 1; when the rame bit is cleared to 0, the on-chip ram is disabled and the corresponding space becomes external space . when area 7 external space is accessed, the cs 7 signal can be output. the size of area 7 is 128 kbytes in modes 1 and 2, and 2 mbytes in modes 3 and 4. 6. bus controller rev.4.00 aug. 20, 2007 page 125 of 638 rej09b0395-0400 6.4.5 basic bus control signal timing 8-bit, three-state-access areas: figure 6.9 shows the timing of bus control signals for an 8-bit, three-state-access area. the upper data bus (d 15 to d 8 ) is used in accesses to these areas. the lwr pin is always high. wait states can be inserted. bus cycle external address in area n valid invalid valid undetermined data hi g h address bus cs n as rd d 15 to d 8 d 7 to d 0 hwr lwr d 15 to d 8 d 7 to d 0 read access write access note: n = 7 to 0 t 1 t 2 t 3 figure 6.9 bus control signal timi ng for 8-bit, three-state-access area 6. bus controller rev.4.00 aug. 20, 2007 page 126 of 638 rej09b0395-0400 8-bit, two-state-access areas: figure 6.10 shows the timing of bus control signals for an 8-bit, two-state-access area. the upper data bus (d 15 to d 8 ) is used in accesses to these areas. the lwr pin is always high. wait states cannot be inserted. bus cycle external address in area n valid invalid valid undetermined data hi g h address bus cs n as rd d 15 to d 8 d 7 to d 0 hwr lwr d 15 to d 8 d 7 to d 0 read access write access note: n = 7 to 0 t 1 t 2 figure 6.10 bus control signal timing for 8-bit, two-state-access area 6. bus controller rev.4.00 aug. 20, 2007 page 127 of 638 rej09b0395-0400 16-bit, three-state-access areas: figures 6.11 to 6.13 show the timing of bus control signals for a 16-bit, three-state-access area. in these areas, the upper data bus (d 15 to d 8 ) is used in accesses to even addresses and the lower data bus (d 7 to d 0 ) in accesses to odd addresses. wait states can be inserted. bus cycle even external address in area n valid invalid valid hi g h address bus cs n as rd d 15 to d 8 d 7 to d 0 hwr lwr d 15 to d 8 d 7 to d 0 read access write access note: n = 7 to 0 t 1 t 2 t 3 undetermined data figure 6.11 bus control signal timing for 16-bit, three-state-access area (1) (byte access to even address) 6. bus controller rev.4.00 aug. 20, 2007 page 128 of 638 rej09b0395-0400 bus cycle odd external address in area n valid invalid valid address bus cs n as rd d 15 to d 8 d 7 to d 0 hwr lwr d 15 to d 8 d 7 to d 0 read access write access note: n = 7 to 0 t 1 t 2 t 3 hi g h undetermined data figure 6.12 bus control signal timing for 16-bit, three-state-access area (2) (byte access to odd address) 6. bus controller rev.4.00 aug. 20, 2007 page 129 of 638 rej09b0395-0400 bus cycle external address in area n valid valid address bus cs n as rd d 15 to d 8 d 7 to d 0 hwr lwr d 15 to d 8 d 7 to d 0 read access write access note: n = 7 to 0 t 1 t 2 t 3 valid valid figure 6.13 bus control signal timing for 16-bit, three-state-access area (3) (word access) 6. bus controller rev.4.00 aug. 20, 2007 page 130 of 638 rej09b0395-0400 16-bit, two-state-access areas: figures 6.14 to 6.16 show the timing of bus control signals for a 16-bit, two-state-access area. in these areas, the upper data bus (d 15 to d 8 ) is used in accesses to even addresses and the lower data bus (d 7 to d 0 ) in accesses to odd addresses. wait states cannot be inserted. bus cycle even external address in area n valid invalid valid hi g h address bus cs n as rd d 15 to d 8 d 7 to d 0 hwr lwr d 15 to d 8 d 7 to d 0 read access write access note: n = 7 to 0 t 1 t 2 undetermined data figure 6.14 bus control signal timing for 16-bit, two-state-access area (1) (byte access to even address) 6. bus controller rev.4.00 aug. 20, 2007 page 131 of 638 rej09b0395-0400 bus cycle odd external address in area n valid invalid valid hi g h address bus cs n as rd d 15 to d 8 d 7 to d 0 hwr lwr d 15 to d 8 d 7 to d 0 read access write access note: n = 7 to 0 t 1 t 2 undetermined data figure 6.15 bus control signal timing for 16-bit, two-state-access area (2) (byte access to odd address) 6. bus controller rev.4.00 aug. 20, 2007 page 132 of 638 rej09b0395-0400 bus cycle external address in area n valid valid address bus cs n as rd d 15 to d 8 d 7 to d 0 hwr lwr d 15 to d 8 d 7 to d 0 read access write access note: n = 7 to 0 t 1 t 2 valid valid figure 6.16 bus control signal timing for 16-bit, two-state-access area (3) (word access) 6.4.6 wait control when accessing external space, the h8/3008 can ex tend the bus cycle by inserting wait states (t w ). there are two ways of inserting wait states: program wait insertion and pin wait insertion using the wait pin. program wait insertion: from 0 to 3 wait states can be in serted automatically between the t 2 state and t 3 state on an individual area basis in three-state access space, according to the settings of wcrh and wcrl. 6. bus controller rev.4.00 aug. 20, 2007 page 133 of 638 rej09b0395-0400 pin wait insertion: setting the waite bit in bcr to 1 enables wait insertion by means of the wait pin. when external space is accessed in this state, a program wait is first inserted. if the wait pin is low at the falling edge of in the last t 2 or t w state, another t w state is inserted. if the wait pin is held low, t w states are inserted until it goes high. this is useful when inserting four or more t w states, or when changing the number of t w states for different external devices. the waite bit setting applies to all areas. figure 6.17 shows an example of the timing for insertion of one program wait state in 3-state space. wait address bus data bus read access write access data bus as rd t 1 t 2 t w t w t w t 3 hwr , lwr note: indicates the timin g of wait pin samplin g . inserted by pro g ram wait inserted by wait pin read data write data figure 6.17 example of wait state insertion timing 6. bus controller rev.4.00 aug. 20, 2007 page 134 of 638 rej09b0395-0400 6.5 idle cycle 6.5.1 operation when the h8/3008 chip accesses external sp ace, it can insert a 1-state idle cycle (t i ) between bus cycles in the following cases: wh en read accesses between differen t areas occur consecutively, and when a write cycle occurs immediately after a read cycle. by inserting an idle cycle it is possible, for example, to avoid data collisions between rom, which has a long output floating time, and high-speed memory, i/o interfaces, and so on. the initial value of the icis1 and icis0 bits in bcr is 1, so that idle cycle insertion is performed in the initial state. if there are no data collisions, the icis bits can be cleared. consecutive reads betw een different areas: if consecutive reads between different areas occur while the icis1 bit is set to 1 in bcr, an idle cycle is inserted at the start of the second read cycle. figure 6.18 shows an example of the operation in this case. in this example, bus cycle a is a read cycle from rom with a long output floating time, and bus cycle b is a read cycle from sram, each being located in a different area. in (a), an id le cycle is not inserted, and a collision occurs in bus cycle b between the read data from rom and that from sram. in (b ), an idle cycle is inserted, and a data collision is prevented. t 1 t 2 t 3 rd t 1 t 2 t 1 t 2 t 3 t i t 2 t 1 address bus data bus rd address bus data bus bus cycle a bus cycle b bus cycle a bus cycle b data collision lon g buffer-off time (a) idle cycle not inserted (b) idle cycle inserted figure 6.18 example of idle cycle operation (icis1 = 1) write after read: if an external write occurs after an external read while the icis0 bit is set to 1 in bcr, an idle cycle is inserted at the start of the write cycle. figure 6.19 shows an example of the operation in this case. in this example, bus cycle a is a read cycle from rom with a long output floating tim e, and bus cycle b is a cpu write cycle. 6. bus controller rev.4.00 aug. 20, 2007 page 135 of 638 rej09b0395-0400 in (a), an idle cycle is not inserted, and a collision occurs in bus cycle b between the read data from rom and the cpu write data. in (b), an idle cycle is inserted, and a data collision is prevented. t 1 t 2 t 3 rd address bus data bus t 1 t 2 t 1 t 2 t 3 t i t 2 t 1 hwr rd address bus data bus hwr bus cycle a bus cycle b bus cycle a bus cycle b lon g buffer-off time data collision (a) idle cycle not inserted (b) idle cycle inserted figure 6.19 example of idle cycle operation (icis0 = 1) usage note: when non-insertion of an idle cycle is specified, the rise (negation) of rd and fall (assertion) of cs n may occur simultaneously. figure 6.20 shows an example of the operation in this case. if consecutive reads to a different external area occur while the icis1 bit in bcr is cleared to 0, or if an external read is followed by a write cycle for a different external area while the icis0 bit is cleared to 0, negation of rd in the first read cycle and assertion of cs n in the following bus cycle will occur simultaneously. depending on the output delay time of each signal, therefore, it is possible that the rd low output in the previous read cycle and the cs n low output in the following bus cycle will overlap. as long as rd and cs n do not change simultaneously, or if there is no problem even if they do, non-insertion of an idle cycle can be specified. 6. bus controller rev.4.00 aug. 20, 2007 page 136 of 638 rej09b0395-0400 t 1 t 2 t 3 rd address bus t 1 t 2 t 1 t 2 t 3 t i t 2 t 1 cs n rd address bus cs n bus cycle a bus cycle b bus cycle a bus cycle b simultaneous chan g e of rd and cs n: possibility of mutual overlap (a) idle cycle not inserted (b) idle cycle inserted figure 6.20 example of idle cycle operation 6.5.2 pin states in idle cycle table 6.5 shows the pin states in an idle cycle. table 6.5 pin states in idle cycle pins pin state a 23 to a 0 next cycle address value d 15 to d 0 high impedance cs n high as high rd high hwr high lwr high 6. bus controller rev.4.00 aug. 20, 2007 page 137 of 638 rej09b0395-0400 6.6 bus arbiter the bus controller has a built-in bus arbiter that arbitrates between different bus masters. the bus master can be either the cpu or an external bus master. when a bus master has the bus right it can carry out read and write operations. each bus master uses a bus request signal to request the bus right. at fixed times the bus arbiter determines priority and uses a bus acknowledge signal to grant the bus to a bus master, which can the operate using the bus. the bus arbiter checks whether the bus request signal from a bus master is active or inactive, and returns an acknowledge signal to the bus master. when two or more bus masters request the bus, the highest-priority bus master receives an acknowl edge signal. the bus master that receives an acknowledge signal can continue to use the bus until the acknowledge signal is deactivated. the bus master priority order is: (high) external bus master > cpu (low) the bus arbiter samples the bus request signals and determines priority at all times, but it does not always grant the bus immediately, even when it receives a bus request from a bus master with higher priority than the current bus master. each bus master has certain times at which it can release the bus to a higher-priority bus master. 6.6.1 operation cpu: the cpu is the lowest-priority bus master. if an external bus master requests the bus while the cpu has the bus right, the bus arbiter transfers the bus right to the bus master that requested it. the bus right is transferred at the following times: ? the bus right is transferred at the boundary of a bus cycle. if word data is accessed by two consecutive byte accesses, however, the bus right is not transferred between the two byte accesses. ? if another bus master requests the bus while the cpu is performing internal operations, such as executing a multiply or divide instruction, the bus right is transferred immediately. the cpu continues its internal operations. ? if another bus master requests the bus while the cpu is in sleep mode, the bus right is transferred immediately. 6. bus controller rev.4.00 aug. 20, 2007 page 138 of 638 rej09b0395-0400 external bus master: when the brle bit is set to 1 in brcr, the bus can be released to an external bus master. the external bus master has highest priority, and requests the bus right from the bus arbiter driving the breq signal low. once the external bus master acquires the bus, it keeps the bus until the breq signal goes high. while the bus is released to an external bus master, the h8/3008 chip holds the address bus, data bus, bus control signals ( as , rd , hwr , and lwr ), and chip select signals ( cs n: n = 7 to 0) in the high-impedance state, and holds the back pin in the low output state. the bus arbiter samples the breq pin at the rise of the system clock ( ). if breq is low, the bus is released to the external bus mast er at the appropriate opportunity. the breq signal should be held low until the back signal goes low. when the breq pin is high in two consecutive samples, the back pin is driven high to end the bus-release cycle. figure 6.21 shows the timing when the bus right is requested by an external bus master during a read cycle in a two-state access ar ea. there is a minimum interval of three states from when the breq signal goes low until the bus is released. rd back (1) (2) (3) (4) (5) (6) breq hwr , lwr t 0 t 1 t 2 as data bus address bus cpu cycles cpu cycles external bus released hi g h address minimum 3 cycles hi g h-impedance hi g h-impedance hi g h-impedance hi g h-impedance hi g h-impedance figure 6.21 example of external bus master operation 6. bus controller rev.4.00 aug. 20, 2007 page 139 of 638 rej09b0395-0400 when making a transition to software standby mode, if there is contention with a bus request from an external bus master, the back and strobe states may be indefinite when the transition is made. when using software standby mode, clear the brle bit to 0 in brcr before executing the sleep instruction. 6.7 register and pin input timing 6.7.1 register write timing abwcr, astcr, wcrh, and wcrl write timing: data written to abwcr, astcr, wcrh, and wcrl takes effect starting from the next bus cycle. figure 6.22 shows the timing when an instruction fetched from area 0 changes area 0 from three-state access to two-state access. t 1 t 2 t 3 t 1 t 2 t 3 t 1 t 2 address bus 3-state access to area 0 2-state access to area 0 astcr address figure 6.22 astcr write timing ddr and cscr write timing: data written to ddr or cscr for the port corresponding to the cs n pin to switch between cs n output and generic input takes effect starting from the t 3 state of the ddr write cycle. figure 6. 23 shows the timing when the cs 1 pin is changed from generic input to cs 1 output. t 1 t 2 t 3 cs 1 address bus hi g h-impedance p8ddr address figure 6.23 ddr write timing brcr write timing: data written to brcr to switch between a 23 , a 22 , a 21 , or a 20 output and generic input or output takes effect starting from the t 3 state of the brcr write cycle. figure 6.24 shows the timing when a pin is changed from generic input to a 23 , a 22 , a 21 , or a 20 output. 6. bus controller rev.4.00 aug. 20, 2007 page 140 of 638 rej09b0395-0400 t 1 t 2 t 3 pa 7 to pa 4 ( a 23 to a 20 ) address bus brcr address hi g h-impedance figure 6.24 brcr write timing 6.7.2 breq pin input timing after driving the breq pin low, hold it low until back goes low. if breq returns to the high level before back goes lows, the bus arbiter may operate incorrectly. to terminate the external-b us-released state, hold the breq signal high for at least three states. if breq is high for too short an interval, th e bus arbiter may operate incorrectly. 7. i/o ports rev.4.00 aug. 20, 2007 page 141 of 638 rej09b0395-0400 section 7 i/o ports 7.1 overview the h8/3008 has six input/output ports (ports 4, 6, 8, 9, a, and b) and one input-only port (port 7). table 7.1 summarizes the port functions. the pins in each port are multiplexed as shown in table 7.1. each port has a data direction register (ddr) for selecting input or output, and a data register (dr) for storing output data. in addition to these registers, port 4 has an input pull-up mos control register (pcr) for switching input pull-up mos transistors on and off. ports 4, 6, and 8 can drive one ttl load and a 90- pf capacitive load . ports 9, a, and b can drive one ttl load and a 30-pf capacitive lo ad. ports 4, 6, 8, 9, a, and b can drive a darlington pair. pins p8 2 to p8 0 , pa 7 to pa 0 have schmitt-trigger input circuits. for block diagrams of the ports see appendix c, i/o port block diagrams. table 7.1 port functions expanded modes port description pins mode 1 mode 2 mode 3 mode 4 port 4 ? 8-bit i/o port ? built-in input pull-up mos p4 7 to p4 0 /d 7 to d 0 data input/output (d 7 to d 0 ) and 8-bit generic input/output 8-bit bus mode: generic input/output 16-bit bus mode: data input/output port 6 ? 8-bit i/o port p6 7 / clock output ( ) and generic input p6 6 / lwr p6 5 / hwr p6 4 / rd p6 3 / as bus control signal output ( lwr , hwr , rd , as ) p6 2 / back p6 1 / breq p6 0 / wait bus control signal input/output ( back , breq , wait ) and 3- bit generic input/output port 7 ? 8-bit i/o port p7 7 /an 7 /da 1 p7 6 /an 6 /da 0 analog input (an 7 , an 6 ) to a/d converter, analog output (da 1 , da 0 ) from d/a converter, and generic input p7 5 to p7 0 / an 5 to an 0 analog input (an 5 to an 0 ) to a/d converter, and generic input 7. i/o ports rev.4.00 aug. 20, 2007 page 142 of 638 rej09b0395-0400 expanded modes port description pins mode 1 mode 2 mode 3 mode 4 port 8 p8 4 / cs 0 ddr = 0: generic input ddr = 1 (reset value): cs 0 output ? 5-bit i/o port ? p8 2 to p8 0 have schmitt inputs p8 3 / irq 3 / cs 1 / adtrg irq 3 input, cs 1 output, external trigger input ( adtrg ) to a/d converter, and generic input ddr = 0 (after reset): generic input ddr = 1: cs 1 output p8 2 / irq 2 / cs 2 p8 1 / irq 1 / cs 3 irq 2 and irq 1 input, cs 2 and cs 3 output, and generic input ddr = 0 (after reset): generic input ddr = 1: cs 2 and cs 3 output p8 0 / irq 0 irq 0 input, and generic input/output port 9 ? 6-bit i/o port p9 5 / irq 5 /sck 1 p9 4 / irq 4 /sck 0 p9 3 /rxd 1 p9 2 /rxd 0 p9 1 /txd 1 p9 0 /txd 0 input and output (sck 1 , sck 0 , rxd 1 , rxd 0 , txd 1 , txd 0 ) for serial communication interfaces 1 and 0 (sci1/0), irq 5 and irq 4 input, and 6-bit generic input/output port a ? 8-bit i/o port ? schmitt inputs pa 7 /tp 7 / tiocb 2 /a 20 output (tp 7 ) from pro- grammable timing pattern controller (tpc), input or output (tiocb 2 ) for 16-bit timer and generic input/output address output (a 20 ) pa 6 /tp 6 /tioca 2 /a 21 pa 5 /tp 5 /tiocb 1 /a 22 pa 4 /tp 4 /tioca 1 /a 23 tpc output (tp 6 to tp 4 ), 16-bit timer input and output (tioca 2 , tiocb 1 , tioca 1 ), and generic input/output pa 3 /tp 3 /tiocb 0 / tclkd pa 2 /tp 2 /tioca 0 / tclkc pa 1 /tp 1 /tclkb pa 0 /tp 0 /tclka tpc output (tp 3 to tp 0 ), 16-bit timer input and output (tiocb 0 , tioca 0 , tclkd, tclkc, tclkb, tclka), 8-bit timer input (tclkd, tclkc, tclkb, tclka), and generic input/output 7. i/o ports rev.4.00 aug. 20, 2007 page 143 of 638 rej09b0395-0400 expanded modes port description pins mode 1 mode 2 mode 3 mode 4 port b ? 8-bit i/o port pb 7 /tp 15 pb 6 /tp 14 pb 5 /tp 13 pb 4 /tp 12 tpc output (tp 15 to tp 12 ) and generic input/output pb 3 /tp 11 /tmio 3 / cs 4 pb 2 /tp 10 /tmo 2 / cs 5 pb 1 /tp 9 /tmio 1 / cs 6 pb 0 /tp 8 /tmo 0 / cs 7 tpc output (tp 11 to tp 8 ), 8-bit timer input and output (tmio 3 , tmo 2 , tmio 1 , tmo 0 ), cs 7 to cs 4 output, and generic input/output legend: sci0: serial communication interface channel 0 sci1: serial communication interface channel 1 tpc: programmable timing pattern controller 16tim: 16-bit timer 8tim: 8-bit timer 7. i/o ports rev.4.00 aug. 20, 2007 page 144 of 638 rej09b0395-0400 7.2 port 4 7.2.1 overview port 4 is an 8-bit input/output port which also functions as a data bus. it's pin configuration is shown in figure 7.1. the pin functions differ depending on the operating mode. in the h8/3008, when the bus width control register (abwcr) designates areas 0 to 7 all as 8-bit- access areas, the chip operates in 8-bit bus mode a nd port 4 is a generic inpu t/output port. when at least one of areas 0 to 7 is designated as a 16-b it-access area, the chip oper ates in 16-bit bus mode and port 4 becomes part of the data bus. port 4 has software-programmable built-in pull-up mos. pins in port 4 can drive one ttl load and a 90-pf capacitive load. they can also drive a darlington transistor pair. port 4 p4 /d p4 /d p4 /d p4 /d p4 /d p4 /d p4 /d p4 /d 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 p4 (input/output)/d 7 (input/output) p4 (input/output)/d 6 (input/output) p4 (input/output)/d 5 (input/output) p4 (input/output)/d 4 (input/output) p4 (input/output)/d 3 (input/output) p4 (input/output)/d 2 (input/output) p4 (input/output)/d 1 (input/output) p4 (input/output)/d 0 (input/output) 7 6 5 4 3 2 1 0 port 4 pins modes 1 to 4 figure 7.1 port 4 pin configuration 7. i/o ports rev.4.00 aug. 20, 2007 page 145 of 638 rej09b0395-0400 7.2.2 register descriptions table 7.2 summarizes the registers of port 4. table 7.2 port 4 registers address * name abbreviation r/w initial value h'ee003 port 4 data direction register p4ddr w h'00 h'fffd3 port 4 data register p4dr r/w h'00 h'ee03e port 4 input pull-up mos control register p4pcr r/w h'00 note: * lower 20 bits of the address in advanced mode. port 4 data directio n register (p4ddr): p4ddr is an 8-bit write-onl y register that can select input or output for each pin in port 4. bit initial value read/write 7 p4 ddr 0 w port 4 data dire c tion 7 to 0 these bits select input or output for port 4 pins 7 6 p4 ddr 0 w 6 5 p4 ddr 0 w 5 4 p4 ddr 0 w 4 3 p4 ddr 0 w 3 2 p4 ddr 0 w 2 1 p4 ddr 0 w 1 0 p4 ddr 0 w 0 when all areas are designated as 8-bit-access ar eas by the bus controlle r's bus width control register (abwcr), selecting 8-bit bus mode, port 4 functions as an input/output port. in this case, a pin in port 4 becomes an output port if the corresponding p4ddr bit is set to 1, and an input port if this bit is cleared to 0. when at least one area is designated as a 16-b it-access area, selecting 16-bit bus mode, port 4 functions as part of the data bus, regardless of the p4ddr settings. p4ddr is a write-only register. its value cannot be read. all bits return 1 when read. p4ddr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. abwcr and p4ddr are not initialized in software standby mode. therefore, if a transition is made to software standby mode while port 4 is functioning as an input/output port and a p4ddr bit is set to 1, the corresponding pin maintains its output state. 7. i/o ports rev.4.00 aug. 20, 2007 page 146 of 638 rej09b0395-0400 port 4 data register (p4dr): p4dr is an 8-bit readable/writable register that stores output data for port 4. when port 4 functions as an output port, the value of this register is output. when a bit in p4ddr is set to 1, if port 4 is read the value of the corresponding p4dr bit is returned. when a bit in p4ddr is cleared to 0, if port 4 is read the corresponding pin logic level is read. bit initial value read/write 7 p4 0 r/w port 4 data 7 to 0 these bits store data for port 4 pins 7 6 p4 0 r/w 6 5 p4 0 r/w 5 4 p4 0 r/w 4 3 p4 0 r/w 3 2 p4 0 r/w 2 1 p4 0 r/w 1 0 p4 0 r/w 0 p4dr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. port 4 input pull-up mos control register (p4pcr): p4pcr is an 8-bit readable/writable register that controls the mos input pull-up transistors in port 4. bit initial value read/write 7 p4 pcr 0 r/w port 4 input pull-up mos c ontrol 7 to 0 these bits control input pull-up mos transistors built into port 4 7 6 p4 pcr 0 r/w 6 5 p4 pcr 0 r/w 5 4 p4 pcr 0 r/w 4 3 p4 pcr 0 r/w 3 2 p4 pcr 0 r/w 2 1 p4 pcr 0 r/w 1 0 p4 pcr 0 r/w 0 in 8-bit bus mode in modes 1 to 4 (expanded modes), when a p4ddr bit is cleared to 0 (selecting generic input), if the corresponding p4pcr bit is set to 1, the input pull-up mos transistor is turned on. p4pcr is initialized to h'00 by a reset and in hard ware standby mode. in software standby mode it retains its previous setting. 7. i/o ports rev.4.00 aug. 20, 2007 page 147 of 638 rej09b0395-0400 table 7.3 summarizes the states of th e input pull-up mos in each operating mode. table 7.3 input pull-up mos transistor states (port 4) mode reset hardware standby mode software standby mode other modes 1 to 4 8-bit bus mode off off on/off on/off 16-bit bus mode off off legend: off: the input pull-up mos transistor is always off. on/off: the input pull-up mos transistor is on if p4pcr = 1 and p4ddr = 0. otherwise, it is off. 7. i/o ports rev.4.00 aug. 20, 2007 page 148 of 638 rej09b0395-0400 7.3 port 6 7.3.1 overview port 6 is an 8-bit input/output port that is also used for input and output of bus control signals ( lwr , hwr , rd , as , back , breq , wait ) and for clock ( ) output. the port 6 pin configuration is shown in figure 7.2. see table 7.5 for the selection of the pin functions. pins in port 6 can drive one ttl load and a 90-pf capacitive load. they can also drive a darlington transistor pair. port 6 p6 / p6 / p6 / p6 / p6 / p6 / p6 / p6 / 7 6 5 4 3 2 1 0 lwr hwr rd as back breq wait port 6 pins modes 1 to 4 (expanded modes) p6 7 (input)/ (output) lwr (output) hwr (output) rd (output) as (output) p6 2 (input/output)/ back (output) p6 1 (input/output)/ breq (input) p6 0 (input/output)/ wait (input) figure 7.2 port 6 pin configuration 7.3.2 register descriptions table 7.4 summarizes the registers of port 6. table 7.4 port 6 registers address * name abbreviation r/w initial value h'ee005 port 6 data direction register p6ddr w h'80 h'fffd5 port 6 data register p6dr r/w h'80 note: * lower 20 bits of the address in advanced mode. port 6 data directio n register (p6ddr): p6ddr is an 8-bit write-onl y register that can select input or output for each pin in port 6. 7. i/o ports rev.4.00 aug. 20, 2007 page 149 of 638 rej09b0395-0400 bit 7 is reserved. it is fixed at 1, and cannot be modified. bit initial value read/write 7 ? 1 ? 6 p6 ddr 0 w 6 5 p6 ddr 0 w 5 4 p6 ddr 0 w 4 3 p6 ddr 0 w 3 2 p6 ddr 0 w 2 1 p6 ddr 0 w 1 0 p6 ddr 0 w 0 port 6 data dire c tion 6 to 0 these bits select input or output for port 6 pins reserved bit ? modes 1 to 4 (expanded modes) p6 7 functions as the clock output pin ( ) or an input port. p6 7 is the clock output pin ( ) if the pstop bit in mstrch is cleared to 0 (initial value), and an input port if this bit is set to 1. p6 6 to p6 3 function as bus control output pins ( lwr , hwr , rd , and as ), regardless of the settings of bits p6 6 ddr to p6 3 ddr. p6 2 to p6 0 function as bus control input/output pins ( back , breq , and wait ) or input/output ports. for the method of selecting the pin functions, see table 7.7. when p6 2 to p6 0 function as input/output ports, the pin becomes an output port if the corresponding p6ddr bit is set to 1, and an input port if this bit is cleared to 0. port 6 data register (p6dr): p6dr is an 8-bit readable/writable register that stores output data for port 6. when port 6 functions as an output port, the value of this register is output. for bit 7, a value of 1 is returned if the bit is read while the pstop bit in mstcrh is cleared to 0, and the p6 7 pin logic level is returned if the bit is read while the pstop bit is set to 1. bit 7 cannot be modified. for bits 6 to 0, the pin logic level is returned if the bit is read while the corresponding bit in p6ddr is cleared to 0, and the p6dr va lue is returned if the bit is read while the corresponding bit in p6ddr is set to 1. bit initial value read/write 7 p6 7 1 r 6 p6 0 r/w 6 5 p6 0 r/w 5 4 p6 0 r/w 4 3 p6 0 r/w 3 2 p6 0 r/w 2 1 p6 0 r/w 1 0 p6 0 r/w 0 port 6 data 7 to 0 these bits store data for port 6 pins p6dr is initialized to h'80 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. 7. i/o ports rev.4.00 aug. 20, 2007 page 150 of 638 rej09b0395-0400 table 7.5 port 6 pin functions in modes 1 to 4 pin pin functions and selection method p6 7 / bit pstop in mstcrh selects the pin function. pstop 0 1 pin function output p6 7 input lwr functions as lwr regardless of the setting of bit p6 6 ddr p6 6 ddr 0 1 pin function lwr output hwr functions as hwr regardless of the setting of bit p6 5 ddr p6 5 ddr 0 1 pin function hwr output rd functions as rd regardless of the setting of bit p6 4 ddr p6 4 ddr 0 1 pin function rd output as functions as as regardless of the setting of bit p6 3 ddr p6 3 ddr 0 1 pin function as output p6 2 / back bit brle in brcr and bit p6 2 ddr select the pin function as follows. brle 0 1 p6 2 ddr 0 1 ? pin function p6 2 input p6 2 output back output p6 1 / breq bit brle in brcr and bit p6 1 ddr select the pin function as follows. brle 0 1 p6 1 ddr 0 1 ? pin function p6 1 input p6 1 output breq input p6 0 / wait bit waite in bcr and bit p6 0 ddr select the pin function as follows. waite 0 1 p6 0 ddr 0 1 0 * pin function p6 0 input p6 0 output wait input note: * do not set bit p6 0 ddr to 1. 7. i/o ports rev.4.00 aug. 20, 2007 page 151 of 638 rej09b0395-0400 7.4 port 7 7.4.1 overview port 7 is an 8-bit input port that is also used for analog input to the a/d converter and analog output from the d/a converter. the pin functions are the same in all operating modes. figure 7.3 shows the pin configuration of port 7. see section 14, a/d converter, for details of the a/d converter analog input pins, and section 15, d/a converter, for details of the d/a converter analog output pins. port 7 p7 (input)/an (input)/da (output) p7 (input)/an (input)/da (output) p7 (input)/an (input) p7 (input)/an (input) p7 (input)/an (input) p7 (input)/an (input) p7 (input)/an (input) p7 (input)/an (input) 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 port 7 pins 1 0 figure 7.3 port 7 pin configuration 7.4.2 register description table 7.6 summarizes the port 7 register. port 7 is an input port, and port 7 has no data direction register. table 7.6 port 7 data register address * name abbreviation r/w initial value h'fffd6 port 7 data register p7dr r undetermined note: * lower 20 bits of the address in advanced mode. 7. i/o ports rev.4.00 aug. 20, 2007 page 152 of 638 rej09b0395-0400 port 7 data register (p7dr) bit initial value read/write 0 p7 ? r * note: * 0 1 p7 ? r * 1 2 p7 ? r * 2 3 p7 ? r * 3 4 p7 ? r * 4 5 p7 ? r * 5 6 p7 ? r * 6 7 p7 ? r * 7 70 determined by pins p7 to p7 . when port 7 is read, the pin logic levels are always read. p7dr cannot be modified. 7.5 port 8 7.5.1 overview port 8 is a 5-bit input/output port that is also used for cs 3 to cs 0 output, irq 3 to irq 0 input, and a/d converter adtrg input. figure 7.4 shows the pin configuration of port 8. in the h8/3008, port 8 can provide cs 3 to cs 0 output, irq 3 to irq 0 input, and adtrg input. see table 7.8 for the selection of pin functions in expanded modes. see section 14, a/d converter, for a description of the a/d converter's adtrg input pin. the irq 3 to irq 0 functions are selected by ier settings, regardless of whether the pin is used for input or output. caution is therefore required. for details see section 5.3.1, external interrupts. pins in port 8 can drive one ttl load and a 90-pf capacitive load. they can also drive a darlington transistor pair. pins p8 2 to p8 0 have schmitt-trigger inputs. 7. i/o ports rev.4.00 aug. 20, 2007 page 153 of 638 rej09b0395-0400 port 8 p8 / p8 / / p8 / / p8 / / p8 / 4 3 2 1 0 0 1 2 3 port 8 pins cs cs cs cs 3 2 1 irq / adtrg irq irq irq 0 p8 (input)/ (output) p8 (input)/ (output)/ (input) / adtrg (input) p8 (input)/ (output)/ (input) p8 (input)/ (output)/ (input) p8 (input/output)/ (input) 4 3 2 1 0 0 1 2 3 cs cs cs cs 3 2 1 irq irq irq irq 0 figure 7.4 port 8 pin configuration 7.5.2 register descriptions table 7.7 summarizes the registers of port 8. table 7.7 port 8 registers address * name abbreviation r/w initial value h'ee007 port 8 data direction register p8ddr w h'f0 h'fffd7 port 8 data register p8dr r/w h'e0 note: * lower 20 bits of the address in advanced mode. port 8 data directio n register (p8ddr): p8ddr is an 8-bit write-onl y register that can select input or output for each pin in port 8. bits 7 to 5 are reserved. they are fixed at 1, and cannot be modified. 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 p8 ddr 1 w 4 3 p8 ddr 0 w 3 2 p8 ddr 0 w 2 1 p8 ddr 0 w 1 0 p8 ddr 0 w 0 reserved bits port 8 data dire c tion 4 to 0 these bits select input or output for port 8 pins bit initial value read/write when bits in p8ddr bit are set to 1, p8 4 to p8 1 become cs 0 to cs 3 output pins. when bits in p8ddr are cleared to 0, the corresponding pins become input ports. 7. i/o ports rev.4.00 aug. 20, 2007 page 154 of 638 rej09b0395-0400 in the h8/3008, following a reset p8 4 functions as the cs 0 output, while cs 1 to cs 3 are input ports. p8ddr is a write-only register. its value cannot be read. all bits return 1 when read. p8ddr is initialized to h'f0 by a reset and in hardware standby mode. in software standby mode p8ddr retains its previous setting. therefore, if a transition is made to software standby mode while port 8 is functioning as an input/output port and a p8ddr bit is set to 1, the corresponding pin maintains its output state. port 8 data register (p8dr): p8dr is an 8-bit readable/writable register that stores output data for port 8. when port 8 functions as an output port, the value of this register is output. when a bit in p8ddr is set to 1, if port 8 is read the value of the corresponding p8dr bit is returned. when a bit in p8ddr is cleared to 0, if port 8 is read the corresponding pin logic level is read. bits 7 to 5 are reserved. they are fixed at 1, and cannot be modified. bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 p8 0 r/w 4 3 p8 0 r/w 3 2 p8 0 r/w 2 1 p8 0 r/w 1 0 p8 0 r/w 0 reserved bits port 8 data 4 to 0 these bits store data for port 8 pins p8dr is initialized to h'e0 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. 7. i/o ports rev.4.00 aug. 20, 2007 page 155 of 638 rej09b0395-0400 table 7.8 port 8 pin functions in modes 1 to 4 pin pin functions and selection method p8 4 / cs 0 bit p8 4 ddr selects the pin function as follows. p8 4 ddr 0 1 pin function p8 4 input cs 0 output p8 3 / cs 1 / irq 3 / bit p8 3 ddr selects the pin function as follows adtrg p8 3 ddr 0 1 pin function p8 3 input cs 1 output irq 3 input adtrg input p8 2 / cs 2 / irq 2 bit p8 2 ddr selects the pin function as follows. p8 2 ddr 0 1 pin function p8 2 input cs 2 output irq 2 input p8 1 / cs 3 / irq 1 bit p8 1 ddr selects the pin function as follows. p8 1 ddr 0 1 pin function p8 1 input cs 3 output irq 1 input p8 0 / irq 0 bit p8 0 ddr selects the pin function as follows. p8 0 ddr 0 1 pin function p8 0 input p8 0 output irq 0 input 7. i/o ports rev.4.00 aug. 20, 2007 page 156 of 638 rej09b0395-0400 7.6 port 9 7.6.1 overview port 9 is a 6-bit input/output port that is also used for input and output (txd 0 , txd 1 , rxd 0 , rxd 1 , sck 0 , sck 1 ) by serial communication in terface channels 0 and 1 (sci0 and sci1), and for irq 5 and irq 4 input. see table 7.10 for the selection of pin functions. the irq 5 and irq 4 functions are selected by ier settings, regardless of whether the pin is used for input or output. caution is therefore required. for details see section 5.3.1, external interrupts. port 9 has the same set of pin functions in all operating modes. figure 7.5 shows the pin configuration of port 9. pins in port 9 can drive one ttl load and a 30-pf capacitive load. they can also drive a darlington transistor pair. port 9 p9 (input/output)/sck p9 (input/output)/sck p9 (input/output)/rxd (input) p9 (input/output)/rxd (input) p9 (input/output)/txd (output) p9 (input/output)/txd (output) 5 4 3 2 1 0 port 9 pins 1 0 (input/output)/ irq (input) (input/output)/ irq (input) 5 4 1 0 1 0 figure 7.5 port 9 pin configuration 7. i/o ports rev.4.00 aug. 20, 2007 page 157 of 638 rej09b0395-0400 7.6.2 register descriptions table 7.9 summarizes the registers of port 9. table 7.9 port 9 registers address * name abbreviation r/w initial value h'ee008 port 9 data direction register p9ddr w h'c0 h'fffd8 port 9 data register p9dr r/w h'c0 note: * lower 20 bits of the address in advanced mode. port 9 data directio n register (p9ddr): p9ddr is an 8-bit write-onl y register that can select input or output for each pin in port 9. bits 7 and 6 are reserved. they are fixed at 1, and cannot be modified. bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 p9 ddr 0 w 5 4 p9 ddr 0 w 4 3 p9 ddr 0 w 3 2 p9 ddr 0 w 2 1 p9 ddr 0 w 1 0 p9 ddr 0 w 0 reserved bits port 9 data dire c tion 5 to 0 these bits select input or output for port 9 pins when port 9 functions as an input/output port, a pin in port 9 becomes an output port if the corresponding p9ddr bit is set to 1, and an input port if this bit is cleared to 0. for the method of selecting the pin functions, see table 7.10. p9ddr is a write-only register. its value cannot be read. all bits return 1 when read. p9ddr is initialized to h'c0 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. therefore, if a transition is made to software standby mode while port 9 is functioning as an input/output port and a p9ddr bit is set to 1, the corresponding pin maintains its output state. 7. i/o ports rev.4.00 aug. 20, 2007 page 158 of 638 rej09b0395-0400 port 9 data register (p9dr): p9dr is an 8-bit readable/writable register that stores output data for port 9. when port 9 functions as an output port, the value of this register is output. when a bit in p9ddr is set to 1, if port 9 is read the value of the corresponding p9dr bit is returned. when a bit in p9ddr is cleared to 0, if port 9 is read the corresponding pin logic level is read. bits 7 and 6 are reserved. they are fixed at 1, and cannot be modified. bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 p9 0 r/w 4 p9 0 r/w 4 3 p9 0 r/w 3 2 p9 0 r/w 2 1 p9 0 r/w 1 0 p9 0 r/w 0 reserved bits port 9 data 5 to 0 these bits store data for port 9 pins 5 p9dr is initialized to h'c0 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. 7. i/o ports rev.4.00 aug. 20, 2007 page 159 of 638 rej09b0395-0400 table 7.10 port 9 pin functions pin pin functions and selection method p9 5 /sck 1 / irq 5 bit c/ a in smr of sci1, bits cke0 and cke1 in scr, and bit p9 5 ddr select the pin function as follows. cke1 0 1 c/ a 0 1 ? cke0 0 1 ? ? p9 5 ddr 0 1 ? ? ? pin function p9 5 input p9 5 output sck 1 output sck 1 output sck 1 input irq 5 input p9 4 /sck 0 / irq 4 bit c/ a in smr of sci0, bits cke0 and cke1 in scr, and bit p9 4 ddr select the pin function as follows. cke1 0 1 c/ a 0 1 ? cke0 0 1 ? ? p9 4 ddr 0 1 ? ? ? pin function p9 4 input p9 4 output sck 0 output sck 0 output sck 0 input irq 4 input p9 3 /rxd 1 bit re in scr of sci1, bit smif in scmr, and bit p9 3 ddr select the pin function as follows. smif 0 1 re 0 1 ? p9 3 ddr 0 1 ? ? pin function p9 3 input p9 3 output rxd 1 input rxd 1 input p9 2 /rxd 0 bit re in scr of sci0, bit smif in scmr, and bit p9 2 ddr select the pin function as follows. smif 0 1 re 0 1 ? p9 2 ddr 0 1 ? ? pin function p9 2 input p9 2 output rxd 0 input rxd 0 input 7. i/o ports rev.4.00 aug. 20, 2007 page 160 of 638 rej09b0395-0400 pin pin functions and selection method p9 1 /txd 1 bit te in scr of sci1, bit smif in scmr, and bit p9 1 ddr select the pin function as follows. smif 0 1 te 0 1 ? p9 1 ddr 0 1 ? ? pin function p9 1 input p9 1 output txd 1 output txd 1 output * note: * functions as the txd 1 output pin, but there are two states: one in which the pin is driven, and another in which the pin is at high-impedance. p9 0 /txd 0 bit te in scr of sci0, bit smif in scmr, and bit p9 0 ddr select the pin function as follows. smif 0 1 te 0 1 ? p9 0 ddr 0 1 ? ? pin function p9 0 input p9 0 output txd 0 output txd 0 output * note: * functions as the txd 0 output pin, but there are two states: one in which the pin is driven, and another in which the pin is at high-impedance. 7. i/o ports rev.4.00 aug. 20, 2007 page 161 of 638 rej09b0395-0400 7.7 port a 7.7.1 overview port a is an 8-bit input/output port that is also used for output (tp 7 to tp 0 ) from the programmable timing pattern controller (tpc), input and output (tiocb 2 , tioca 2 , tiocb 1 , tioca 1 , tiocb 0 , tioca 0 , tclkd, tclkc, tclkb, tclka) by the 16-bit timer, clock input (tclkd, tclkc, tclkb, tclka) to the 8-bit timer, and address output (a 23 to a 20 ). a reset or hardware standby transition leaves port a as an input port, except that in modes 3 and 4, one pin is always used for a 20 output. see tables 7.12 to 7.14 for the selection of pin functions. usage of pins for tpc, 16-bit timer, and 8-bit timer input and output is described in the sections on those modules. for output of address bits a 23 to a 20 in modes 3 and 4, see section 6.2.4, bus release control register (brcr). pins not assigned to any of these functions are available for generic input/output. figure 7.6 shows the pin configuration of port a. pins in port a can drive one ttl load and a 30-pf capacitive load. they can also drive a darlington transistor pair. port a has schmitt-trigger inputs. 7. i/o ports rev.4.00 aug. 20, 2007 page 162 of 638 rej09b0395-0400 port a pa /tp /tiocb /a pa /tp /tioca /a 21 pa /tp /tiocb /a 22 pa /tp /tioca /a 23 pa /tp /tiocb /tclkd pa /tp /tioca /tclkc pa /tp /tclkb pa /tp /tclka 7 6 5 4 3 2 1 0 port a pins 7 6 5 4 3 2 1 0 2 2 1 1 0 0 7 6 5 4 3 2 1 0 pin fun c tions in modes 1 and 2 pa (input/output)/tp (output)/tiocb (input/output) pa (input/output)/tp (output)/tioca (input/output) pa (input/output)/tp (output)/tiocb (input/output) pa (input/output)/tp (output)/tioca (input/output) pa (input/output)/tp (output)/tiocb (input/output)/tclkd (input) pa (input/output)/tp (output)/tioca (input/output)/tclkc (input) pa (input/output)/tp (output)/tclkb (input) pa (input/output)/tp (output)/tclka (input) 7 6 5 4 3 2 1 0 2 2 1 1 0 0 20 6 5 4 3 2 1 0 pin fun c tions in modes 3 and 4 a (output) pa (input/output)/tp (output)/tioca (input/output)/a (output) pa (input/output)/tp (output)/tiocb (input/output)/a (output) pa (input/output)/tp (output)/tioca (input/output)/a (output) pa (input/output)/tp (output)/tiocb (input/output)/tclkd (input) pa (input/output)/tp (output)/tioca (input/output)/tclkc (input) pa (input/output)/tp (output)/tclkb (input) pa (input/output)/tp (output)/tclka (input) 6 5 4 3 2 1 0 2 1 1 0 0 20 21 22 23 figure 7.6 port a pin configuration 7.7.2 register descriptions table 7.11 summarizes the registers of port a. table 7.11 port a registers initial value address * name r/w modes 1 and 2 modes 3 and 4 h'ee009 port a data direction register paddr w h'00 h'80 h'fffd9 port a data register padr r/w h'00 h'00 note: * lower 20 bits of the address in advanced mode. 7. i/o ports rev.4.00 aug. 20, 2007 page 163 of 638 rej09b0395-0400 port a data direct ion register (paddr): paddr is an 8-bit write-only register that can select input or output for each pin in port a. when pins are used for tpc output, the corresponding paddr bits must also be set. 7 pa ddr 1 ? 0 w port a data dire c tion 7 to 0 these bits select input or output for port a pins 7 6 pa ddr 0 w 0 w 6 5 pa ddr 0 w 0 w 5 4 pa ddr 0 w 0 w 4 3 pa ddr 0 w 0 w 3 2 pa ddr 0 w 0 w 2 1 pa ddr 0 w 0 w 1 0 pa ddr 0 w 0 w 0 bit modes 3 and 4 initial value read/write initial value read/write modes 1 and 2 the pin functions that can be selected for pins pa 7 to pa 4 differ between modes 1 and 2, and modes 3 and 4. for the method of selecting the pin functions, see tables 7.12 and 7.13. the pin functions that can be selected for pins pa 3 to pa 0 are the same in modes 1 to 4. for the method of selecting the pin functions, see table 7.14. when port a functions as an input/output port, a pin in port a becomes an output port if the corresponding paddr bit is set to 1, and an input port if this bit is cleared to 0. in modes 3 and 4, pa 7 ddr is fixed at 1 and pa 7 functions as the a 20 address output pin. paddr is a write-only register. its value cannot be read. all bits return 1 when read. paddr is initialized to h'00 by a reset and in ha rdware standby mode in modes 1 and 2. it is initialized to h'80 by a reset and in hardware stan dby mode in modes 3 and 4. in software standby mode it retains its previous setting. therefore, if a transition is made to software standby mode while port a is functioning as an input/output port and a paddr bit is set to 1, the corresponding pin maintains its output state. 7. i/o ports rev.4.00 aug. 20, 2007 page 164 of 638 rej09b0395-0400 port a data register (padr): padr is an 8-bit readable/writa ble register that stores output data for port a. when port a functions as an output port, the value of this register is output. when a bit in paddr is set to 1, if port a is read th e value of the corresponding padr bit is returned. when a bit in paddr is cleared to 0, if port a is read the corresponding pin logic level is read. bit initial value read/write 0 pa 0 r/w 0 1 pa 0 r/w 1 2 pa 0 r/w 2 3 pa 0 r/w 3 4 pa 0 r/w 4 5 pa 0 r/w 5 6 pa 0 r/w 6 7 pa 0 r/w 7 port a data 7 to 0 these bits store data for port a pins padr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. 7. i/o ports rev.4.00 aug. 20, 2007 page 165 of 638 rej09b0395-0400 table 7.12 port a pin functions (modes 1 and 2) pin pin functions and selection method pa 7 /tp 7 / tiocb 2 bit pwm2 in tmdr, bits iob2 to iob0 in tior2, bit nder7 in ndera, and bit pa 7 ddr select the pin function as follows. 16-bit timer channel 2 settings (1) in table below (2) in table below pa 7 ddr ? 0 1 1 nder7 ? ? 0 1 pin function tiocb 2 output pa 7 input pa 7 output tp 7 output tiocb 2 input * note: * tiocb 2 input when iob2 = 1 and pwm2 = 0. 16-bit timer channel 2 settings (2) (1) (2) iob2 0 1 iob1 0 0 1 ? iob0 0 1 ? ? pa 6 /tp 6 / tioca 2 bit pwm2 in tmdr, bits ioa2 to ioa0 in tior2, bit nder6 in ndera, and bit pa 6 ddr select the pin function as follows. 16-bit timer channel 2 settings (1) in table below (2) in table below pa 6 ddr ? 0 1 1 nder6 ? ? 0 1 pin function tioca 2 output pa 6 input pa 6 output tp 6 output tioca 2 input * note: * tioca 2 input when ioa2 = 1. 16-bit timer channel 2 settings (2) (1) (2) (1) pwm2 0 1 ioa2 0 1 ? ioa1 0 0 1 ? ? ioa0 0 1 ? ? ? 7. i/o ports rev.4.00 aug. 20, 2007 page 166 of 638 rej09b0395-0400 pin pin functions and selection method pa 5 /tp 5 / tiocb 1 bit pwm1 in tmdr, bits iob2 to iob0 in tior1, bit nder5 in ndera, and bit pa 5 ddr select the pin function as follows. 16-bit timer channel 1 settings (1) in table below (2) in table below pa 5 ddr ? 0 1 1 nder5 ? ? 0 1 pin function tiocb 1 output pa 5 input pa 5 output tp 5 output tiocb 1 input * note: * tiocb 1 input when iob2 = 1 and pwm1 = 0. 16-bit timer channel 1 settings (2) (1) (2) iob2 0 1 iob1 0 0 1 ? iob0 0 1 ? ? pa 4 /tp 4 / tioca 1 bit pwm1 in tmdr, bits ioa2 to ioa0 in tior1, bit nder4 in ndera, and bit pa 4 ddr select the pin function as follows. 16-bit timer channel 1 settings (1) in table below (2) in table below pa 4 ddr ? 0 1 1 nder4 ? ? 0 1 pin function tioca 1 output pa 4 input pa 4 output tp 4 output tioca 1 input * note: * tioca 1 input when ioa2 = 1. 16-bit timer channel 1 settings (2) (1) (2) (1) pwm1 0 1 ioa2 0 1 ? ioa1 0 0 1 ? ? ioa0 0 1 ? ? ? 7. i/o ports rev.4.00 aug. 20, 2007 page 167 of 638 rej09b0395-0400 table 7.13 port a pin functions (modes 3 and 4) pin pin functions and selection method a 20 always used as a 20 output. pin function a 20 output pa 6 /tp 6 / tioca 2 /a 21 bit pwm2 in tmdr, bits ioa2 to ioa0 in tior2, bit nder6 in ndera, bit a21e in brcr, and bit pa 6 ddr select the pin function as follows. a21e 1 0 16-bit timer channel 2 settings (1) in table below (2) in table below ? pa 6 ddr ? 0 1 1 ? nder6 ? ? 0 1 ? pin function tioca 2 output pa 6 input pa 6 output tp 6 output a 21 output tioca 2 input * note: * tioca 2 input when ioa2 = 1. 16-bit timer channel 2 settings (2) (1) (2) (1) pwm2 0 1 ioa2 0 1 ? ioa1 0 0 1 ? ? ioa0 0 1 ? ? ? 7. i/o ports rev.4.00 aug. 20, 2007 page 168 of 638 rej09b0395-0400 pin pin functions and selection method pa 5 /tp 5 / tiocb 1 /a 22 bit pwm1 in tmdr, bits iob2 to iob0 in tior1, bit nder5 in ndera, bit a22e in brcr, and bit pa 5 ddr select the pin function as follows. a22e 1 0 16-bit timer channel 1 settings (1) in table below (2) in table below ? pa 5 ddr ? 0 1 1 ? nder5 ? ? 0 1 ? pin function tiocb 1 output pa 5 input pa 5 output tp 5 output a 22 output tiocb 1 input * note: * tiocb 1 input when iob2 = 1 and pwm1 = 0. 16-bit timer channel 1 settings (2) (1) (2) iob2 0 1 iob1 0 0 1 ? iob0 0 1 ? ? pa 4 /tp 4 / tioca 1 /a 23 bit pwm1 in tmdr, bits ioa2 to ioa0 in tior1, bit nder4 in ndera, bit a23e in brcr, and bit pa 4 ddr select the pin function as follows. a23e 1 0 16-bit timer channel 1 settings (1) in table below (2) in table below ? pa 4 ddr ? 0 1 1 ? nder4 ? ? 0 1 ? pin function tioca 1 output pa 4 input pa 4 output tp 4 output a 23 output tioca 1 input * note: * tioca 1 input when ioa2 = 1. 16-bit timer channel 1 settings (2) (1) (2) (1) pwm1 0 1 ioa2 0 1 ? ioa1 0 0 1 ? ? ioa0 0 1 ? ? ? 7. i/o ports rev.4.00 aug. 20, 2007 page 169 of 638 rej09b0395-0400 table 7.14 port a pin functions (modes 1 to 4) pin pin functions and selection method pa 3 /tp 3 / tiocb 0 / tclkd bit pwm0 in tmdr, bits iob2 to iob0 in tior0, bits tpsc2 to tpsc0 in 16tcr2 to 16tcr0 of the 16-bit timer, bits cks2 to cks0 in 8tcr2 of the 8-bit timer, bit nder3 in ndera, and bit pa 3 ddr select the pin function as follows. 16-bit timer channel 0 settings (1) in table below (2) in table below pa 3 ddr ? 0 1 1 nder3 ? ? 0 1 pin function tiocb 0 output pa 3 input pa 3 output tp 3 output tiocb 0 input * 1 tclkd input * 2 notes: 1. tiocb 0 input when iob2 = 1 and pwm0 = 0. 2. tclkd input when tpsc2 = tpsc1 = tpsc0 = 1 in any of 16tcr2 to 16tcr0, or bits cks2 to cks0 in 8tcr2 are as shown in (3) in the table below. 16-bit timer channel 0 settings (2) (1) (2) iob2 0 1 iob1 0 0 1 ? iob0 0 1 ? ? 8-bit timer channel 2 settings (4) (3) cks2 0 1 cks1 ? 0 1 cks0 ? 0 1 ? 7. i/o ports rev.4.00 aug. 20, 2007 page 170 of 638 rej09b0395-0400 pin pin functions and selection method pa 2 /tp 2 / tioca 0 / tclkc bit pwm0 in tmdr, bits ioa2 to ioa0 in tior0, bits tpsc2 to tpsc0 in 16tcr2 to 16tcr0 of the 16-bit timer, bits cks2 to cks0 in 8tcr0 of the 8-bit timer, bit nder2 in ndera, and bit pa 2 ddr select the pin function as follows. 16-bit timer channel 0 settings (1) in table below (2) in table below pa 2 ddr ? 0 1 1 nder2 ? ? 0 1 pin function tioca 0 output pa 2 input pa 2 output tp 2 output tioca 0 input * 1 tclkc input * 2 notes: 1. tioca 0 input when ioa2 = 1. 2. tclkc input when tpsc2 = tpsc1 = 1 and tpsc0 = 0 in any of 16tcr2 to 16tcr0, or bits cks2 to cks0 in 8tcr0 are as shown in (3) in the table below. 16-bit timer channel 0 settings (2) (1) (2) (1) pwm0 0 1 ioa2 0 1 ? ioa1 0 0 1 ? ? ioa0 0 1 ? ? ? 8-bit timer channel 0 settings (4) (3) cks2 0 1 cks1 ? 0 1 cks0 ? 0 1 ? 7. i/o ports rev.4.00 aug. 20, 2007 page 171 of 638 rej09b0395-0400 pin pin functions and selection method pa 1 /tp 1 / tclkb bit mdf in tmdr, bits tpsc2 to tpsc0 in 16tcr2 to 16tcr0 of the 16-bit timer, bits cks2 to cks0 in 8tcr3 of the 8-bit timer, bit nder1 in ndera, and bit pa 1 ddr select the pin function as follows. pa 1 ddr 0 1 1 nder1 ? 0 1 pin function pa 1 input pa 1 output tp 1 output tclkb input * note: * tclkb input when mdf = 1 in tmdr, or tpsc2 = 1, tpsc1 = 0, and tpsc0 = 1 in any of 16tcr2 to 16tcr0, or bits cks2 to cks0 in 8tcr3 are as shown in (1) in the table below. 8-bit timer channel 3 settings (2) (1) cks2 0 1 cks1 ? 0 1 cks0 ? 0 1 ? pa 0 /tp 0 / tclka bit mdf in tmdr, bits tpsc2 to tpsc0 in 16tcr2 to 16tcr0 of the 16-bit timer, bits cks2 to cks0 in 8tcr1 of the 8-bit timer, bit nder0 in ndera, and bit pa 0 ddr select the pin function as follows. pa 0 ddr 0 1 nder0 ? 0 1 pin function pa 0 input pa 0 output tp 0 output tclka input * note: * tclka input when mdf = 1 in tmdr, or tpsc2 = 1 and tpsc1 = 0, and tpsc0 = 0 in any of 16tcr2 to 16tcr0, or bits cks2 to cks0 in 8tcr1 are as shown in (1) in the table below. 8-bit timer channel 1 settings (2) (1) cks2 0 1 cks1 ? 0 1 cks0 ? 0 1 ? 7. i/o ports rev.4.00 aug. 20, 2007 page 172 of 638 rej09b0395-0400 7.8 port b 7.8.1 overview port b is an 8-bit input/output port that is also used for output (tp 15 to tp 8 ) from the programmable timing pattern controller (tpc), input/output (tmio 3 , tmo 2 , tmio 1 , tmo 0 ) by the 8-bit timer, and cs 7 to cs 4 output. see table 7.16 for the selection of pin functions. a reset or hardware standby transition leaves port b as an input/output port. for output of cs 7 to cs 4 in modes 1 to 4, see section 6.3.4, chip select signals. pins not assigned to any of these functions are available for generic input/output. figure 7.7 shows the pin configuration of port b. pins in port b can drive one ttl load and a 30-pf capacitive load. they can also drive darlington transistor pair. port b pb 7 /tp 15 pb 6 /tp 14 pb 5 /tp 13 pb 4 /tp 12 pb 3 /tp /tmio 3 / cs 4 11 pb 2 /tp /tmo 2 / cs 5 10 pb 1 /tp /tmio 1 / cs 6 9 pb 0 /tp /tmo 0 / cs 7 8 port b pins pb 7 (input/output)/tp 15 (output) pb 6 (input/output)/tp 14 (output) pb 5 (input/output)/tp 13 (output) pb 4 (input/output)/tp 12 (output) pb 3 (input/output)/tp 11 (output) /tmio 3 (input/output) / cs 4 (output) pb 2 (input/output)/tp 10 (output) /tmo 2 (output) / cs 5 (output) pb 1 (input/output)/tp 9 (output) /tmio 1 (input/output) / cs 6 (output) pb 0 (input/output)/tp 8 (output) /tmo 0 (output) / cs 7 (output) pin fun c tions in modes 1 to 4 figure 7.7 port b pin configuration 7. i/o ports rev.4.00 aug. 20, 2007 page 173 of 638 rej09b0395-0400 7.8.2 register descriptions table 7.15 summarizes the registers of port b. table 7.15 port b registers address * name abbreviation r/w initial value h'ee00a port b data direction register pbddr w h'00 h'fffda port b data register pbdr r/w h'00 note: * lower 20 bits of the address in advanced mode. port b data directio n register (pbddr): pbddr is an 8-bit write-only register that can select input or output for each pin in port b. when pins are used for tpc output, the corresponding pbddr bits must also be set. bit initial value read/write 7 pb ddr 0 w port b data dire c tion 7 to 0 these bits select input or output for port b pins 7 6 pb ddr 0 w 6 5 pb ddr 0 w 5 4 pb ddr 0 w 4 3 pb ddr 0 w 3 2 pb ddr 0 w 2 1 pb ddr 0 w 1 0 pb ddr 0 w 0 for the method of selecting the pin functions, see table 7.16. when port b functions as an input/output port, a pin in port b becomes an output port if the corresponding pbddr bit is set to 1, and an input port if this bit is cleared to 0. pbddr is a write-only register. its value cannot be read. all bits return 1 when read. pbddr is initialized to h'00 by a reset and in ha rdware standby mode. in software standby mode it retains its previous setting. therefore, if a transition is made to software standby mode while port b is functioning as an input/output port and a pbddr bit is set to 1, the corresponding pin maintains its output state. 7. i/o ports rev.4.00 aug. 20, 2007 page 174 of 638 rej09b0395-0400 port b data register (pbdr): pbdr is an 8-bit readable/writable register that stores output data for pins port b. when port b functions as an output port, the value of this register is output. when a bit in pbddr is set to 1, if port b is read the value of the corresponding pbdr bit is returned. when a bit in pbddr is cleared to 0, if port b is read the corresponding pin logic level is read. bit initial value read/write 0 pb 0 r/w 0 1 pb 0 r/w 1 2 pb 0 r/w 2 3 pb 0 r/w 3 4 pb 0 r/w 4 5 pb 0 r/w 5 6 pb 0 r/w 6 7 pb 0 r/w 7 port b data 7 to 0 these bits store data for port b pins pbdr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. 7. i/o ports rev.4.00 aug. 20, 2007 page 175 of 638 rej09b0395-0400 table 7.16 port b pin functions (modes 1 to 4) pin pin functions and selection method pb 7 /tp 15 bit nder15 in nderb and bit pb 7 ddr select the pin function as follows. pb 7 ddr 0 1 1 nder15 ? 0 1 pin function pb 7 input pb 7 output tp 15 output pb 6 /tp 14 bit nder14 in nderb and bit pb 6 ddr select the pin function as follows. pb 6 ddr 0 1 1 nder14 ? 0 1 pin function pb 6 input pb 6 output tp 14 output pb 5 /tp 13 bit nder13 in nderb and bit pb 5 ddr select the pin function as follows. pb 5 ddr 0 1 1 nder13 ? 0 1 pin function pb 5 input pb 5 output tp 13 output pb 4 /tp 12 bit nder12 in nderb and bit pb 4 ddr select the pin function as follows. pb 4 ddr 0 1 1 nder12 ? 0 1 pin function pb 4 input pb 4 output tp 12 output pb 3 /tp 11 / tmio 3 / cs 4 bits ois3/2 and os1/0 in 8tcsr3, bits cclr1/0 in 8tcr3, bit cs4e in cscr, bit nder11 in nderb, and bit pb 3 ddr select the pin function as follows. ois3/2 and os1/0 all 0 not all 0 cs4e 0 1 ? pb 3 ddr 0 1 1 ? ? nder11 ? 0 1 ? ? pin function pb 3 input pb 3 output tp 11 output cs 4 output tmio 3 output tmio 3 input * note: * tmio 3 input when bit ice = 1 in 8tcsr3. 7. i/o ports rev.4.00 aug. 20, 2007 page 176 of 638 rej09b0395-0400 pin pin functions and selection method pb 2 /tp 10 / tmo 2 / cs 5 bits ois3/2 and os1/0 in 8tcsr2, bit cs5e in cscr, bit nder10 in nderb, and bit pb 2 ddr select the pin function as follows. ois3/2 and os1/0 all 0 not all 0 cs5e 0 1 ? pb 2 ddr 0 1 1 ? ? nder10 ? 0 1 ? ? pin function pb 2 input pb 2 output tp 10 output cs 5 output tmio 2 output pb 1 /tp 9 / tmio 1 / cs 6 bits ois3/2 and os1/0 in 8tcsr1, bits cclr1/0 in 8tcr1, bit cs6e in cscr, bit nder9 in nderb, and bit pb 1 ddr select the pin function as follows. ois3/2 and os1/0 all 0 not all 0 cs6e 0 1 ? pb 1 ddr 0 1 1 ? ? nder9 ? 0 1 ? ? pin function pb 1 input pb 1 output tp 9 output cs 6 output tmio 1 output tmio 1 input * note: * tmio 1 input when bit ice = 1 in 8tcsr1. pb 0 /tp 8 / tmo 0 / cs 7 bits ois3/2 and os1/0 in 8tcsr0, bit cs7e in cscr, bit nder8 in nderb, and bit pb 0 ddr select the pin function as follows. ois3/2 and os1/0 all 0 not all 0 cs7e 0 1 ? pb 0 ddr 0 1 1 ? ? nder8 ? 0 1 ? ? pin function pb 0 input pb 0 output tp 8 output cs 7 output tmo 0 output 8. 16-bit timer rev.4.00 aug. 20, 2007 page 177 of 638 rej09b0395-0400 section 8 16-bit timer 8.1 overview the h8/3008 has built-in 16-bit timer modul e with three 16-bit counter channels. 8.1.1 features 16-bit timer features are listed below. ? capability to process up to 6 pulse outputs or 6 pulse inputs ? six general registers (grs, two per channel) with independently-assignable output compare or input capture functions ? selection of eight counter clock sources for each channel: internal clocks: , /2, /4, /8 external clocks: tclka, tclkb, tclkc, tclkd ? five operating modes selectable in all channels: ? waveform output by compare match selection of 0 output, 1 output, or toggle output (only 0 or 1 output in channel 2) ? input capture function rising edge, falling edge, or both edges (selectable) ? counter clearing function counters can be cleared by compare match or input capture ? synchronization two or more timer counters (16tcnts) can be preset simultaneously, or cleared simultaneously by compare match or input capture. counter synchronization enables synchronous register input and output. ? pwm mode pwm output can be provided with an arbitrary duty cycle. with synchronization, up to three-phase pwm output is possible ? phase counting mode selectable in channel 2 two-phase encoder output can be counted automatically. ? high-speed access via internal 16-bit bus the 16tcnts and grs can be accessed at high speed via a 16-bit bus. ? any initial timer output value can be set ? nine interrupt sources 8. 16-bit timer rev.4.00 aug. 20, 2007 page 178 of 638 rej09b0395-0400 each channel has two compare match/input capture interrupts and an overflow interrupt. all interrupts can be requested independently. ? output triggering of programmable timing pattern controller (tpc) compare match/input capture signals from channels 0 to 2 can be used as tpc output triggers. table 8.1 summarizes the 16-bit timer functions. table 8.1 16-bit timer functions item channel 0 channel 1 channel 2 clock sources internal clocks: , /2, /4, /8 external clocks: tclka, tclkb, tclkc, tclkd, selectable independently general registers (output compare/input capture registers) gra0, grb0 gra1, grb1 gra2, grb2 input/output pins tioca 0 , tiocb 0 tioca 1 , tiocb 1 tioca 2 , tiocb 2 counter clearing function gra0/grb0 compare match or input capture gra1/grb1 compare match or input capture gra2/grb2 compare match or input capture initial output value setting function available available available 0 available available available compare match output 1 available available available toggle available available not available input capture function available available available synchronization available available available pwm mode available available available phase counting mode not available not available available interrupt sources three sources ? compare match/input capture a0 ? compare match/input capture b0 ? overflow three sources ? compare match/input capture a1 ? compare match/input capture b1 ? overflow three sources ? compare match/input capture a2 ? compare match/input capture b2 ? overflow 8. 16-bit timer rev.4.00 aug. 20, 2007 page 179 of 638 rej09b0395-0400 8.1.2 block diagrams 16-bit timer block diagram (overall): figure 8.1 is a block diagram of the 16-bit timer. 16-bit timer channel 2 16-bit timer channel 1 16-bit timer channel 0 module data bus bus interface internal data bus imia0 to imia2 imib0 to imib2 ovi0 to ovi2 tclka to tclkd , /2, /4, /8 clock selector control lo g ic tioca 0 to tioca 2 tiocb 0 to tiocb 2 tstr tsnr tmdr tolr tisra tisrb tisrc le g end: tstr: timer start re g ister (8 bits) tsnr: timer synchro re g ister (8 bits) tmdr: timer mode re g ister (8 bits) tolr: timer output level settin g re g ister (8 bits) tisra: timer interrupt status re g ister a (8 bits) tisrb: timer interrupt status re g ister b (8 bits) tisrc: timer interrupt status re g ister c (8 bits) figure 8.1 16-bit timer block diagram (overall) 8. 16-bit timer rev.4.00 aug. 20, 2007 page 180 of 638 rej09b0395-0400 block diagram of channels 0 and 1: 16-bit timer channels 0 and 1 are functionally identical. both have the structure shown in figure 8.2. clock selector comparator control lo g ic tclka to tclkd , /2, /4, /8 tioca 0 tiocb 0 imia0 imib0 ovi0 16tcnt gra grb 16tcr tior module data bus le g end: 16tcnt: gra, grb: 16tcr: tior: timer counter (16 bits) general re g isters a and b (input capture/output compare re g isters) (16 bits 2) timer control re g ister (8 bits) timer i/o control re g ister (8 bits) figure 8.2 block diagram of channels 0 and 1 8. 16-bit timer rev.4.00 aug. 20, 2007 page 181 of 638 rej09b0395-0400 block diagram of channel 2: figure 8.3 is a block diagram of channel 2 clock selector comparator control lo g ic tclka to tclkd , /2, /4, /8 tioca 2 tiocb 2 imia2 imib2 ovi2 16tcnt2 gra2 grb2 16tcr2 tior2 module data bus le g end: 16tcnt2: gra2, grb2: 16tcr2: tior2: timer counter 2 (16 bits) general re g isters a2 and b2 (input capture/output compare re g isters) (16 bits 2) timer control re g ister 2 (8 bits) timer i/o control re g ister 2 (8 bits) figure 8.3 block diagram of channel 2 8. 16-bit timer rev.4.00 aug. 20, 2007 page 182 of 638 rej09b0395-0400 8.1.3 pin configuration table 8.2 summarizes the 16-bit timer pins. table 8.2 16-bit timer pins channel name abbre- viation input/ output function common clock input a tclka input external clock a input pin (phase-a input pin in phase counting mode) clock input b tclkb input external clock b input pin (phase-b input pin in phase counting mode) clock input c tclkc input external clock c input pin clock input d tclkd input external clock d input pin 0 input capture/output compare a0 tioca 0 input/ output gra0 output compare or input capture pin pwm output pin in pwm mode input capture/output compare b0 tiocb 0 input/ output grb0 output compare or input capture pin 1 input capture/output compare a1 tioca 1 input/ output gra1 output compare or input capture pin pwm output pin in pwm mode input capture/output compare b1 tiocb 1 input/ output grb1 output compare or input capture pin 2 input capture/output compare a2 tioca 2 input/ output gra2 output compare or input capture pin pwm output pin in pwm mode input capture/output compare b2 tiocb 2 input/ output grb2 output compare or input capture pin 8. 16-bit timer rev.4.00 aug. 20, 2007 page 183 of 638 rej09b0395-0400 8.1.4 register configuration table 8.3 summarizes the 16-bit timer registers. table 8.3 16-bit timer registers channel address * 1 name abbre- viation r/w initial value common h'fff60 timer start register tstr r/w h'f8 h'fff61 timer synchro register tsnc r/w h'f8 h'fff62 timer mode register tmdr r/w h'98 h'fff63 timer output level setting register tolr w h'c0 h'fff64 timer interrupt status register a tisra r/(w) * 2 h'88 h'fff65 timer interrupt status register b tisrb r/(w) * 2 h'88 h'fff66 timer interrupt status register c tisrc r/(w) * 2 h'88 0 h'fff68 timer control register 0 16tcr0 r/w h'80 h'fff69 timer i/o control register 0 tior0 r/w h'88 h'fff6a timer counter 0h 16tcnt0h r/w h'00 h'fff6b timer counter 0l 16tcnt0l r/w h'00 h'fff6c general register a0h gra0h r/w h'ff h'fff6d general register a0l gra0l r/w h'ff h'fff6e general register b0h grb0h r/w h'ff h'fff6f general register b0l grb0l r/w h'ff 1 h'fff70 timer control register 1 16tcr1 r/w h'80 h'fff71 timer i/o control register 1 tior1 r/w h'88 h'fff72 timer counter 1h 16tcnt1h r/w h'00 h'fff73 timer counter 1l 16tcnt1l r/w h'00 h'fff74 general register a1h gra1h r/w h'ff h'fff75 general register a1l gra1l r/w h'ff h'fff76 general register b1h grb1h r/w h'ff h'fff77 general register b1l grb1l r/w h'ff 8. 16-bit timer rev.4.00 aug. 20, 2007 page 184 of 638 rej09b0395-0400 channel address * 1 name abbre- viation r/w initial value 2 h'fff78 timer control register 2 16tcr2 r/w h'80 h'fff79 timer i/o control register 2 tior2 r/w h'88 h'fff7a timer counter 2h 16tcnt2h r/w h'00 h'fff7b timer counter 2l 16tcnt2l r/w h'00 h'fff7c general register a2h gra2h r/w h'ff h'fff7d general register a2l gra2l r/w h'ff h'fff7e general register b2h grb2h r/w h'ff h'fff7f general register b2l grb2l r/w h'ff notes: 1. the lower 20 bits of the address in advanced mode are indicated. 2. only 0 can be written in bits 3 to 0, to clear the flags. 8.2 register descriptions 8.2.1 timer start register (tstr) tstr is an 8-bit readable/writabl e register that starts and stop s the timer counter (16tcnt) in channels 0 to 2. bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 2 str2 0 r/w 1 str1 0 r/w 0 str0 0 r/w reserved bits counter start 2 to 0 these bits start and stop 16tcnt2 to 16tcnt0 tstr is initialized to h'f8 by a reset and in standby mode. bits 7 to 3?reserved: these bits cannot be modified and are always read as 1. 8. 16-bit timer rev.4.00 aug. 20, 2007 page 185 of 638 rej09b0395-0400 bit 2?counter start 2 (str2): starts and stops timer counter 2 (16tcnt2). bit 2 str2 description 0 16tcnt2 is halted (initial value) 1 16tcnt2 is counting bit 1?counter start 1 (str1): starts and stops timer counter 1 (16tcnt1). bit 1 str1 description 0 16tcnt1 is halted (initial value) 1 16tcnt1 is counting bit 0?counter start 0 (str0): starts and stops timer counter 0 (16tcnt0). bit 0 str0 description 0 16tcnt0 is halted (initial value) 1 16tcnt0 is counting 8.2.2 timer synchro register (tsnc) tsnc is an 8-bit readable/writable register that selects whether channels 0 to 2 operate independently or synchronously. channels are synchronized by setting the corresponding bits to 1. bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 2 sync2 0 r/w 1 sync1 0 r/w 0 sync0 0 r/w reserved bits timer syn c 2 to 0 these bits synchronize channels 2 to 0 tsnc is initialized to h'f8 by a reset and in standby mode. bits 7 to 3?reserved: these bits cannot be modified and are always read as 1. 8. 16-bit timer rev.4.00 aug. 20, 2007 page 186 of 638 rej09b0395-0400 bit 2?timer sync 2 (sync2): selects whether channel 2 operates independently or synchronously. bit 2 sync2 description 0 channel 2's timer counter (16tcnt2) operates independently (initial value) 16tcnt2 is preset and cleared independently of other channels 1 channel 2 operates synchronously 16tcnt2 can be synchronously preset and cleared bit 1?timer sync 1 (sync1): selects whether channel 1 operates independently or synchronously. bit 1 sync1 description 0 channel 1's timer counter (16tcnt1) operates independently (initial value) 16tcnt1 is preset and cleared independently of other channels 1 channel 1 operates synchronously 16tcnt1 can be synchronously preset and cleared bit 0?timer sync 0 (sync0): selects whether channel 0 operates independently or synchronously. bit 0 sync0 description 0 channel 0's timer counter (16tcnt0) operates independently (initial value) 16tcnt0 is preset and cleared independently of other channels 1 channel 0 operates synchronously 16tcnt0 can be synchronously preset and cleared 8. 16-bit timer rev.4.00 aug. 20, 2007 page 187 of 638 rej09b0395-0400 8.2.3 timer mode register (tmdr) tmdr is an 8-bit readable/writable register that selects pwm mode for channels 0 to 2. it also selects phase counting mode and the overflow flag (ovf) setting conditions for channel 2. bit initial value read/write 7 ? 1 ? 6 mdf 0 r/w 5 fdir 0 r/w 4 ? 1 ? 3 ? 1 ? 0 pwm0 0 r/w 2 pwm2 0 r/w 1 pwm1 0 r/w reserved bit reserved bit pwm mode 2 to 0 these bits select pwm mode for channels 2 to 0 phase c ounting mode flag selects phase countin g mode for channel 2 flag dire c tion selects the settin g condition for the overflow fla g (ovf) in tisrc tmdr is initialized to h'98 by a reset and in standby mode. bit 7?reserved: this bit cannot be modified and is always read as 1. bit 6?phase counting mode flag (mdf): selects whether channel 2 operates normally or in phase counting mode. bit 6 mdf description 0 channel 2 operates normally (initial value) 1 channel 2 operates in phase counting mode when mdf is set to 1 to select phase counting mode, 16tcnt2 operates as an up/down-counter and pins tclka and tclkb become counter clock input pins. 16tcnt2 counts both rising and falling edges of tclka and tclkb, and counts up or down as follows. 8. 16-bit timer rev.4.00 aug. 20, 2007 page 188 of 638 rej09b0395-0400 counting direction down-counting up-counting tclka pin high low low high tclkb pin low high high low in phase counting mode, external clock edge selection by bits ckeg1 and ckeg0 in 16tcr2 and counter clock selection by bits tpsc2 to tpsc0 are invalid, and the above phase counting mode operations take precedence. the counter clearing condition selected by th e cclr1 and cclr0 bits in 16tcr2 and the compare match/input capture setti ngs and interrupt functions of tior2, tisra, tisrb, tisrc remain effective in phase counting mode. bit 5?flag direction (fdir): designates the setting condition for the ovf flag in tisrc. the fdir designation is valid in all modes in channel 2. bit 5 fdir description 0 ovf is set to 1 in tisrc when 16tcnt2 overflows or underflows (initial value) 1 ovf is set to 1 in tisrc when 16tcnt2 overflows bits 4 and 3?reserved: these bits cannot be modified and are always read as 1. bit 2?pwm mode 2 (pwm2): selects whether channel 2 operates normally or in pwm mode. bit 2 pwm2 description 0 channel 2 operates normally (initial value) 1 channel 2 operates in pwm mode when bit pwm2 is set to 1 to select pwm mode, pin tioca 2 becomes a pwm output pin. the output goes to 1 at compare match with gra2, and to 0 at compare match with grb2. bit 1?pwm mode 1 (pwm1): selects whether channel 1 operates normally or in pwm mode. bit 1 pwm1 description 0 channel 1 operates normally (initial value) 1 channel 1 operates in pwm mode 8. 16-bit timer rev.4.00 aug. 20, 2007 page 189 of 638 rej09b0395-0400 when bit pwm1 is set to 1 to select pwm mode, pin tioca 1 becomes a pwm output pin. the output goes to 1 at compare match with gra1, and to 0 at compare match with grb1. bit 0?pwm mode 0 (pwm0): selects whether channel 0 operates normally or in pwm mode. bit 0 pwm0 description 0 channel 0 operates normally (initial value) 1 channel 0 operates in pwm mode when bit pwm0 is set to 1 to select pwm mode, pin tioca 0 becomes a pwm output pin. the output goes to 1 at compare match with gra0, and to 0 at compare match with grb0. 8.2.4 timer interrupt status register a (tisra) tisra is an 8-bit readable/writable register th at indicates gra compare match or input capture and enables or disables gra compare match and input capture interrupt requests. 7 ? 1 ? bit initial value read/write 6 imiea2 0 r/w 5 imiea1 0 r/w 4 imiea0 0 r/w 3 ? 1 ? 2 imfa2 0 r/(w) * 1 imfa1 0 r/(w) * 0 imfa0 0 r/(w) * reserved bit reserved bit input c apture/ c ompare mat c h interrupt enable a2 to a0 these bits enable or disable interrupts by the imfa fla g s input c apture/ c ompare mat c h flags a2 to a0 status fla g s indicatin g gra compare match or input capture note: * only 0 can be written, to clear the fla g . tisra is initialized to h'88 by a reset and in standby mode. bit 7?reserved: this bit cannot be modified and is always read as 1. 8. 16-bit timer rev.4.00 aug. 20, 2007 page 190 of 638 rej09b0395-0400 bit 6?input capture/compare match interrupt enable a2 (imiea2): enables or disables the interrupt requested by the imfa2 when imfa2 flag is set to 1. bit 6 imiea2 description 0 imia2 interrupt requested by imfa2 flag is disabled (initial value) 1 imia2 interrupt requested by imfa2 flag is enabled bit 5?input capture/compare match interrupt enable a1 (imiea1): enables or disables the interrupt requested by the imfa1 flag when imfa1 is set to 1. bit 5 imiea1 description 0 imia1 interrupt requested by imfa1 flag is disabled (initial value) 1 imia1 interrupt requested by imfa1 flag is enabled bit 4?input capture/compare match interrupt enable a0 (imiea0): enables or disables the interrupt requested by the imfa0 flag when imfa0 is set to 1. bit 4 imiea0 description 0 imia0 interrupt requested by imfa0 flag is disabled (initial value) 1 imia0 interrupt requested by imfa0 flag is enabled bit 3?reserved: this bit cannot be modified and is always read as 1. bit 2?input capture/compare match flag a2 (imfa2): this status flag indicates gra2 compare match or input capture events. bit 2 imfa2 description 0 [clearing condition] (initial value) read imfa2 flag when imfa2 = 1, then write 0 in imfa2 flag 1 [setting conditions] ? 16tcnt2 = gra2 when gra2 functions as an output compare register ? 16tcnt2 value is transferred to gra2 by an input capture signal when gra2 functions as an input capture register 8. 16-bit timer rev.4.00 aug. 20, 2007 page 191 of 638 rej09b0395-0400 bit 1?input capture/compare match flag a1 (imfa1): this status flag indicates gra1 compare match or input capture events. bit 1 imfa1 description 0 [clearing condition] (initial value) read imfa1 flag when imfa1 = 1, then write 0 in imfa1 flag 1 [setting conditions] ? 16tcnt1 = gra1 when gra1 functions as an output compare register ? 16tcnt1 value is transferred to gra1 by an input capture signal when gra1 functions as an input capture register bit 0?input capture/compare match flag a0 (imfa0): this status flag indicates gra0 compare match or input capture events. bit 0 imfa0 description 0 [clearing condition] (initial value) read imfa0 flag when imfa0 = 1, then write 0 in imfa0 flag 1 [setting conditions] ? 16tcnt0 = gra0 when gra0 functions as an output compare register ? 16tcnt0 value is transferred to gra0 by an input capture signal when gra0 functions as an input capture register 8. 16-bit timer rev.4.00 aug. 20, 2007 page 192 of 638 rej09b0395-0400 8.2.5 timer interrupt status register b (tisrb) tisrb is an 8-bit readable/writable register that indicates grb compare match or input capture and enables or disables grb compare match and input capture interrupt requests. 7 ? 1 ? bit initial value read/write 6 imieb2 0 r/w 5 imieb1 0 r/w 4 imieb0 0 r/w 3 ? 1 ? 2 imfb2 0 r/(w) * 1 imfb1 0 r/(w) * 0 imfb0 0 r/(w) * reserved bit reserved bit input c apture/ c ompare mat c h interrupt enable b2 to b0 these bits enable or disable interrupts by the imfb fla g s input c apture/ c ompare mat c h flags b2 to b0 status fla g s indicatin g grb compare match or input capture note: * only 0 can be written, to clear the fla g . tisrb is initialized to h'88 by a reset and in standby mode. bit 7?reserved: this bit cannot be modified and is always read as 1. bit 6?input capture/compare match interrupt enable b2 (imieb2): enables or disables the interrupt requested by the imfb2 when imfb2 flag is set to 1. bit 6 imieb2 description 0 imib2 interrupt requested by imfb2 flag is disabled (initial value) 1 imib2 interrupt requested by imfb2 flag is enabled 8. 16-bit timer rev.4.00 aug. 20, 2007 page 193 of 638 rej09b0395-0400 bit 5?input capture/compare match interrupt enable b1 (imieb1): enables or disables the interrupt requested by the imfb1 when imfb1 flag is set to 1. bit 5 imieb1 description 0 imib1 interrupt requested by imfb1 flag is disabled (initial value) 1 imib1 interrupt requested by imfb1 flag is enabled bit 4?input capture/compare match interrupt enable b0 (imieb0): enables or disables the interrupt requested by the imfb0 when imfb0 flag is set to 1. bit 4 imieb0 description 0 imib0 interrupt requested by imfb0 flag is disabled (initial value) 1 imib0 interrupt requested by imfb0 flag is enabled bit 3?reserved: this bit cannot be modified and is always read as 1. bit 2?input capture/compare match flag b2 (imfb2): this status flag indicates grb2 compare match or input capture events. bit 2 imfb2 description 0 [clearing condition] (initial value) read imfb2 flag when imfb2 = 1, then write 0 in imfb2 flag 1 [setting conditions] ? 16tcnt2 = grb2 when grb2 functions as an output compare register ? 16tcnt2 value is transferred to grb2 by an input capture signal when grb2 functions as an input capture register 8. 16-bit timer rev.4.00 aug. 20, 2007 page 194 of 638 rej09b0395-0400 bit 1?input capture/compare match flag b1 (imfb1): this status flag indicates grb1 compare match or input capture events. bit 1 imfb1 description 0 [clearing condition] (initial value) read imfb1 flag when imfb1 = 1, then write 0 in imfb1 flag 1 [setting conditions] ? 16tcnt1 = grb1 when grb1 functions as an output compare register ? 16tcnt1 value is transferred to grb1 by an input capture signal when grb1 functions as an input capture register bit 0?input capture/compare match flag b0 (imfb0): this status flag indicates grb0 compare match or input capture events. bit 0 imfb0 description 0 [clearing condition] (initial value) read imfb0 flag when imfb0 = 1, then write 0 in imfb0 flag 1 [setting conditions] ? 16tcnt0 = grb0 when grb0 functions as an output compare register ? 16tcnt0 value is transferred to grb0 by an input capture signal when grb0 functions as an input capture register 8. 16-bit timer rev.4.00 aug. 20, 2007 page 195 of 638 rej09b0395-0400 8.2.6 timer interrupt status register c (tisrc) tisrc is an 8-bit readable/writable register that indicates 16tcnt overflow or underflow and enables or disables overflow interrupt requests. 7 ? 1 ? bit initial value read/write 6 ovie2 0 r/w 5 ovie1 0 r/w 4 ovie0 0 r/w 3 ? 1 ? 2 ovf2 0 r/(w) * 1 ovf1 0 r/(w) * 0 ovf0 0 r/(w) * reserved bit reserved bit overflow interrupt enable 2 to 0 these bits enable or disable interrupts by the ovf fla g s overflow flags 2 to 0 status fla g s indicatin g interrupts by ovf fla g s note: * only 0 can be written, to clear the fla g . tisrc is initialized to h'88 by a reset and in standby mode. bit 7?reserved: this bit cannot be modified and is always read as 1. bit 6?overflow interrupt enable 2 (ovie2): enables or disables the interrupt requested by the ovf2 when ovf2 flag is set to 1. bit 6 ovie2 description 0 ovi2 interrupt requested by ovf2 flag is disabled (initial value) 1 ovi2 interrupt requested by ovf2 flag is enabled 8. 16-bit timer rev.4.00 aug. 20, 2007 page 196 of 638 rej09b0395-0400 bit 5?overflow interrupt enable 1 (ovie1): enables or disables the interrupt requested by the ovf1 when ovf1 flag is set to 1. bit 5 ovie1 description 0 ovi1 interrupt requested by ovf1 flag is disabled (initial value) 1 ovi1 interrupt requested by ovf1 flag is enabled bit 4?overflow interrupt enable 0 (ovie0): enables or disables the interrupt requested by the ovf0 when ovf0 flag is set to 1. bit 4 ovie0 description 0 ovi0 interrupt requested by ovf0 flag is disabled (initial value) 1 ovi0 interrupt requested by ovf0 flag is enabled bit 3?reserved: this bit cannot be modified and is always read as 1. bit 2?overflow flag 2 (ovf2): this status flag indicates 16tcnt2 overflow. bit 2 ovf2 description 0 [clearing condition] (initial value) read ovf2 flag when ovf2 = 1, then write 0 in ovf2 flag 1 [setting condition] 16tcnt2 overflowed from h'ffff to h'0000, or underflowed from h'0000 to h'ffff note: 16tcnt underflow occurs when 16tcnt operates as an up/down-counter. underflow occurs only when channel 2 operates in phase counting mode (mdf = 1 in tmdr). bit 1?overflow flag 1 (ovf1): this status flag indicates 16tcnt1 overflow. bit 1 ovf1 description 0 [clearing condition] (initial value) read ovf1 flag when ovf1 = 1, then write 0 in ovf1 flag 1 [setting condition] 16tcnt1 overflowed from h'ffff to h'0000 8. 16-bit timer rev.4.00 aug. 20, 2007 page 197 of 638 rej09b0395-0400 bit 0?overflow flag 0 (ovf0): this status flag indicates 16tcnt0 overflow. bit 0 ovf0 description 0 [clearing condition] (initial value) read ovf0 flag when ovf0 = 1, then write 0 in ovf0 flag 1 [setting condition] 16tcnt0 overflowed from h'ffff to h'0000 8.2.7 timer counters (16tcnt) 16tcnt is a 16-bit counter. the 16-bit timer has three 16tcnts, one for each channel. channel abbreviation function 0 16tcnt0 up-counter 1 16tcnt1 2 16tcnt2 phase counting mode: up/down-counter other modes: up-counter bit initial value read/write 14 0 r/w 12 0 r/w 10 0 r/w 8 0 r/w 6 0 r/w 0 0 r/w 4 0 r/w 2 0 r/w 15 0 r/w 13 0 r/w 11 0 r/w 9 0 r/w 7 0 r/w 1 0 r/w 5 0 r/w 3 0 r/w each 16tcnt is a 16-bit readable/writable register that counts pulse inputs from a clock source. the clock source is selected by bits tpsc2 to tpsc0 in 16tcr. 16tcnt0 and 16tcnt1 are up-counters. 16tcnt2 is an up/down-counter in phase counting mode and an up-counter in other modes. 16tcnt can be cleared to h'0000 by compare match with gra or grb or by input capture to gra or grb (counter clearing function). when 16tcnt overflows (changes fr om h'ffff to h'0000), the ovf flag is set to 1 in tisrc of the corresponding channel. when 16tcnt underflows (changes from h'0000 to h'ffff), the ovf flag is set to 1 in tisrc of the corresponding channel. 8. 16-bit timer rev.4.00 aug. 20, 2007 page 198 of 638 rej09b0395-0400 the 16tcnts are linked to the cpu by an internal 16-bit bus and can be written or read by either word access or byte access. each 16tcnt is initialized to h'0000 by a reset and in standby mode. 8.2.8 general registers (gra, grb) the general registers are 16-bit registers. the 16-bit timer has 6 general registers, two in each channel. channel abbreviation function 0 gra0, grb0 output compare/input capture register 1 gra1, grb1 2 gra2, grb2 bit initial value read/write 14 1 r/w 12 1 r/w 10 1 r/w 8 1 r/w 6 1 r/w 0 1 r/w 4 1 r/w 2 1 r/w 15 1 r/w 13 1 r/w 11 1 r/w 9 1 r/w 7 1 r/w 1 1 r/w 5 1 r/w 3 1 r/w a general register is a 16-bit readable/writable register that can function as either an output compare register or an input capture register. the function is selected by settings in tior. when a general register is used as an output co mpare register, its value is constantly compared with the 16tcnt value. when the two values match (compare match), the imfa or imfb flag is set to 1 in tisra/tisrb. compare match output can be selected in tior. when a general register is used as an input captu re register, an external input capture signal are detected and the current 16tcnt value is stored in the general register. the corresponding imfa or imfb flag in tisra/tisrb is set to 1 at the same time. the edges of the input capture signal are selected in tior. tior settings are ignored in pwm mode. general registers are linked to the cpu by an internal 16-bit bus and can be written or read by either word access or byte access. general registers are set as output compare registers (with no pin output) and initialized to h'ffff by a reset and in standby mode. 8. 16-bit timer rev.4.00 aug. 20, 2007 page 199 of 638 rej09b0395-0400 8.2.9 timer control registers (16tcr) 16tcr is an 8-bit register. the 16-bit timer has three 16tcrs, one in each channel. channel abbreviation function 0 16tcr0 1 16tcr1 2 16tcr2 16tcr controls the timer counter. the 16tcrs in all channels are functionally identical. when phase counting mode is selected in channel 2, the settings of bits ckeg1 and ckeg0 and tpsc2 to tpsc0 in 16tcr2 are ignored bit initial value read/write 7 ? 1 ? 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w timer pres c aler 2 to 0 these bits select the timer counter clock reserved bit clo c k edge 1/0 these bits select external clock ed g es counter c lear 1/0 these bits select the counter clear source each 16tcr is an 8-bit readable/writable register that selects the timer counter clock source, selects the edge or edges of external clock sources, and selects how the counter is cleared. 16tcr is initialized to h'80 by a reset and in standby mode. bit 7?reserved: this bit cannot be modified and is always read as 1. 8. 16-bit timer rev.4.00 aug. 20, 2007 page 200 of 638 rej09b0395-0400 bits 6 and 5?counter clear 1 and 0 (cclr1, cclr0): these bits select how 16tcnt is cleared. bit 6 cclr1 bit 5 cclr0 description 0 0 16tcnt is not cleared (initial value) 1 16tcnt is cleared by gra compare match or input capture * 1 1 0 16tcnt is cleared by grb compare match or input capture * 1 1 synchronous clear: 16tcnt is cleared in synchronization with other synchronized timers * 2 notes: 1. 16tcnt is cleared by compare match when the general register functions as an output compare register, and by input capture when th e general register functions as an input capture register. 2. selected in tsnc. bits 4 and 3?clock edge 1 and 0 (ckeg1, ckeg0): these bits select external clock input edges when an external clock source is used. bit 4 ckeg1 bit 3 ckeg0 description 0 0 count rising edges (initial value) 1 count falling edges 1 ? count both edges when channel 2 is set to phase counting mode, bits ckeg1 and ckeg0 in 16tcr2 are ignored. phase counting takes precedence. 8. 16-bit timer rev.4.00 aug. 20, 2007 page 201 of 638 rej09b0395-0400 bits 2 to 0?timer prescaler 2 to 0 (tpsc2 to tpsc0): these bits select the counter clock source. bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 function 0 0 0 internal clock: (initial value) 1 internal clock: /2 1 0 internal clock: /4 1 internal clock: /8 1 0 0 external clock a: tclka input 1 external clock b: tclkb input 1 0 external clock c: tclkc input 1 external clock d: tclkd input when bit tpsc2 is cleared to 0 an internal clock source is sel ected, and the timer counts only falling edges. when bit tpsc2 is set to 1 an external clock source is selected, and the timer counts the edges selected by bits ckeg1 and ckeg0. when channel 2 is set to phase counting mode (mdf = 1 in tmdr), the settings of bits tpsc2 to tpsc0 in 16tcr2 are ignored. phase counting takes precedence. 8. 16-bit timer rev.4.00 aug. 20, 2007 page 202 of 638 rej09b0395-0400 8.2.10 timer i/o control register (tior) tior is an 8-bit register. the 16-bit timer has three ti ors, one in each channel. channel abbreviation function 0 tior0 1 tior1 tior controls the general registers. some functions differ in pwm mode. 2 tior2 bit initial value read/write 7 ? 1 ? 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ? 1 ? 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w i/o c ontrol a2 to a0 these bits select gra functions reserved bit i/o c ontrol b2 to b0 these bits select grb functions reserved bit each tior is an 8-bit readable/writable register that selects the output compare or input capture function for gra and grb, and specifies the functions of the tiora and tiorb pins. if the output compare function is selected, tior also selects the type of output. if input capture is selected, tior also selects the edges of the input capture signal. tior is initialized to h'88 by a reset and in standby mode. bit 7?reserved: this bit cannot be modified and is always read as 1. 8. 16-bit timer rev.4.00 aug. 20, 2007 page 203 of 638 rej09b0395-0400 bits 6 to 4?i/o control b2 to b0 (iob2 to iob0): these bits select the grb function. bit 6 iob2 bit 5 iob1 bit 4 iob0 function 0 0 0 no output at compare match (initial value) 1 grb is an output compare register 0 output at grb compare match * 1 1 0 1 output at grb compare match * 1 1 output toggles at grb compare match (1 output in channel 2) * 1, * 2 1 0 0 grb captures rising edge of input 1 grb captures falling edge of input 1 0 grb is an input capture register grb captures both edges of input 1 notes: 1. after a reset, the output conforms to the tolr setting until the first compare match. 2. channel 2 output cannot be toggled by compare match. when this setting is made, 1 output is selected automatically. bit 3?reserved: this bit cannot be modified and is always read as 1. bits 2 to 0?i/o control a2 to a0 (ioa2 to ioa0): these bits select the gra function. bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 function 0 0 0 no output at compare match (initial value) 1 0 output at gra compare match * 1 1 0 gra is an output compare register 1 output at gra compare match * 1 1 output toggles at gra compare match (1 output in channel 2) * 1, * 2 1 0 0 gra captures rising edge of input 1 gra is an input capture register gra captures falling edge of input 1 0 gra captures both edges of input 1 notes: 1. after a reset, the output conforms to the tolr setting until the first compare match. 2. channel 2 output cannot be toggled by compare match. when this setting is made, 1 output is selected automatically. 8. 16-bit timer rev.4.00 aug. 20, 2007 page 204 of 638 rej09b0395-0400 8.2.11 timer output level setting register c (tolr) tolr is an 8-bit write-only register that selects the timer output level for channels 0 to 2. 7 ? 1 ? bit initial value read/write 6 ? 1 ? 5 tob2 0 w 4 toa2 0 w 3 tob1 0 w 2 toa1 0 w 1 tob0 0 w 0 toa0 0 w reserved bits output level setting a2 to a0, b2 to b0 these bits set the levels of the timer outputs (tioca 2 to tioca 0 , and tiocb 2 to tiocb 0 ) a tolr setting can only be made when the corresponding bit in tstr is 0. tolr is a write-only register, and cannot be read. if it is read, all bits will return a value of 1. tolr is initialized to h'c0 by a reset and in standby mode. bits 7 and 6?reserved: these bits cannot be modified. bit 5?output level setting b2 (tob2): sets the value of timer output tiocb 2 . bit 5 tob2 description 0 tiocb 2 is 0 (initial value) 1 tiocb 2 is 1 bit 4?output level setting a2 (toa2): sets the value of timer output tioca 2 . bit 4 toa2 description 0 tioca 2 is 0 (initial value) 1 tioca 2 is 1 8. 16-bit timer rev.4.00 aug. 20, 2007 page 205 of 638 rej09b0395-0400 bit 3?output level setting b1 (tob1): sets the value of timer output tiocb 1 . bit 3 tob1 description 0 tiocb 1 is 0 (initial value) 1 tiocb 1 is 1 bit 2?output level setting a1 (toa1): sets the value of timer output tioca 1 . bit 2 toa1 description 0 tioca 1 is 0 (initial value) 1 tioca 1 is 1 bit 1?output level setting b0 (tob0): sets the value of timer output tiocb 0 . bit 0 tob0 description 0 tiocb 0 is 0 (initial value) 1 tiocb 0 is 1 bit 0?output level setting a0 (toa0): sets the value of timer output tioca 0 . bit 0 toa0 description 0 tioca 0 is 0 (initial value) 1 tioca 0 is 1 8. 16-bit timer rev.4.00 aug. 20, 2007 page 206 of 638 rej09b0395-0400 8.3 cpu interface 8.3.1 16-bit accessible registers the timer counters (16tcnts), general registers a and b (gras and grbs) are 16-bit registers, and are linked to the cpu by an internal 16-bit data bus. these registers can be written or read a word at a time, or a byte at a time. figures 8.4 and 8.5 show examples of word read/write access to a timer counter (16tcnt). figures 8.6 to 8.9 show examples of byt e read/write access to 16tcnth and 16tcntl. on-chip data bus cpu h l bus interface h l module data bus 16tcnth 16tcntl figure 8.4 16tcnt access operation [cpu 16tcnt (word)] on-chip data bus cpu h l bus interface h l module data bus 16tcnth 16tcntl figure 8.5 access to timer counter (cpu reads 16tcnt, word) 8. 16-bit timer rev.4.00 aug. 20, 2007 page 207 of 638 rej09b0395-0400 on-chip data bus cpu h l bus interface h l module data bus 16tcnth 16tcntl figure 8.6 access to timer counter h (c pu writes to 16tcnth, upper byte) on-chip data bus cpu h l bus interface h l module data bus 16tcnth 16tcntl figure 8.7 access to timer counter l (cpu writes to 16tcntl, lower byte) on-chip data bus cpu h l bus interface h l module data bus 16tcnth 16tcntl figure 8.8 access to timer counter h (cpu reads 16tcnth, upper byte) 8. 16-bit timer rev.4.00 aug. 20, 2007 page 208 of 638 rej09b0395-0400 on-chip data bus cpu h l bus interface h l module data bus 16tcnth 16tcntl figure 8.9 access to timer counter l (cpu reads 16tcntl, lower byte) 8.3.2 8-bit accessible registers the registers other than the timer counters and gene ral registers are 8-bit registers. these registers are linked to the cpu by an internal 8-bit data bus. figures 8.10 and 8.11 show examples of byte read and write access to a 16tcr. if a word-size data transfer instruction is executed, two byte transfers are performed. on-chip data bus cpu h l bus interface h l module data bus 16tcr figure 8.10 16tcr access (cpu writes to 16tcr) 8. 16-bit timer rev.4.00 aug. 20, 2007 page 209 of 638 rej09b0395-0400 on-chip data bus cpu h l bus interface h l module data bus 16tcr figure 8.11 16tcr access (cpu reads 16tcr) 8.4 operation 8.4.1 overview a summary of operations in the various modes is given below. normal operation: each channel has a timer counter and general registers. the timer counter counts up, and can operate as a free-running counter, periodic counter, or external event counter. gra and grb can be used for input capture or output compare. synchronous operation: the timer counters in designated channels are preset synchronously. data written to the timer counter in any one of these channels is simultaneously written to the timer counters in the other channels as well. the timer counters can also be cleared synchronously if so designated by the cclr1 and cclr0 bits in the tcrs. pwm mode: a pwm waveform is output from the tioca pin. the output goes to 1 at compare match a and to 0 at compare match b. the duty cycle can be varied from 0 % to 100 % depending on the settings of gra and grb. when a channel is set to pwm mode, its gra and grb automatically become out put compare registers. phase counting mode: the phase relationship between two clock signals input at tclka and tclkb is detected and 16tcnt2 counts up or down accordingly. when phase counting mode is selected tclka and tclkb become clock input pins and 16tcnt2 operates as an up/down- counter. 8.4.2 basic functions counter operation: when one of bits str0 to str2 is set to 1 in the timer start register (tstr), the timer counter (16tcnt) in the corresponding channel starts counting. the counting can be free-running or periodic. 8. 16-bit timer rev.4.00 aug. 20, 2007 page 210 of 638 rej09b0395-0400 ? sample setup procedure for counter figure 8.12 shows a sample procedure for setting up a counter. counter setup select counter clock count operation periodic countin g select counter clear source select output compare re g ister function set period start counter free-runnin g countin g start counter periodic counter free-runnin g counter 1 ye s no 2 3 4 55 figure 8.12 counter setup procedure (example) 1. set bits tpsc2 to tpsc0 in 16tcr to select the counter clock source. if an external clock source is selected, set bits ckeg1 and ckeg0 in 16tcr to select the desired edge(s) of the external clock signal. 2. for periodic counting, set cclr1 and cclr0 in 16tcr to have 16tcnt cleared at gra compare match or grb compare match. 3. set tior to select the output compare function of gra or grb, whichever was selected in step 2. 4. write the count period in gra or grb, whichever was selected in step 2. 8. 16-bit timer rev.4.00 aug. 20, 2007 page 211 of 638 rej09b0395-0400 5. set the str bit to 1 in tstr to start the timer counter. ? free-running and periodic counter operation a reset leaves the counters (16tcnts) in 16-bit timer channels 0 to 2 all set as free-running counters. a free-running counter starts counting up when the corresponding bit in tstr is set to 1. when the count overflows from h'ffff to h'0000, the ovf flag is set to 1 in tisrc. after the overflow, the counter continues co unting up from h'0000. figure 8.13 illustrates free-running counting. 16tcnt value h'ffff h'0000 str0 to str2 bit ovf time figure 8.13 free-running counter operation when a channel is set to have its counter cleared by compare match, in that channel 16tcnt operates as a periodic counter. select the output compare function of gra or grb, set bit cclr1 or cclr0 in 16tcr to have the counter cleared by compare match, and set the count period in gra or grb. after these settings, the counter starts counting up as a periodic counter when the corresponding bit is set to 1 in tstr. when the count matches gra or grb, the imfa or imfb flag is set to 1 in tisra/tisrb and the counter is cleared to h'0000. if the corresponding imiea or imieb bit is set to 1 in tisra/tisrb, a cpu interrupt is requested at this time. after the compare match, 16tcnt continues counting up from h'0000. figure 8.14 illu strates periodic counting. 8. 16-bit timer rev.4.00 aug. 20, 2007 page 212 of 638 rej09b0395-0400 16tcnt value gr h'0000 str bit imf time counter cleared by g eneral re g ister compare match figure 8.14 period ic counter operation ? 16tcnt count timing ? internal clock source bits tpsc2 to tpsc0 in 16tcr select the system clock ( ) or one of three internal clock sources obtained by prescaling the system clock ( /2, /4, /8). figure 8.15 shows the timing. internal clock 16tcnt input clock 16tcnt n ? 1 n n + 1 figure 8.15 count timing for internal clock sources ? external clock source the external clock pin (tclka to tclkd) can be selected by bits tpsc2 to tpsc0 in 16tcr, and the detected edge by bits ckeg1 and ckeg0. the rising edge, falling edge, or both edges can be selected. the pulse width of the external clock signal must be at least 1.5 system clocks when a single edge is selected, and at least 2.5 system clocks when both edge s are selected. shorter pulses will not be counted correctly. figure 8.16 shows the timing when both edges are detected. 8. 16-bit timer rev.4.00 aug. 20, 2007 page 213 of 638 rej09b0395-0400 external clock input 16tcnt input clock 16tcnt n ? 1 n n + 1 figure 8.16 count timing for external cl ock sources (when both edges are detected) waveform output by compare match: in 16-bit timer channels 0, 1 compare match a or b can cause the output at the tioca or tiocb pin to go to 0, go to 1, or toggle. in channel 2 the output can only go to 0 or go to 1. ? sample setup procedure for waveform output by compare match figure 8.17 shows an example of the setup procedure for waveform output by compare match. output setup select waveform output mode set output timin g start counter waveform output select the compare match output mode (0, 1, or to gg le) in tior. when a waveform output mode is selected, the pin switches from its g eneric input/ output function to the output compare function (tioca or tiocb). an output compare pin outputs the value set in tolr until the first compare match occurs. set a value in gra or grb to desi g nate the compare match timin g . set the str bit to 1 in tstr to start the timer counter. 1 2 3 1. 2. 3. figure 8.17 setup procedure for wavefo rm output by compare match (example) 8. 16-bit timer rev.4.00 aug. 20, 2007 page 214 of 638 rej09b0395-0400 ? examples of waveform output figure 8.18 shows examples of 0 and 1 output. 16tcnt operates as a free-running counter, 0 output is selected for compare match a, and 1 ou tput is selected for compare match b. when the pin is already at the selected output level, the pin level does not change. time h'ffff grb tiocb tioca gra no chan g e no chan g e no chan g e no chan g e 1 output 0 output 16tcnt value h'0000 figure 8.18 0 and 1 output (toa = 1, tob = 0) figure 8.19 shows examples of toggle output. 16tcnt operates as a periodic counter, cleared by compare match b. toggle output is selected for both compare match a and b. grb tiocb tioca gra 16tcnt value time counter cleared by compare match with grb to gg le output to gg le output h'0000 figure 8.19 toggle output (toa = 1, tob = 0) 8. 16-bit timer rev.4.00 aug. 20, 2007 page 215 of 638 rej09b0395-0400 ? output compare output timing the compare match signal is generated in the last state in which 16tcnt and the general register match (when 16tcnt changes from the matching value to the next value). when the compare match signal is generated, the output value selected in tior is output at the output compare pin (tioca or tiocb). when 16tcnt matches a general register, the compare match signal is not generated until the next counter clock pulse. figure 8.20 shows the output compare timing. n + 1 n n 16tcnt input clock 16tcnt gr compare match si g nal tioca, tiocb figure 8.20 output compare output timing input capture function: the 16tcnt value can be transferre d to a general register when an input edge is detected at an input capture input/output compare pin (tioca or tiocb). rising- edge, falling-edge, or both-edge de tection can be selected. the input capture function can be used to measure pulse width or period. 8. 16-bit timer rev.4.00 aug. 20, 2007 page 216 of 638 rej09b0395-0400 ? sample setup procedure for input capture figure 8.21 shows a sample procedure for setting up input capture. input selection select input-capture input start counter input capture set tior to select the input capture function of a g eneral re g ister and the risin g ed g e, fallin g ed g e, or both ed g es of the input capture si g nal. clear the ddr bit to 0 before makin g these tior settin g s. set the str bit to 1 in tstr to start the timer counter. 1 2 1. 2. figure 8.21 setup procedure for input capture (example) ? examples of input capture figure 8.22 illustrates input capture when the falling edge of tiocb and both edges of tioca are selected as capture edges. 16tcnt is cleared by input capture into grb. h'0005 h'0180 h'0180 h'0160 h'0005 h'0000 tiocb tioca gra grb 16tcnt value h'0160 figure 8.22 input capture (example) 8. 16-bit timer rev.4.00 aug. 20, 2007 page 217 of 638 rej09b0395-0400 ? input capture signal timing input capture on the rising edge, falling edge, or both edges can be sel ected by settings in tior. figure 8.23 shows the timing when the rising edge is selected. the pulse width of the input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system clocks for capture of both edges. n n input-capture input input capture si g nal 16tcnt gra, grb figure 8.23 input capture signal timing 8.4.3 synchronization the synchronization function enables two or more timer counters to be synchronized by writing the same data to them simultaneously (synchronous preset). with appropriate 16tcr settings, two or more timer counters can also be cleared simultaneously (synchronous clear). synchronization enables additional general registers to be associated with a single time base. synchronization can be selected for all channels (0 to 2). sample setup procedure for synchronization: figure 8.24 shows a sample procedure for setting up synchronization. 8. 16-bit timer rev.4.00 aug. 20, 2007 page 218 of 638 rej09b0395-0400 setup for synchronization synchronous preset set the sync bits to 1 in tsnc for the channels to be synchronized. when a value is written in 16tcnt in one of the synchronized channels, the same value is simultaneously written in 16tcnt in the other channels. set the cclr1 or cclr0 bit in 16tcr to have the counter cleared by compare match or input capture. set the cclr1 and cclr0 bits in 16tcr to have the counter cleared synchronously. set the str bits in tstr to 1 to start the synchronized counters. 1. 2. 3. 4. 5. 2 3 1 5 4 5 select synchronization synchronous preset write to 16tcnt synchronous clear clearin g synchronized to this channel? select counter clear source start counter counter clear synchronous clear start counter select counter clear source ye s no figure 8.24 setup procedure for synchronization (example) example of synchronization: figure 8.25 shows an example of synchronization. channels 0, 1, and 2 are synchronized, and are set to operate in pwm mode. channel 0 is set for counter clearing by compare match with grb0. channels 1 and 2 are set for synchronous counter clearing. the timer counters in channels 0, 1, and 2 are synchronously preset, and are synchronously cleared by compare match with grb0. a three-phase pwm waveform is output from pins tioca 0 , tioca 1 , and tioca 2 . for further information on pwm mode, see section 8.4.4, pwm mode. 8. 16-bit timer rev.4.00 aug. 20, 2007 page 219 of 638 rej09b0395-0400 tioca 2 tioca 1 tioca 0 gra2 gra1 grb2 gra0 grb1 grb0 value of 16tcnt0 to 16tcnt2 cleared by compare match with grb0 h'0000 figure 8.25 synchronization (example) 8.4.4 pwm mode in pwm mode gra and grb are paired and a pwm waveform is output from the tioca pin. gra specifies the time at which the pwm output ch anges to 1. grb specifies the time at which the pwm output changes to 0. if either gra or grb compare match is selected as the counter clear source, a pwm waveform with a duty cycle from 0 % to 100 % is output at the tioca pin. pwm mode can be selected in all channels (0 to 2). table 8.4 summarizes the pwm output pins and corresponding registers. if the same value is set in gra and grb, the output does not change when compare match occurs. 8. 16-bit timer rev.4.00 aug. 20, 2007 page 220 of 638 rej09b0395-0400 table 8.4 pwm output pins and registers channel output pin 1 output 0 output 0 tioca 0 gra0 grb0 1 tioca 1 gra1 grb1 2 tioca 2 gra2 grb2 sample setup procedure for pwm mode: figure 8.26 shows a sample procedure for setting up pwm mode. pwm mode 1. 2. 3. 4. 5. 6. set bits tpsc2 to tpsc0 in 16tcr to select the counter clock source. if an external clock source is selected, set bits ckeg1 and ckeg0 in 16tcr to select the desired ed g e(s) of the external clock si g nal. set bits cclr1 and cclr0 in 16tcr to select the counter clear source. set the time at which the pwm waveform should g o to 1 in gra. set the time at which the pwm waveform should g o to 0 in grb. set the pwm bit in tmdr to select pwm mode. when pwm mode is selected, re g ardless of the tior contents, gra and grb become output compare re g isters specifyin g the times at which the pwm output g oes to 1 and 0. the tioca pin automatically becomes the pwm output pin. the tiocb pin conforms to the settin g s of bits iob1 and iob0 in tior. if tiocb output is not desired, clear both iob1 and iob0 to 0. set the str bit to 1 in tstr to start the timer counter. pwm mode select counter clock 1 select counter clear source 2 set gra 3 set grb 4 select pwm mode 5 start counter 6 figure 8.26 setup procedu re for pwm mode (example) 8. 16-bit timer rev.4.00 aug. 20, 2007 page 221 of 638 rej09b0395-0400 examples of pwm mode: figure 8.27 shows examples of operation in pwm mode. in pwm mode tioca becomes an output pin. the output goes to 1 at compare match with gra, and to 0 at compare match with grb. in the examples shown, 16tcnt is cleared by compare match with gra or grb. synchronized operation and free-running counting are also possible. 16tcnt value counter cleared by compare match a time gra grb tioca a. counter cleared by gra (toa = 1) 16tcnt value counter cleared by compare match b time grb gra tioca b. counter cleared by grb (toa = 0) h'0000 h'0000 figure 8.27 pwm mode (example 1) 8. 16-bit timer rev.4.00 aug. 20, 2007 page 222 of 638 rej09b0395-0400 figure 8.28 shows examples of the output of pwm waveforms with duty cycles of 0 % and 100 % . if the counter is cleared by compare match with gr b, and gra is set to a higher value than grb, the duty cycle is 0 % . if the counter is cleared by compare match with gra, and grb is set to a higher value than gra, the duty cycle is 100 % . 16tcnt value counter cleared by compare match b time grb gra tioca a. 0 % duty cycle (toa = 0) 16tcnt value counter cleared by compare match a time gra grb tioca b. 100 % duty cycle (toa = 1) write to gra write to gra write to grb write to grb h'0000 h'0000 figure 8.28 pwm mode (example 2) 8. 16-bit timer rev.4.00 aug. 20, 2007 page 223 of 638 rej09b0395-0400 8.4.5 phase counting mode in phase counting mode the phase difference between two external clock inputs (at the tclka and tclkb pins) is detect ed, and 16tcnt2 counts up or down accordingly. in phase counting mode, the tclka and tclkb pins automatically function as external clock input pins and 16tcnt2 becomes an up/down-counter, regardless of the settings of bits tpsc2 to tpsc0, ckeg1, and ckeg0 in 16tcr2. settings of bits cclr1, cclr0 in 16tcr2, and settings in tior2, tisra, tisrb, tisrc, setting of str2 bit in tstr, gra2, and grb2 are valid. the input capture and output compare f unctions can be used, and interrupts can be generated. phase counting is available only in channel 2. sample setup procedure for phase counting mode: figure 8.29 shows a sample procedure for setting up phase counting mode. phase countin g mode select phase countin g mode select fla g settin g condition start counter 1 2 3 phase countin g mode 1. 2. 3. set the mdf bit in tmdr to 1 to select phase countin g mode. select the fla g settin g condition with the fdir bit in tmdr. set the str2 bit to 1 in tstr to start the timer counter. figure 8.29 setup procedure for phase counting mode (example) 8. 16-bit timer rev.4.00 aug. 20, 2007 page 224 of 638 rej09b0395-0400 example of phase counting mode: figure 8.30 shows an example of operations in phase counting mode. table 8.5 lists the up-counting and down-counting conditions for 16tcnt2. in phase counting mode both the rising and falling edges of tclka and tclkb are counted. the phase difference between tclka and tclkb must be at least 1.5 states, the phase overlap must also be at least 1.5 states, and the pul se width must be at least 2.5 states. 16tcnt2 value countin g up countin g down tclkb tclka figure 8.30 operation in phase counting mode (example) table 8.5 up/down counting conditions counting direction up-counting down-counting tclkb pin high low high low tclka pin low high low high tclka tclkb phase difference phase difference pulse width pulse width overlap overlap phase difference and overlap: pulse width: at least 1.5 states at least 2.5 states figure 8.31 phase differen ce, overlap, and pulse widt h in phase counting mode 8. 16-bit timer rev.4.00 aug. 20, 2007 page 225 of 638 rej09b0395-0400 8.4.6 16-bit timer output timing the initial value of 16-bit timer output when a timer count operation begins can be specified arbitrarily by making a setting in tolr. figure 8.32 shows the timing for setting the initial value with tolr. only write to tolr when the correspo nding bit in tstr is cleared to 0. t 1 tolr address n n t 2 t 3 address bus tolr 16-bit timer output pin figure 8.32 timing for setting 16-bit timer output level by writing to tolr 8. 16-bit timer rev.4.00 aug. 20, 2007 page 226 of 638 rej09b0395-0400 8.5 interrupts the 16-bit timer has two types of interrupts: input capture/compare match interrupts, and overflow interrupts. 8.5.1 setting of status flags timing of setting of imfa and imfb at compare match: imfa and imfb are set to 1 by a compare match signal generated when 16tcnt matches a general register (gr). the compare match signal is generated in the last state in which the values match (when 16tcnt is updated from the matching count to the next count). therefore, when 16tcnt matches a general register, the compare match signal is not generated until th e next 16tcnt clock input . figure 8.33 shows the timing of the setting of imfa and imfb. 16tcnt gr imf imi 16tcnt input clock compare match si g nal nn + 1 n figure 8.33 timing of setting of imfa and imfb by compare match 8. 16-bit timer rev.4.00 aug. 20, 2007 page 227 of 638 rej09b0395-0400 timing of setting of imfa and imfb by input capture: imfa and imfb are set to 1 by an input capture signal. the 16tcnt contents are simultaneously transferred to the corresponding general register. figure 8.34 shows the timing. input capture si g nal n n imf 16tcnt gr imi figure 8.34 timing of setting of imfa and imfb by input capture 8. 16-bit timer rev.4.00 aug. 20, 2007 page 228 of 638 rej09b0395-0400 timing of setting of overflow flag (ovf): ovf is set to 1 when 16tcnt overflows from h'ffff to h'0000 or underflows from h'00 00 to h'ffff. figure 8. 35 shows the timing. overflow si g nal 16tcnt ovf ovi figure 8.35 timing of setting of ovf 8.5.2 timing of clearing of status flags if the cpu reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared. figure 8.36 shows the timing. address imf, ovf tisr write cycle tisr address t 1 t 2 t 3 figure 8.36 timing of clearing of status flags 8. 16-bit timer rev.4.00 aug. 20, 2007 page 229 of 638 rej09b0395-0400 8.5.3 interrupt sources each 16-bit timer channel can generate a comp are match/input capture a interrupt, a compare match/input capture b interrupt, and an overflow interrupt. in total there are nine interrupt sources of three kinds, all independently vectored. an interrupt is requested when the interrupt request flag are set to 1. the priority order of the channels can be modified in interrupt priority registers a (ipra). for details see section 5, interrupt controller. table 8.6 lists the interrupt sources. table 8.6 16-bit timer interrupt sources channel interrupt source description priority * 0 imia0 imib0 ovi0 compare match/input capture a0 compare match/input capture b0 overflow 0 high 1 imia1 imib1 ovi1 compare match/input capture a1 compare match/input capture b1 overflow 1 2 imia2 imib2 ovi2 compare match/input capture a2 compare match/input capture b2 overflow 2 low note: * the priority immediately after a reset is indicated. inter-channel priorities can be changed by settings in ipra. 8. 16-bit timer rev.4.00 aug. 20, 2007 page 230 of 638 rej09b0395-0400 8.6 usage notes this section describes contention and other matters requiring special attention during 16-bit timer operations. contention between 16tcnt write and clear: if a counter clear signal occurs in the t 3 state of a 16tcnt write cycle, clearing of the counter takes priority and the write is not performed. see figure 8.37. address bus internal write si g nal counter clear si g nal 16tcnt 16tcnt write cycle 16tcnt address n h'0000 t 1 t 2 t 3 figure 8.37 contention be tween 16tcnt write and clear 8. 16-bit timer rev.4.00 aug. 20, 2007 page 231 of 638 rej09b0395-0400 contention between 16tcnt word write and increment: if an increment pulse occurs in the t 3 state of a 16tcnt word write cycle, writing takes priority and 16tcnt is not incremented. figure 8.38 shows the timing in this case. address bus internal write si g nal 16tcnt input clock 16tcnt n 16tcnt address m 16tcnt write data 16tcnt word write cycle t 1 t 2 t 3 figure 8.38 contention between 16tcnt word write and increment 8. 16-bit timer rev.4.00 aug. 20, 2007 page 232 of 638 rej09b0395-0400 contention between 16tcnt byte write and increment: if an increment pulse occurs in the t 2 or t 3 state of a 16tcnt byte write cycle, writing takes priority and 16tcnt is not incremented. the byte data for which a write was not performed is not incremented, and retains its pre-write value. see figure 8.39, which shows an increment pulse occurring in the t 2 state of a byte write to 16tcnth. address bus internal write si g nal 16tcnt input clock 16tcnth 16tcntl 16tcnth byte write cycle t 1 t 2 t 3 n 16tcnth address m 16tcnt write data xx x + 1 figure 8.39 contention between 16tcnt byte write and increment 8. 16-bit timer rev.4.00 aug. 20, 2007 page 233 of 638 rej09b0395-0400 contention between general re gister write and compare match: if a compare match occurs in the t 3 state of a general register write cycle, writing takes priority and the compare match signal is inhibited. see figure 8.40. address bus internal write si g nal 16tcnt gr compare match si g nal general re g ister write cycle t 1 t 2 t 3 n gr address m n n + 1 general re g ister write data inhibited figure 8.40 contention between gen eral register write and compare match 8. 16-bit timer rev.4.00 aug. 20, 2007 page 234 of 638 rej09b0395-0400 contention between 16tcnt writ e and overflow or underflow: if an overflow occurs in the t 3 state of a 16tcnt write cycle, writing takes priority and the counter is not incremented. ovf is set to 1.the same holds for underflow. see figure 8.41. address bus internal write si g nal 16tcnt input clock overflow si g nal 16tcnt ovf h'ffff 16tcnt address m 16tcnt write data 16tcnt write cycle t 1 t 2 t 3 figure 8.41 contention between 16tcnt write and overflow 8. 16-bit timer rev.4.00 aug. 20, 2007 page 235 of 638 rej09b0395-0400 contention between general register read and input capture: if an input capture signal occurs during the t 3 state of a general register read cycle, the value before input capture is read. see figure 8.42. address bus internal read si g nal input capture si g nal gr internal data bus gr address x general re g ister read cycle t 1 t 2 t 3 xm figure 8.42 contention between general register read and input capture 8. 16-bit timer rev.4.00 aug. 20, 2007 page 236 of 638 rej09b0395-0400 contention between counter clearing by input capture and counter increment: if an input capture signal and counter increm ent signal occur simultaneously, th e counter is cleared according to the input capture signal. the counter is not incremented by the increment signal. the value before the counter is cleared is transferred to the general register. see figure 8.43. input capture si g nal counter clear si g nal 16tcnt input clock 16tcnt gr n n h'0000 figure 8.43 contention between counter clearing by input capture and counter increment 8. 16-bit timer rev.4.00 aug. 20, 2007 page 237 of 638 rej09b0395-0400 contention between general re gister write and input capture: if an input capture signal occurs in the t 3 state of a general register write cycle, input capture takes priority and the write to the general register is not performed. see figure 8.44. address bus internal write si g nal input capture si g nal 16tcnt gr m gr address general re g ister write cycle t 1 t 2 t 3 m figure 8.44 contention between general register write and input capture 8. 16-bit timer rev.4.00 aug. 20, 2007 page 238 of 638 rej09b0395-0400 note on waveform period setting: when a counter is cleared by compare match, the counter is cleared in the last state at whic h the 16tcnt value matches the general register value, at the time when this value would normally be updated to the next count. the actual counter frequency is therefore given by the following formula: f = (n + 1) (f: counter frequency. : system clock frequency. n: value set in general register.) note on writes in sy nchronized operation: when channels are synchronized, if a 16tcnt value is modified by byte write access, all 16 bits of all synchronized counters assume the same value as the counter that was addressed. (example) when channels 1 and 2 are synchronized ? byte write to channel 1 or byte write to channel 2 16tcnt1 16tcnt2 w y x z 16tcnt1 16tcnt2 a a x x 16tcnt1 16tcnt2 y y a a 16tcnt1 16tcnt2 w y x z 16tcnt1 16tcnt2 a a b b ? word write to channel 1 or word write to channel 2 upper byte lower byte upper byte lower byte upper byte lower byte upper byte lower byte upper byte lower byte write a to upper byte of channel 1 write a to lower byte of channel 2 write ab word to channel 1 or 2 8. 16-bit timer rev.4.00 aug. 20, 2007 page 239 of 638 rej09b0395-0400 16-bit timer operating modes table 8.7 (a) 16-bit timer operating modes (channel 0) register settings tsnc tmdr tior0 16tcr0 syn c hro- clear clo c k operating mode nization mdf fdir pwm ioa iob sele c t sele c t synchronous preset sync0 = 1 ?? pwm mode ?? pwm0 = 1 ? * output compare a ?? pwm0 = 0 ioa2 = 0 other bits unrestricted output compare b ? ? iob2 = 0 other bits unrestricted input capture a ?? pwm0 = 0 ioa2 = 1 other bits unrestricted input capture b ?? pwm0 = 0 iob2 = 1 other bits unrestricted counter by compare ? ? cclr1 = 0 clearin g match/input cclr0 = 1 capture a by compare ?? cclr1 = 1 match/input cclr0 = 0 capture b syn- sync0 = 1 ?? cclr1 = 1 chronous cclr0 = 1 clear le g e nd: : settin g av ailable (v alid). ?: settin g do es not affe ct this m ode. note: the input capture function cannot be used in pwm mode. if compare match a and compare match b occur simultaneously, the compare match si g nal is inhibited. * 8. 16-bit timer rev.4.00 aug. 20, 2007 page 240 of 638 rej09b0395-0400 table 8.7 (b) 16-bit timer operating modes (channel 1) register settings tsnc tmdr tior1 16tcr1 syn c hro- clear clo c k operating mode nization mdf fdir pwm ioa iob sele c t sele c t synchronous preset sync1 = 1 ?? pwm mode ?? pwm1 = 1 ? output compare a ?? pwm1 = 0 ioa2 = 0 other bits unrestricted output compare b ?? iob2 = 0 other bits unrestricted input capture a ?? pwm1 = 0 ioa2 = 1 other bits unrestricted input capture b ?? pwm1 = 0 iob2 = 1 other bits unrestricted counter by compare ?? cclr1 = 0 clearin g match/input cclr0 = 1 capture a by compare ?? cclr1 = 1 match/input cclr0 = 0 capture b syn- sync1 = 1 ?? cclr1 = 1 chronous cclr0 = 1 clear * le g e nd: : settin g av ailable (v alid). ?: settin g do es not affe ct this m ode. note: the input capture function cannot be used in pwm mode. if compare match a and compare match b occur simultaneously, the compare match si g nal is inhibited. * 8. 16-bit timer rev.4.00 aug. 20, 2007 page 241 of 638 rej09b0395-0400 table 8.7 (c) 16-bit timer operating modes (channel 2) register settings tsnc tmdr tior2 16tcr2 syn c hro- clear clo c k operating mode nization mdf fdir pwm ioa iob sele c t sele c t synchronous preset sync2 = 1 ? pwm mode ? pwm2 = 1 ? * output compare a ? pwm2 = 0 ioa2 = 0 other bits unrestricted output compare b ? iob2 = 0 other bits unrestricted input capture a ? pwm2 = 0 ioa2 = 1 other bits unrestricted input capture b ? pwm2 = 0 iob2 = 1 other bits unrestricted counter by compare ? cclr1 = 0 clearin g match/input cclr0 = 1 capture a by compare ? cclr1 = 1 match/input cclr0 = 0 capture b syn- sync2 = 1 ? cclr1 = 1 chronous cclr0 = 1 clear phase countin g mdf = 1 ? mode le g e nd: : settin g av ailable (v alid). ?: settin g do es not affe ct this m ode. note: the input capture function cannot be used in pwm mode. if compare match a and compare match b occur simultaneously, the compare match si g nal is inhibited. * 8. 16-bit timer rev.4.00 aug. 20, 2007 page 242 of 638 rej09b0395-0400 9. 8-bit timers rev.4.00 aug. 20, 2007 page 243 of 638 rej09b0395-0400 section 9 8-bit timers 9.1 overview the h8/3008 has a built-in 8-bit timer module with four channels (tmr0, tmr1, tmr2, and tmr3), based on 8-bit counters. each channel has an 8-bit timer counter (8tcnt) and two 8-bit time constant registers (tcora and tcorb) th at are constantly comp ared with the 8tcnt value to detect compare match events. the timers can be used as multifunctional timers in a variety of applications, including the generation of a rectangular-wave output with an arbitrary duty cycle. 9.1.1 features the features of the 8-bit timer module are listed below. ? selection of four clock sources the counters can be driven by one of three internal clock signals ( /8, /64, or /8192) or an external clock input (enabling use as an external event counter). ? selection of three ways to clear the counters the counters can be cleared on compare match a or b, or input capture b. ? timer output controlled by two compare match signals the timer output signal in each channel is controlled by two independent compare match signals, enabling the timer to generate output waveforms with an arbitrary duty cycle or pwm output. ? a/d converter can be activated by a compare match ? two channels can be cascaded ? channels 0 and 1 can be operated as the upper and lower halves of a 16-bit timer (16-bit count mode). ? channels 2 and 3 can be operated as the upper and lower halves of a 16-bit timer (16-bit count mode). ? channel 1 can count channel 0 compare matc h events (compare match count mode). ? channel 3 can count channel 2 compare matc h events (compare match count mode). ? input capture function can be set 8-bit or 16-bit input capture operation is available. ? twelve interrupt sources there are twelve interrupt sources: four compare match sources, four compare match/input capture sources, four overflow sources. 9. 8-bit timers rev.4.00 aug. 20, 2007 page 244 of 638 rej09b0395-0400 two of the compare match sources and two of the combined compare match/input capture sources each have an independent interrupt v ector. the remaining compare match interrupts, combined compare match/input capture interrupts, and overflow interrupts have one interrupt vector for two sources. 9. 8-bit timers rev.4.00 aug. 20, 2007 page 245 of 638 rej09b0395-0400 9.1.2 block diagram the 8-bit timers are divided into two groups of two channels each: group 0 comprising channels 0 and 1, and group 1 comprising channels 2 and 3. figure 9.1 shows a block diagram of 8-bit timer group 0. /8 /64 /8192 cmia0 cmib0 cmia1/cmib1 ovi0/ovi1 interrupt si g nals tmo 0 tmio 1 tcora0 tcorb0 8tcsr0 8tcr0 tcora1 8tcnt1 tcorb1 8tcsr1 8tcr1 tclka tclkc 8tcnt0 le g end: tcora: time constant re g ister a tcorb: time constant re g ister b 8tcnt: timer counter 8tcsr: timer control/status re g ister 8tcr: timer control re g ister external clock sources internal clock sources clock select control lo g ic clock 1 clock 0 compare match a1 compare match a0 overflow 1 overflow 0 compare match b1 compare match b0 input capture b1 comparator a0 comparator a1 comparator b0 comparator b1 internal bus figure 9.1 block diagram of 8-bit timer unit (two channels: group 0) 9. 8-bit timers rev.4.00 aug. 20, 2007 page 246 of 638 rej09b0395-0400 9.1.3 pin configuration table 9.1 summarizes the input/output pins of the 8-bit timer module. table 9.1 8-bit timer pins group channel name abbreviation i/o function 0 0 timer output tmo 0 output compare match output timer clock input tclkc input counter external clock input 1 timer input/output tmio 1 i/o compare match output/input capture input timer clock input tclka input counter external clock input 1 2 timer output tmo 2 output compare match output timer clock input tclkd input counter external clock input 3 timer input/output tmio 3 i/o compare match output/input capture input timer clock input tclkb input counter external clock input 9. 8-bit timers rev.4.00 aug. 20, 2007 page 247 of 638 rej09b0395-0400 9.1.4 register configuration table 9.2 summarizes the regist ers of the 8-bit timer module. table 9.2 8-bit timer registers channel address * 1 name abbreviation r/w initial value 0 h'fff80 timer control register 0 8tcr0 r/w h'00 h'fff82 timer control/status register 0 8tcsr0 r/(w) * 2 h'00 h'fff84 time constant register a0 tcora0 r/w h'ff h'fff86 time constant register b0 tcorb0 r/w h'ff h'fff88 timer counter 0 8tcnt0 r/w h'00 1 h'fff81 timer control register 1 8tcr1 r/w h'00 h'fff83 timer control/status register 1 8tcsr1 r/(w) * 2 h'00 h'fff85 time constant register a1 tcora1 r/w h'ff h'fff87 time constant register b1 tcorb1 r/w h'ff h'fff89 timer counter 1 8tcnt1 r/w h'00 2 h'fff90 timer control register 2 8tcr2 r/w h'00 h'fff92 timer control/status register 2 8tcsr2 r/(w) * 2 h'10 h'fff94 time constant register a2 tcora2 r/w h'ff h'fff96 time constant register b2 tcorb2 r/w h'ff h'fff98 timer counter 2 8tcnt2 r/w h'00 3 h'fff91 timer control register 3 8tcr3 r/w h'00 h'fff93 timer control/status register 3 8tcsr3 r/(w) * 2 h'00 h'fff95 time constant register a3 tcora3 r/w h'ff h'fff97 time constant register b3 tcorb3 r/w h'ff h'fff99 timer counter 3 8tcnt3 r/w h'00 notes: 1. indicates the lower 20 bits of the address in advanced mode. 2. only 0 can be written to bits 7 to 5, to clear these flags. each pair of registers for channel 0 and channel 1 comprises a 16-bit register with the channel 0 register as the upper 8 bits and the channel 1 register as the lower 8 bits, so they can be accessed together by word access. similarly, each pair of registers for channel 2 a nd channel 3 comprises a 16-bit register with the channel 2 register as the upper 8 bits and the channel 3 register as the lower 8 bits, so they can be accessed together by word access. 9. 8-bit timers rev.4.00 aug. 20, 2007 page 248 of 638 rej09b0395-0400 9.2 register descriptions 9.2.1 timer counters (8tcnt) 15 0 r/w bit initial value read/write 14 0 r/w bit initial value read/write 13 0 r/w 12 0 r/w 11 0 r/w 10 0 r/w 9 0 r/w 8 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w 8tcnt0 8tcnt1 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 10 0 r/w 9 0 r/w 8 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w 8tcnt2 8tcnt3 the timer counters (8tcnt) are 8-bit readable/writable up-counters that increment on pulses generated from an internal or external clock source. the clock source is selected by clock select bits 2 to 0 (cks2 to cks0) in the timer contro l register (8tcr). the cpu can always read or write to the timer counters. the 8tcnt0 and 8tcnt1 pair, and the 8tcnt2 and 8tcnt3 pair, can each be accessed as a 16-bit register by word access. 8tcnt can be cleared by an input capture signal or compare match signal. counter clear bits 1 and 0 (cclr1 and cclr0) in 8tcr select the method of clearing. when 8tcnt overflows from h'ff to h'00, the overflow flag (ovf) in the timer control/status register (8tcsr) is set to 1. each 8tcnt is initialized to h'00 by a reset and in standby mode. 9. 8-bit timers rev.4.00 aug. 20, 2007 page 249 of 638 rej09b0395-0400 9.2.2 time constant registers a (tcora) tcora0 to tcora3 are 8-bit readable/writable registers. 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcora0 tcora1 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcora2 tcora3 bit initial value read/write bit initial value read/write the tcora0 and tcora1 pair, and the tcora2 and tcora3 pair, can each be accessed as a 16-bit register by word access. the tcora value is constantly compared with th e 8tcnt value. when a match is detected, the corresponding compare match flag a (cmfa) is set to 1 in 8tcsr. the timer output can be freely controlled by these compare match signals and the settings of output select bits 1 and 0 (os1, os0) in 8tcsr. each tcora register is initialized to h'ff by a reset and in standby mode. 9. 8-bit timers rev.4.00 aug. 20, 2007 page 250 of 638 rej09b0395-0400 9.2.3 time constant registers b (tcorb) 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcorb0 tcorb1 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcorb2 tcorb3 bit initial value read/write bit initial value read/write tcorb0 to tcorb3 are 8-bit readable/writable registers. the tcorb0 and tcorb1 pair, and the tcorb2 and tcorb3 pair, can each be accessed as a 16-bit register by word access. the tcorb value is constantly compared with th e 8tcnt value. when a match is detected, the corresponding compare match flag b (cmfb) is set to 1 in 8tcsr*. the timer output can be freely controlled by these compare match signals and the settings of output/input capture edge select bits 3 and 2 (ois3, ois2) in 8tcsr. when tcorb is used for input capture, it stores the 8tcnt value on detection of an external input capture signal. at this time, the cmfb flag is set to 1 in the corresponding 8tcsr register. the detected edge of the input capture signal is set in 8tcsr. each tcorb register is initialized to h'ff by a reset and in standby mode. note: * when channel 1 and channel 3 are designated for tcorb input capture, the cmfb flag is not set by a channel 0 or channel 2 compare match b. 9. 8-bit timers rev.4.00 aug. 20, 2007 page 251 of 638 rej09b0395-0400 9.2.4 timer control register (8tcr) 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit initial value read/write 8tcr is an 8-bit readable/writable register that selects the 8tcnt input clock, gives the 8tcnt clearing specification, and enables interrupt requests. 8tcr is initialized to h'00 by a reset and in standby mode. for the timing, see section 9.4, operation. bit 7?compare match interrupt enable b (cmieb): enables or disables the cmib interrupt request when the cmfb flag is set to 1 in 8tcsr. bit 7 cmieb description 0 cmib interrupt requested by cmfb is disabled (initial value) 1 cmib interrupt requested by cmfb is enabled bit 6?compare match interrupt enable a (cmiea): enables or disables the cmia interrupt request when the cmfa flag is set to 1 in 8tcsr. bit 6 cmiea description 0 cmia interrupt requested by cmfa is disabled (initial value) 1 cmia interrupt requested by cmfa is enabled bit 5?timer overflow interrupt enable (ovie): enables or disables the ovi interrupt request when the ovf flag is set to 1 in 8tcsr. bit 5 ovie description 0 ovi interrupt requested by ovf is disabled (initial value) 1 ovi interrupt requested by ovf is enabled 9. 8-bit timers rev.4.00 aug. 20, 2007 page 252 of 638 rej09b0395-0400 bits 4 and 3?counter clear 1 and 0 (cclr1, cclr0): these bits specify the 8tcnt clearing source. compare match a or b, or input cap ture b, can be selected as the clearing source. bit 4 cclr1 bit 3 cclr0 description 0 0 clearing is disabled (initial value) 1 cleared by compare match a 1 0 cleared by compare match b/input capture b 1 cleared by input capture b note: when input capture b is set as the 8tcnt1 and 8tcnt3 counter clear source, 8tcnt0 and 8tcnt2 are not cleared by compare match b. bits 2 to 0?clock select 2 to 0 (csk2 to csk0): these bits select whether the clock input to 8tcnt is an internal or external clock. three internal clocks can be selected , all divided from the system clock ( ): /8, /64, and /8192. the rising edge of the selected in ternal clock triggers the count. when use of an external clock is selected, three types of count can be selected: at the rising edge, the falling edge, and both rising and falling edges. when cks2, cks1, cks0 = 1, 0, 0, channels 0 and 1 and channels 2 and 3 are cascaded. the incrementing clock source is different when 8tcr0 and 8tcr2 are set, and when 8tcr1 and 8tcr3 are set. 9. 8-bit timers rev.4.00 aug. 20, 2007 page 253 of 638 rej09b0395-0400 bit 2 csk2 bit 1 csk1 bit 0 csk0 description 0 0 0 clock input disabled (initial value) 1 internal clock, counted on falling edge of /8 1 0 internal clock, counted on falling edge of /64 1 internal clock, counted on falling edge of /8192 1 0 0 channel 0 (16-bit count mode): count on 8tcnt1 overflow signal * 1 channel 1 (compare match count mode): count on 8tcnt0 compare match a * 1 channel 2 (16-bit count mode): count on 8tcnt3 overflow signal * 2 channel 3 (compare match count mode): count on 8tcnt2 compare match a * 2 1 external clock, counted on rising edge 1 0 external clock, counted on falling edge 1 external clock, counted on both rising and falling edges notes: 1. if the clock input of channel 0 is the 8tcnt1 overflow signal and that of channel 1 is the 8tcnt0 compare match signal, no incrementing clock is generated. do not use this setting. 2. if the clock input of channel 2 is the 8tcnt3 overflow signal and that of channel 3 is the 8tcnt2 compare match signal, no incrementing clock is generated. do not use this setting. 9. 8-bit timers rev.4.00 aug. 20, 2007 page 254 of 638 rej09b0395-0400 9.2.5 timer control/status registers (8tcsr) 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 ? 1 ? 3 ois3 0 r/w 0 os0 0 r/w 2 ois2 0 r/w 1 os1 0 r/w 8tcsr2 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 0 r/w 3 ois3 0 r/w 0 os0 0 r/w 2 ois2 0 r/w 1 os1 0 r/w 8tcsr0 adte bit initial value read/write bit initial value read/write 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 ice 0 r/w 3 ois3 0 r/w 0 os0 0 r/w 2 ois2 0 r/w 1 os1 0 r/w 8tcsr1, 8tcsr3 note: * only 0 can be written to bits 7 to 5, to clear these fla g s. bit initial value read/write the timer control/status registers 8tcsr are 8-b it registers that indicate compare match/input capture and overflow statuses, and control compare match output/input capture edge selection. 8tcsr2 is initialized to h'10, and 8tcsr0, 8tcsr1, and 8tcsr3 to h'00, by a reset and in standby mode. 9. 8-bit timers rev.4.00 aug. 20, 2007 page 255 of 638 rej09b0395-0400 bit 7?compare match/input capture flag b (cmfb): status flag th at indicates the occurrence of a tcorb compare match or input capture. bit 7 cmfb description 0 [clearing condition] (initial value) read cmfb when cmfb = 1, then write 0 in cmfb 1 [setting conditions] ? 8tcnt = tcorb * ? the 8tcnt value is transferred to tcorb by an input capture signal when tcorb functions as an input capture register note: * when bit ice is set to 1 in 8tcsr1 and 8tcsr3, the cmfb flag is not set when 8tcnt0 = tcorb0 or 8tcnt2 = tcorb2. bit 6?compare match flag a (cmfa): status flag that indicates the occurrence of a tcora compare match. bit 6 cmfa description 0 [clearing condition] (initial value) read cmfa when cmfa = 1, then write 0 in cmfa 1 [setting condition] 8tcnt = tcora bit 5?timer overflow flag (ovf): status flag that indicates that the 8tcnt has overflowed from h'ff to h'00. bit 5 ovf description 0 [clearing condition] (initial value) read ovf when ovf = 1, then write 0 in ovf 1 [setting condition] 8tcnt overflows from h'ff to h'00 9. 8-bit timers rev.4.00 aug. 20, 2007 page 256 of 638 rej09b0395-0400 bit 4?a/d trigger enable (adte) (in 8tcsr0): in combination with trge in the a/d control register (adcr), enables or disables a/d converter start requests by compare match a or an external trigger. trge * bit 4 adte description 0 0 a/d converter start requests by compare match a or external trigger pin ( adtrg ) input are disabled (initial value) 1 a/d converter start requests by compare match a or external trigger pin ( adtrg ) input are disabled 1 0 a/d converter start requests by external trigger pin ( adtrg ) input are enabled, and a/d converter start requests by compare match a are disabled 1 a/d converter start requests by compare match a are enabled, and a/d converter start requests by external trigger pin ( adtrg ) input are disabled note: * trge is bit 7 of the a/d control register (adcr). bit 4?reserved (in 8tcsr1): this bit is a reserved bit, but can be read and written. bit 4?input capture enable (ice) (in 8tcsr1 and 8tcsr3): selects the function of tcorb1 and tcorb3. bit 4 ice description 0 tcorb1 and tcorb3 are compare match registers (initial value) 1 tcorb1 and tcorb3 are input capture registers when bit ice is set to 1 in 8tcsr1 or 8tcsr3, the operation of the tcora and tcorb registers in channels 0 to 3 is as shown in the tables below. 9. 8-bit timers rev.4.00 aug. 20, 2007 page 257 of 638 rej09b0395-0400 table 9.3 operation of channels 0 and 1 when bit ice is set to 1 in 8tcsr1 register register register function status flag change timer output capture input interrupt request tcora0 compare match operation cmfa changed from 0 to 1 in 8tcsr0 by compare match tmo 0 output controllable cmia0 interrupt request generated by compare match tcorb0 compare match operation cmfb not changed from 0 to 1 in 8tcsr0 by compare match no output from tmo 0 cmib0 interrupt request not generated by compare match tcora1 compare match operation cmfa changed from 0 to 1 in 8tcsr1 by compare match tmio 1 is dedicated input capture pin cmia1 interrupt request generated by compare match tcorb1 input capture operation cmfb changed from 0 to 1 in 8tcsr1 by input capture tmio 1 is dedicated input capture pin cmib1 interrupt request generated by input capture table 9.4 operation of channels 2 and 3 when bit ice is set to 1 in 8tcsr3 register register register function status flag change timer output capture input interrupt request tcora2 compare match operation cmfa changed from 0 to 1 in 8tcsr2 by compare match tmo 2 output controllable cmia2 interrupt request generated by compare match tcorb2 compare match operation cmfb not changed from 0 to 1 in 8tcsr2 by compare match no output from tmo 2 cmib2 interrupt request not generated by compare match tcora3 compare match operation cmfa changed from 0 to 1 in 8tcsr3 by compare match tmio 3 is dedicated input capture pin cmia3 interrupt request generated by compare match tcorb3 input capture operation cmfb changed from 0 to 1 in 8tcsr3 by input capture tmio 3 is dedicated input capture pin cmib3 interrupt request generated by input capture 9. 8-bit timers rev.4.00 aug. 20, 2007 page 258 of 638 rej09b0395-0400 bits 3 and 2?output/input capture edge select b3 and b2 (ois3, ois2): in combination with the ice bit in 8tcsr1 (8tcsr3), these bits select the compare match b output level or the input capture input detected edge. the function of tcorb1 (tcorb3) depends on the setting of bit 4 of 8tcsr1 (8tcsr3). ice bit in 8tcsr1 (8tcsr3) bit 3 ois3 bit 2 ois2 description 0 0 0 no change when compare match b occurs (initial value) 1 0 is output when compare match b occurs 1 0 1 is output when compare match b occurs 1 output is inverted when compare match b occurs (toggle output) 1 0 0 tcorb input capture on rising edge 1 tcorb input capture on falling edge 1 0 tcorb input capture on both rising and falling edges 1 ? when the compare match register function is used, the timer output priority order is: toggle output > 1 output > 0 output. ? if compare match a and b occur simultaneously , the output changes in accordance with the higher-priority compare match. ? when bits ois3, ois2, os1, and os0 are a ll cleared to 0, timer output is disabled. bits 1 and 0?output select a1 and a0 (os1, os0): these bits select the compare match a output level. bit 1 os1 bit 0 os0 description 0 0 no change when compare match a occurs (initial value) 1 0 is output when compare match a occurs 1 0 1 is output when compare match a occurs 1 output is inverted when compare match a occurs (toggle output) ? when the compare match register function is used, the timer output priority order is: toggle output > 1 output > 0 output. ? if compare match a and b occur simultaneously , the output changes in accordance with the higher-priority compare match. ? when bits ois3, ois2, os1, and os0 are a ll cleared to 0, timer output is disabled. 9. 8-bit timers rev.4.00 aug. 20, 2007 page 259 of 638 rej09b0395-0400 9.3 cpu interface 9.3.1 8-bit registers 8tcnt, tcora, tcorb, 8tcr, and 8tcsr are 8-b it registers. these registers are connected to the cpu by an internal 16-bit data bus and can be read and written a word at a time or a byte at a time. figures 9.2 and 9.3 show the operation in word read and write accesses to 8tcnt. figures 9.4 to 9.7 show the operation in byte read and write accesses to 8tcnt0 and 8tcnt1. 8tcnt0 8tcnt1 h l h l c p u internal data bus bus interface module data bus figure 9.2 8tcnt access operation (cpu writes to 8tcnt, word) 8tcnt0 8tcnt1 h l h l c p u internal data bus bus interface module data bus figure 9.3 8tcnt access opera tion (cpu reads 8tcnt, word) 8tcnth0 8tcntl1 h l h l c p u internal data bus bus interface module data bus figure 9.4 8tcnt0 access operation (c pu writes to 8tcnt0, upper byte) 9. 8-bit timers rev.4.00 aug. 20, 2007 page 260 of 638 rej09b0395-0400 8tcnth0 8tcntl1 h l h l c p u internal data bus bus interface module data bus figure 9.5 8tcnt1 access operation (c pu writes to 8tcnt1, lower byte) 8tcnt0 8tcnt1 h l h l c p u internal data bus bus interface module data bus figure 9.6 8tcnt0 access operation (cpu reads 8tcnt0, upper byte) 8tcnt0 8tcnt1 h l h l c p u internal data bus bus interface module data bus figure 9.7 8tcnt1 access operation (cpu reads 8tcnt1, lower byte) 9. 8-bit timers rev.4.00 aug. 20, 2007 page 261 of 638 rej09b0395-0400 9.4 operation 9.4.1 8tcnt count timing 8tcnt is incremented by input clock pulses (either internal or external). internal clock: three different internal clock signals ( /8, /64, or /8192) divided from the system clock ( ) can be selected, by setting bits cks2 to cks0 in 8tcr. figure 9.8 shows the count timing. 8tcnt n ? 1 n n + 1 internal clock 8tcnt input clock note: even if the same internal clock is selected for the 16-bit timer and the 8-bit timer, the same operation will not be performed since the incrementin g ed g e is different in each case. figure 9.8 count timing for internal clock input external clock: three incrementation methods can be selected by setting bits cks2 to cks0 in 8tcr: on the rising edge, the falling e dge, and both rising and falling edges. the pulse width of the external clock signal must be at least 1.5 system clocks when a single edge is selected, and at least 2.5 system clocks when bo th edges are selected. shorter pulses will not be counted correctly. figure 9.9 shows the timing for incrementation on both edges of the external clock signal. 9. 8-bit timers rev.4.00 aug. 20, 2007 page 262 of 638 rej09b0395-0400 8tcnt n ? 1 n n + 1 external clock input 8tcnt input clock figure 9.9 count timing for external clock input (both-edge detection) 9.4.2 compare match timing timer output timing: when compare match a or b occurs, the timer output is as specified by the ois3, ois2, os1, and os0 bits in 8tcsr (unchanged, 0 output, 1 output, or toggle output). figure 9.10 shows the timing when the output is set to toggle on compare match a. compare match a si g nal timer output figure 9.10 timing of timer output 9. 8-bit timers rev.4.00 aug. 20, 2007 page 263 of 638 rej09b0395-0400 clear by compare match: depending on the setting of the cclr1 and cclr0 bits in 8tcr, 8tcnt can be cleared when compare match a or b occurs, figure 9.11 shows the timing of this operation. n h'00 8tcnt compare match si g nal figure 9.11 timing of clear by compare match clear by input capture: depending on the setting of the cclr1 and cclr0 bits in 8tcr, 8tcnt can be cleared when input capture b occurs. figure 9.12 shows the timing of this operation. input capture si g nal input capture input 8tcnt n h'00 figure 9.12 timing of clear by input capture 9.4.3 input capture signal timing input capture on the rising edge, falling edge, or both edges can be selected by settings in 8tcsr. figure 9.13 shows the timing when the rising edge is selected. the pulse width of the input capture input signal must be at least 1.5 system clocks when a single edge is selected, and at least 2.5 system clocks when both edges are selected. 9. 8-bit timers rev.4.00 aug. 20, 2007 page 264 of 638 rej09b0395-0400 input capture si g nal input capture input 8tcnt n tcorb n figure 9.13 timing of input capture input signal 9.4.4 timing of status flag setting timing of cmfa/cmfb flag settin g when compare match occurs: the cmfa and cmfb flags in 8tcsr are set to 1 by the compare match signal output when the tcora or tcorb and 8tcnt values match. the compare match signal is generated in the last state of the match (when the matched 8tcnt count value is updated). therefore, after the 8tcnt and tcora or tcorb values match, the compare match signal is not generated until an incrementing clock pulse signal is generated. figure 9.14 shows the timing in this case. cmf compare match si g nal 8tcnt n n + 1 n tcor figure 9.14 cmf flag setting timing when compare match occurs timing of cmfb flag setting when input capture occurs: on generation of an input capture signal, the cmfb flag is set to 1 and at the same time the 8tcnt value is transferred to tcorb. figure 9.15 shows the timing in this case. 9. 8-bit timers rev.4.00 aug. 20, 2007 page 265 of 638 rej09b0395-0400 cmfb input capture si g nal 8tcnt n n tcorb figure 9.15 cmfb flag setting ti ming when input capture occurs timing of overflow flag (ovf) setting: the ovf flag in 8tcsr is set to 1 by the overflow signal generated when 8tcnt overflows (from h'ff to h'00). figure 9.16 shows the timing in this case. ovf overflow si g nal 8tcnt h'ff h'00 figure 9.16 timing of ovf setting 9.4.5 operation with cascaded connection if bits cks2 to cks0 are set to (100) in either 8tcr0 or 8tcr1, the 8-bit timers of channels 0 and 1 are cascaded. with this configuration, the two timers can be used as a single 16-bit timer (16-bit timer mode), or channel 0 8-bit timer compare matches can be counted in channel 1 (compare match count mode). similarly, if bits cks2 to cks0 are set to (100) in either 8tcr2 or 8tcr3, the 8-bit timers of channels 2 and 3 are cascaded. with this configuration, the two timers can be used as a single 16-bit tim er (16-bit timer mode),or channel 2 8-bit timer compare matches can be counted in channel 3 (compare match coun t mode). in this case, the timer operates as below. 9. 8-bit timers rev.4.00 aug. 20, 2007 page 266 of 638 rej09b0395-0400 16-bit count mode ? channels 0 and 1: when bits cks2 to cks0 are set to (100) in 8tcr0, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. ? setting when compare match occurs ? the cmfa or cmfb flag is set to 1 in 8tcsr0 when a 16-bit compare match occurs. ? the cmfa or cmfb flag is set to 1 in 8tcsr1 when a lower 8-bit compare match occurs. ? tmo 0 pin output control by bits ois3, ois2, os1, and os0 in 8tcsr0 is in accordance with the 16-bit compare match conditions. ? tmio 1 pin output control by bits ois3, ois2, os1, and os0 in 8tcsr1 is in accordance with the lower 8-bit compare match conditions. ? setting when input capture occurs ? the cmfb flag is set to 1 in 8tcsr0 a nd 8tcsr1 when the ice bit is 1 in tcsr1 and input capture occurs. ? tmio 1 pin input capture input signal edge detection is selected by bits ois3 and ois2 in 8tcsr0. ? counter clear specification ? if counter clear on compare match or input capture has been selected by the cclr1 and cclr0 bits in 8tcr0, the 16-bit counter (both 8tcnt0 and 8tcnt1) is cleared. ? the settings of the cclr1 and cclr0 bits in 8tcr1 are ignored. the lower 8 bits cannot be cleared independently. ? ovf flag operation ? the ovf flag is set to 1 in 8tcsr0 when the 16-bit counter (8tcnt0 and 8tcnt1) overflows (from h' ffff to h'0000). ? the ovf flag is set to 1 in 8tcsr1 when the 8-bit counter (8tcnt1) overflows (from h'ff to h'00). ? channels 2 and 3: when bits cks2 to cks0 are set to (100) in 8tcr2, the timer functions as a single 16-bit timer with channel 2 occupying the upper 8 bits and channel 3 occupying the lower 8 bits. ? setting when compare match occurs ? the cmfa or cmfb flag is set to 1 in 8tcsr2 when a 16-bit compare match occurs. ? the cmfa or cmfb flag is set to 1 in 8tcsr3 when a lower 8-bit compare match occurs. ? tmo 2 pin output control by bits ois3, ois2, os1, and os0 in 8tcsr2 is in accordance with the 16-bit compare match conditions. 9. 8-bit timers rev.4.00 aug. 20, 2007 page 267 of 638 rej09b0395-0400 ? tmio 3 pin output control by bits ois3, ois2, os1, and os0 in 8tcsr3 is in accordance with the lower 8-bit compare match conditions. ? setting when input capture occurs ? the cmfb flag is set to 1 in 8tcsr2 a nd 8tcsr3 when the ice bit is 1 in tcsr3 and input capture occurs. ? tmio 3 pin input capture input signal edge detection is selected by bits ois3 and ois2 in 8tcsr2. ? counter clear specification ? if counter clear on compare match has been selected by the cclr1 and cclr0 bits in 8tcr2, the 16-bit counter (both 8tcnt2 and 8tcnt3) is cleared. ? the settings of the cclr1 and cclr0 bits in 8tcr3 are ignored. the lower 8 bits cannot be cleared independently. ? ovf flag operation ? the ovf flag is set to 1 in 8tcsr2 when the 16-bit counter (8tcnt2 and 8tcnt3) overflows (from h' ffff to h'0000). ? the ovf flag is set to 1 in 8tcsr3 when the 8-bit counter (8tcnt3) overflows (from h'ff to h'00). compare match count mode ? channels 0 and 1: when bits cks2 to cks0 are set to (100) in 8tcr1, 8tcnt1 counts channel 0 compare match a events. channels 0 and 1 are controlled independently. cmf flag setting, interrupt generation, tmo pin output, counter clearing, and so on, is in accordance with the settings for each channel. note: when bit ice = 1 in 8tcsr1, the compare match register function of tcorb0 in channel 0 cannot be used. ? channels 2 and 3: when bits cks2 to cks0 are set to (100) in 8tcr3, 8tcnt3 counts channel 2 compare match a events. channels 2 and 3 are controlled independently. cmf flag setting, interrupt generation, tmo pin output, counter clearing, and so on, is in accordance with the settings for each channel. note: when bit ice = 1 in 8tcsr3, the compare match register function of tcorb2 in channel 2 cannot be used. 9. 8-bit timers rev.4.00 aug. 20, 2007 page 268 of 638 rej09b0395-0400 caution do not set 16-bit counter mode and compare match count mode simultaneously within the same group, as the 8tcnt input clock will not be generated and the counters will not operate. 9.4.6 input capture setting the 8tcnt value can be transferred to tcorb on detection of an input edge on the input capture/output compare pin (tmio 1 or tmio 3 ). rising edge, falling edge , or both edge detection can be selected. in 16-bit count mode , 16-bit input capture can be used. setting input capture operation in 8-bit timer mode (normal operation) ? channel 1: ? set tcorb1 as an 8-bit input capture register with the ice bit in 8tcsr1. ? select rising edge, falling edge, or both edges as the input edge(s) for the input capture signal (tmio 1 ) with bits ois3 and ois2 in 8tcsr1. ? select the input clock with bits cks2 to cks0 in 8tcr1, and start the 8tcnt count. ? channel 3: ? set tcorb3 as an 8-bit input capture register with the ice bit in 8tcsr3. ? select rising edge, falling edge, or both edges as the input edge(s) for the input capture signal (tmio 3 ) with bits ois3 and ois2 in 8tcsr3. ? select the input clock with bits cks2 to cks0 in 8tcr3, and start the 8tcnt count. note: when tcorb1 in channel 1 is used for input capture, tcorb0 in channel 0 cannot be used as a compare match register. similarly, when tcorb3 in channel 3 is used for input capture, tcorb2 in channel 2 cannot be used as a compare match register. setting input capture operation in 16-bit count mode ? channels 0 and 1: ? in 16-bit count mode, tcorb0 and tcorb1 function as a 16-bit input capture register when the ice bit is set to 1 in 8tcsr1. ? select rising edge, falling edge, or both edges as the input edge(s) for the input capture signal (tmio 1 ) with bits ois3 and ois2 in 8tcsr0. (in 16-bit count mode, the settings of bits ois3 and ois2 in 8tcsr1 are ignored.) ? select the input clock with bits cks2 to cks0 in 8tcr1, and start the 8tcnt count. ? channels 2 and 3: ? in 16-bit count mode, tcorb2 and tcorb3 function as a 16-bit input capture register when the ice bit is set to 1 in 8tcsr3. 9. 8-bit timers rev.4.00 aug. 20, 2007 page 269 of 638 rej09b0395-0400 ? select rising edge, falling edge, or both edges as the input edge(s) for the input capture signal (tmio 3 ) with bits ois3 and ois2 in 8tcsr2. (in 16-bit count mode, the settings of bits ois3 and ois2 in 8tcsr3 are ignored.) ? select the input clock with bits cks2 to cks0 in 8tcr3, and start the 8tcnt count. 9.5 interrupt 9.5.1 interrupt sources the 8-bit timer unit can generate three types of interrupt: compare match a and b (cmia and cmib) and overflow (tovi). table 9.5 shows the interrupt sources and their priority order. each interrupt source is enabled or disabled by the corresponding interrupt enable bit in 8tcr. a separate interrupt request signal is sent to the interrupt controller by each interrupt source. table 9.5 types of 8-bit timer int errupt sources and priority order interrupt source description priority cmia interrupt by cmfa high cmib interrupt by cmfb tovi interrupt by ovf low for compare match interrupts cmia1/cmib1 and cmia3/cmib3 and the overflow interrupts (tovi0/tovi1 and tovi2/tovi3), one vector is shared by two interrupts. table 9.6 lists the interrupt sources. 9. 8-bit timers rev.4.00 aug. 20, 2007 page 270 of 638 rej09b0395-0400 table 9.6 8-bit timer interrupt sources channel interrupt source description 0 cmia0 tcora0 compare match cmib0 tcorb0 compare match/input capture 1 cmia1/cmib1 tcora1 compare match, or tcorb1 compare match/input capture 0, 1 tovi0/tovi1 counter 0 or counter 1 overflow 2 cmia2 tcora2 compare match cmib2 tcorb2 compare match/input capture 3 cmia3/cmib3 tcora3 compare match, or tcorb3 compare match/input capture 2, 3 tovi2/tovi3 counter 2 or counter 3 overflow 9.5.2 a/d converter activation the a/d converter can only be activated by channel 0 compare match a. if the adte bit setting is 1 when the cmfa flag in 8tcsr0 is set to 1 by generation of channel 0 compare match a, an a/d conversion start request will be issued to the a/d converter. if the trge bit in adcr is 1 at this time, the a/d converter will be started. if the adte bit in 8tcsr0 is 1, a/d converter external trigger pin ( adtrg ) input is disabled. 9. 8-bit timers rev.4.00 aug. 20, 2007 page 271 of 638 rej09b0395-0400 9.6 8-bit timer application example figure 9.17 shows how the 8-bit timer module can be used to output pulses with any desired duty cycle. the settings for this example are as follows: ? clear the cclr1 bit to 0 and set the cclr0 bit to 1 in 8tcr so that 8tcnt is cleared by a tcora compare match. ? set bits ois3, ois2, os1, and os0 to (0110) in 8tcsr so that 1 is output on a tcora compare match and 0 is output on a tcorb compare match. the above settings enable a wave form with the cycle determined by tcora and the pulse width detected by tcorb to be output without software intervention. 8tcnt h'ff counter clear tcora tcorb h'00 tmo figure 9.17 example of pulse output 9. 8-bit timers rev.4.00 aug. 20, 2007 page 272 of 638 rej09b0395-0400 9.7 usage notes note that the following kinds of contention can occur in 8-bit timer operation. 9.7.1 contention between 8tcnt write and clear if a timer counter clear signal occurs in the t 3 state of a 8tcnt write cycle, clearing of the counter takes priority and the write is not performed. figure 9.18 shows the timing in this case. address bus 8tcnt address internal write si g nal counter clear si g nal 8tcnt n h'00 t 1 t 3 t 2 8tcnt write cycle figure 9.18 contention between 8tcnt write and clear 9. 8-bit timers rev.4.00 aug. 20, 2007 page 273 of 638 rej09b0395-0400 9.7.2 contention between 8tcnt write and increment if an increment puls e occurs in the t 3 state of a 8tcnt write cycle, writing takes priority and 8tcnt is not incremented. figure 9.19 shows the timing in this case. address bus 8 tcnt address internal write si g nal 8tcnt input clock 8tcnt nm t 1 t 3 t 2 8tcnt write cycle 8tcnt write data figure 9.19 contention betw een 8tcnt write and increment 9. 8-bit timers rev.4.00 aug. 20, 2007 page 274 of 638 rej09b0395-0400 9.7.3 contention between tc or write and compare match if a compare match occurs in the t 3 state of a tcor write cycle, writing takes priority and the compare match signal is inhibited. figure 9.20 shows the timing in this case. address bus tcor address internal write si g nal 8tcnt tcor nm t 1 t 3 t 2 tcor write cycle tcor write data n n + 1 compare match si g nal inhibited figure 9.20 contention between tcor write and compare match 9. 8-bit timers rev.4.00 aug. 20, 2007 page 275 of 638 rej09b0395-0400 9.7.4 contention between tcor read and input capture if an input capture signal occurs in the t 3 state of a tcor read cycle, the value before input capture is read. figure 9.21 shows the timing in this case. address bus tcorb address internal read si g nal input capture si g nal tcorb nm t 1 t 3 t 2 tcorb read cycle internal data bus n figure 9.21 contention between tcor read and input capture 9. 8-bit timers rev.4.00 aug. 20, 2007 page 276 of 638 rej09b0395-0400 9.7.5 contention between counter cleari ng by input capture and counter increment if an input capture signal and counter increment signal occur simultaneously, counter clearing by the input capture signal takes priority and the counter is not incremented. the value before the counter is cleared is transferred to tcorb. figure 9.22 shows the timing in this case. counter clear si g nal 8tcnt internal clock 8tcnt n x h'00 input capture si g nal tcorb n figure 9.22 contention between counter clearing by input capture and counter increment 9. 8-bit timers rev.4.00 aug. 20, 2007 page 277 of 638 rej09b0395-0400 9.7.6 contention between tcor write and input capture if an input capture signal occurs in the t 3 state of a tcor write cycle, input capture takes priority and the write to tcor is not performed. figure 9.23 shows the timing in this case. address bus tcor address internal write si g nal input capture si g nal 8tcnt m t 1 t 3 t 2 tcor write cycle tcor m x figure 9.23 contention between tcor write and input capture 9. 8-bit timers rev.4.00 aug. 20, 2007 page 278 of 638 rej09b0395-0400 9.7.7 contention between 8tcnt byte wr ite and increment in 16-bit count mode (cascaded connection) if an increment puls e occurs in the t 2 or t 3 state of an 8tcnt byte write cycle in 16-bit count mode, the counter write takes priority and the byte data for which the write was performed is not incremented. the byte data for which a write was not performed is incremented. figure 9.24 shows the timing when an incr ement pulse occurs in the t 2 state of a byte write to 8tcnt (upper byte). if an increment pulse occurs in the t 2 state, on the other hand, the increment takes priority. address bus 8tcnth address internal write si g nal 8tcnt input clock 8tcnt (upper byte) n 8tcnt write data t 1 t 3 t 2 8tcnt (upper byte) byte write cycle 8tcnt (lower byte) x + 1 n + 1 x figure 9.24 contention betw een 8tcnt byte write and increment in 16-bit count mode 9. 8-bit timers rev.4.00 aug. 20, 2007 page 279 of 638 rej09b0395-0400 9.7.8 contention between compare matches a and b if compare matches a and b occur at the same time, the 8-bit timer operates according to the relative priority of the output states set for co mpare match a and compare match b, as shown in table 9.7. table 9.7 timer output priority order output setting priority toggle output high 1 output 0 output no change low 9.7.9 8tcnt operation and int ernal clock source switchover switching internal clock sources may cause 8tcnt to increment, depending on the switchover timing. table 9.8 shows the relation between the time of the switchover (by writing to bits cks1 and cks0) and the operation of 8tcnt. the 8tcnt input clock is generated from the internal clock source by detecting the rising edge of the internal clock. if a switchover is made from a low clock source to a high clock source, as in case no. 3 in table 9.8, the switchover will be re garded as a falling edge, a 8tcnt clock pulse will be generated, and 8tcnt will be incremented. 8tcnt may also be incremented when switchi ng between internal and external clocks. 9. 8-bit timers rev.4.00 aug. 20, 2007 page 280 of 638 rej09b0395-0400 table 9.8 internal clock switchover and 8tcnt operation no. cks1 and cks0 write timing 8tcnt operation 1 high high switchover * 1 old clock source new clock source 8tcnt clock 8tcnt cks bits rewritten n n + 1 2 high low switchover * 2 old clock source new clock source 8tcnt clock 8tcnt cks bits rewritten n n + 1 n + 2 3 low high switchover * 3 old clock source new clock source 8tcnt clock 8tcnt cks bits rewritten n n + 1 n + 2 * 4 9. 8-bit timers rev.4.00 aug. 20, 2007 page 281 of 638 rej09b0395-0400 no. cks1 and cks0 write timing 8tcnt operation 4 low low switchover * 4 old clock source new clock source 8tcnt clock 8tcnt cks bits rewritten n n + 1 n + 2 notes: 1. including switchovers from the high leve l to the halted state, and from the halted state to the high level. 2. including switchover from the halted state to the low level. 3. including switchover from the low level to the halted state. 4. the switchover is regarded as a rising edge, causing 8tcnt to increment. 9. 8-bit timers rev.4.00 aug. 20, 2007 page 282 of 638 rej09b0395-0400 10. programmable timing pattern controller (tpc) rev.4.00 aug. 20, 2007 page 283 of 638 rej09b0395-0400 section 10 programmable timing pattern controller (tpc) 10.1 overview the h8/3008 has a built-in programmable timing pattern controller (tpc) that provides pulse outputs by using the 16-bit timer as a time base. the tpc pulse outputs are divided into 4-bit groups (group 3 to group 0) that can operate simultaneously and independently. 10.1.1 features tpc features are listed below. ? 16-bit output data maximum 16-bit data can be output. tpc output can be enabled on a bit-by-bit basis. ? four output groups output trigger signals can be selected in 4-bit groups to provide up to four different 4-bit outputs. ? selectable output trigger signals output trigger signals can be selected for each group from the compare match signals of three 16-bit timer channels. ? non-overlap mode a non-overlap margin can be provided between pulse outputs. 10. programmable timing pattern controller (tpc) rev.4.00 aug. 20, 2007 page 284 of 638 rej09b0395-0400 10.1.2 block diagram figure 10.1 shows a block diagram of the tpc. pa d d r ndera tpmr pbddr nderb tpcr internal data bus tp tp tp tp tp tp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 control lo g ic 16-bit timer compare match si g nals pulse output pins, g roup 3 pbdr pa d r le g end: tpmr: tpcr: nderb: ndera: pbddr: paddr: ndrb: ndra: pbdr: padr: pulse output pins, g roup 2 pulse output pins, g roup 1 pulse output pins, g roup 0 tpc output mode re g ister tpc output control re g ister next data enable re g ister b next data enable re g ister a port b data direction re g ister port a data direction re g ister next data re g ister b next data re g ister a port b data re g ister port a data re g ister ndrb ndra tp tp tp tp tp tp tp tp tp tp figure 10.1 tpc block diagram 10. programmable timing pattern controller (tpc) rev.4.00 aug. 20, 2007 page 285 of 638 rej09b0395-0400 10.1.3 pin configuration table 10.1 summarizes the tpc output pins. table 10.1 tpc pins name symbol i/o function tpc output 0 tp 0 output group 0 pulse output tpc output 1 tp 1 output tpc output 2 tp 2 output tpc output 3 tp 3 output tpc output 4 tp 4 output group 1 pulse output tpc output 5 tp 5 output tpc output 6 tp 6 output tpc output 7 tp 7 output tpc output 8 tp 8 output group 2 pulse output tpc output 9 tp 9 output tpc output 10 tp 10 output tpc output 11 tp 11 output tpc output 12 tp 12 output group 3 pulse output tpc output 13 tp 13 output tpc output 14 tp 14 output tpc output 15 tp 15 output 10. programmable timing pattern controller (tpc) rev.4.00 aug. 20, 2007 page 286 of 638 rej09b0395-0400 10.1.4 register configuration table 10.2 summarizes the tpc registers. table 10.2 tpc registers address * 1 name abbreviation r/w initial value h'ee009 port a data direction register paddr w h'00 h'fffd9 port a data register padr r/(w) * 2 h'00 h'ee00a port b data direction register pbddr w h'00 h'fffda port b data register pbdr r/(w) * 2 h'00 h'fffa0 tpc output mode register tpmr r/w h'f0 h'fffa1 tpc output control register tpcr r/w h'ff h'fffa2 next data enable register b nderb r/w h'00 h'fffa3 next data enable register a ndera r/w h'00 h'fffa5/ h'fffa7 * 3 next data register a ndra r/w h'00 h'fffa4/ h'fffa6 * 3 next data register b ndrb r/w h'00 notes: 1. lower 20 bits of the address in advanced mode. 2. bits used for tpc output cannot be written. 3. the ndra address is h'fffa5 when the same output trigger is selected for tpc output groups 0 and 1 by settings in tpcr. when the output triggers are different, the ndra address is h'fffa7 for group 0 and h'fffa5 for group 1. similarly, the address of ndrb is h'fffa4 when the same output trigger is selected for tpc output groups 2 and 3 by settings in tpcr. when the output triggers are different, the ndrb address is h'fffa6 for group 2 and h'fffa4 for group 3. 10. programmable timing pattern controller (tpc) rev.4.00 aug. 20, 2007 page 287 of 638 rej09b0395-0400 10.2 register descriptions 10.2.1 port a data di rection register (paddr) paddr is an 8-bit write-only register that se lects input or output for each pin in port a. bit initial value read/write 7 pa ddr 0 w port a data dire c tion 7 to 0 these bits select input or output for port a pins 7 6 pa ddr 0 w 6 5 pa ddr 0 w 5 4 pa ddr 0 w 4 3 pa ddr 0 w 3 2 pa ddr 0 w 2 1 pa ddr 0 w 1 0 pa ddr 0 w 0 port a is multiplexed with pins tp 7 to tp 0 . bits corresponding to pins used for tpc output must be set to 1. for further information about paddr, see section 7.11, port a. 10.2.2 port a data register (padr) padr is an 8-bit readable/writable register that stores tpc output data for groups 0 and 1, when these tpc output groups are used. bit initial value read/write 0 pa 0 r/(w) 0 1 pa 0 r/(w) 1 2 pa 0 r/(w) 2 3 pa 0 r/(w) 3 4 pa 0 r/(w) 4 5 pa 0 r/(w) 5 6 pa 0 r/(w) 6 7 pa 0 r/(w) 7 port a data 7 to 0 these bits store output data for tpc output g roups 0 and 1 ******** note: bits selected for tpc output by ndera settin g s become read-only bits. * for further information about padr, see section 7.11, port a. 10. programmable timing pattern controller (tpc) rev.4.00 aug. 20, 2007 page 288 of 638 rej09b0395-0400 10.2.3 port b data di rection register (pbddr) pbddr is an 8-bit write-only register that se lects input or output for each pin in port b. bit initial value read/write 7 pb ddr 0 w port b data dire c tion 7 to 0 these bits select input or output for port b pins 7 6 pb ddr 0 w 6 5 pb ddr 0 w 5 4 pb ddr 0 w 4 3 pb ddr 0 w 3 2 pb ddr 0 w 2 1 pb ddr 0 w 1 0 pb ddr 0 w 0 port b is multiplexed with pins tp 15 to tp 8 . bits corresponding to pins used for tpc output must be set to 1. for further information about pbddr, see section 7.12, port b. 10.2.4 port b data register (pbdr) pbdr is an 8-bit readable/writable register that stores tpc output data for groups 2 and 3, when these tpc output groups are used. bit initial value read/write 0 pb 0 r/(w) 0 1 pb 0 r/(w) 1 2 pb 0 r/(w) 2 3 pb 0 r/(w) 3 4 pb 0 r/(w) 4 5 pb 0 r/(w) 5 6 pb 0 r/(w) 6 7 pb 0 r/(w) 7 port b data 7 to 0 these bits store output data for tpc output g roups 2 and 3 ******** note: bits selected for tpc output by nderb settin g s become read-only bits. * for further information about pbdr, see section 7.12, port b. 10. programmable timing pattern controller (tpc) rev.4.00 aug. 20, 2007 page 289 of 638 rej09b0395-0400 10.2.5 next data register a (ndra) ndra is an 8-bit readable/writable register that stores the next output data for tpc output groups 1 and 0 (pins tp 7 to tp 0 ). during tpc output, when an 16-bit timer compare match event specified in tpcr occurs, ndra contents are transferred to the corresponding bits in padr. the address of ndra differs depending on whether tpc output groups 0 and 1 have the same output trigger or different output triggers. ndra is initialized to h'00 by a reset and in ha rdware standby mode. it is not initialized in software standby mode. same trigger for tpc output groups 0 and 1: if tpc output groups 0 and 1 are triggered by the same compare match event, the ndra address is h'fffa5. the upper 4 bits belong to group 1 and the lower 4 bits to group 0. address h'fffa7 consists entirely of reserved bits that cannot be modified and always read 1. address h'fffa5 bit initial value read/write 0 ndr0 0 r/w 1 ndr1 0 r/w 2 ndr2 0 r/w 3 ndr3 0 r/w 4 ndr4 0 r/w 5 ndr5 0 r/w 6 ndr6 0 r/w 7 ndr7 0 r/w next data 7 to 4 these bits store the next output data for tpc output g roup 1 next data 3 to 0 these bits store the next output data for tpc output g roup 0 address h'fffa7 bit initial value read/write 0 ? 1 ? 1 ? 1 ? 2 ? 1 ? 3 ? 1 ? 4 ? 1 ? 5 ? 1 ? 6 ? 1 ? 7 ? 1 ? reserved bits 10. programmable timing pattern controller (tpc) rev.4.00 aug. 20, 2007 page 290 of 638 rej09b0395-0400 different triggers for tpc output groups 0 and 1: if tpc output groups 0 and 1 are triggered by different compare match events, the address of the upper 4 bits of ndra (group 1) is h'fffa5 and the address of the lower 4 bits (group 0) is h'fffa7. bits 3 to 0 of address h'fffa5 and bits 7 to 4 of address h'fffa7 are reserved bits th at cannot be modified and always read 1. address h'fffa5 bit initial value read/write 0 ? 1 ? 1 ? 1 ? 2 ? 1 ? 3 ? 1 ? 4 ndr4 0 r/w 5 ndr5 0 r/w 6 ndr6 0 r/w 7 ndr7 0 r/w next data 7 to 4 these bits store the next output data for tpc output g roup 1 reserved bits address h'fffa7 bit initial value read/write 0 ndr0 0 r/w 1 ndr1 0 r/w 2 ndr2 0 r/w 3 ndr3 0 r/w 4 ? 1 ? 5 ? 1 ? 6 ? 1 ? 7 ? 1 ? reserved bits next data 3 to 0 these bits store the next output data for tpc output g roup 0 10. programmable timing pattern controller (tpc) rev.4.00 aug. 20, 2007 page 291 of 638 rej09b0395-0400 10.2.6 next data register b (ndrb) ndrb is an 8-bit readable/writable register that stores the next output data for tpc output groups 3 and 2 (pins tp 15 to tp 8 ). during tpc output, when an 16-bit timer compare match event specified in tpcr occurs, ndrb c ontents are transferred to the co rresponding bits in pbdr. the address of ndrb differs depending on whether tpc output groups 2 and 3 have the same output trigger or different output triggers. ndrb is initialized to h'00 by a reset and in ha rdware standby mode. it is not initialized in software standby mode. same trigger for tpc output groups 2 and 3: if tpc output groups 2 and 3 are triggered by the same compare match event, the ndrb address is h'fffa4. the upper 4 bits belong to group 3 and the lower 4 bits to group 2. address h'fffa6 consists entirely of reserved bits that cannot be modified and always read 1. address h'fffa4 bit initial value read/write 0 ndr8 0 r/w 1 ndr9 0 r/w 2 ndr10 0 r/w 3 ndr11 0 r/w 4 ndr12 0 r/w 5 ndr13 0 r/w 6 ndr14 0 r/w 7 ndr15 0 r/w next data 15 to 12 these bits store the next output data for tpc output g roup 3 next data 11 to 8 these bits store the next output data for tpc output g roup 2 address h'fffa6 bit initial value read/write 0 ? 1 ? 1 ? 1 ? 2 ? 1 ? 3 ? 1 ? 4 ? 1 ? 5 ? 1 ? 6 ? 1 ? 7 ? 1 ? reserved bits 10. programmable timing pattern controller (tpc) rev.4.00 aug. 20, 2007 page 292 of 638 rej09b0395-0400 different triggers for tpc output groups 2 and 3: if tpc output groups 2 and 3 are triggered by different compare match events, the address of the upper 4 bits of ndrb (group 3) is h'fffa4 and the address of the lower 4 bits (group 2) is h'fffa6. bits 3 to 0 of address h'fffa4 and bits 7 to 4 of address h'fffa6 are reserved bits th at cannot be modified and always read 1. address h'fffa4 bit initial value read/write 0 ? 1 ? 1 ? 1 ? 2 ? 1 ? 3 ? 1 ? 4 ndr12 0 r/w 5 ndr13 0 r/w 6 ndr14 0 r/w 7 ndr15 0 r/w next data 15 to 12 these bits store the next output data for tpc output g roup 3 reserved bits address h'fffa6 bit initial value read/write 0 ndr8 0 r/w 1 ndr9 0 r/w 2 ndr10 0 r/w 3 ndr11 0 r/w 4 ? 1 ? 5 ? 1 ? 6 ? 1 ? 7 ? 1 ? reserved bits next data 11 to 8 these bits store the next output data for tpc output g roup 2 10. programmable timing pattern controller (tpc) rev.4.00 aug. 20, 2007 page 293 of 638 rej09b0395-0400 10.2.7 next data enable register a (ndera) ndera is an 8-bit readable/writable register that enables or disables tpc output groups 1 and 0 (tp 7 to tp 0 ) on a bit-by-bit basis. bit initial value read/write 0 nder0 0 r/w 1 nder1 0 r/w 2 nder2 0 r/w 3 nder3 0 r/w 4 nder4 0 r/w 5 nder5 0 r/w 6 nder6 0 r/w 7 nder7 0 r/w next data enable 7 to 0 these bits enable or disable tpc output g roups 1 and 0 if a bit is enabled for tpc output by ndera, then when the 16-bit timer compare match event selected in the tpc output cont rol register (tpcr) occurs, th e ndra value is automatically transferred to the corresponding padr bit, updating the output value. if tpc output is disabled, the bit value is not transferred from ndra to padr and the output value does not change. ndera is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 0?next data enable 7 to 0 (nder7 to nder0): these bits enable or disable tpc output groups 1 and 0 (tp 7 to tp 0 ) on a bit-by-bit basis. bits 7 to 0 nder7 to nder0 description 0 tpc outputs tp 7 to tp 0 are disabled (ndr7 to ndr0 are not transferred to pa 7 to pa 0 ) (initial value) 1 tpc outputs tp 7 to tp 0 are enabled (ndr7 to ndr0 are transferred to pa 7 to pa 0 ) 10. programmable timing pattern controller (tpc) rev.4.00 aug. 20, 2007 page 294 of 638 rej09b0395-0400 10.2.8 next data enable register b (nderb) nderb is an 8-bit readable/writable register that enables or disables tpc output groups 3 and 2 (tp 15 to tp 8 ) on a bit-by-bit basis. bit initial value read/write 0 nder8 0 r/w 1 nder9 0 r/w 2 nder10 0 r/w 3 nder11 0 r/w 4 nder12 0 r/w 5 nder13 0 r/w 6 nder14 0 r/w 7 nder15 0 r/w next data enable 15 to 8 these bits enable or disable tpc output g roups 3 and 2 if a bit is enabled for tpc output by nderb, then when the 16-bit timer compare match event selected in the tpc output cont rol register (tpcr) occurs, th e ndrb value is automatically transferred to the corresponding pbdr bit, updating the output value. if tpc output is disabled, the bit value is not transferred from ndrb to pbdr and the output value does not change. nderb is initialized to h'00 by a reset and in ha rdware standby mode. it is not initialized in software standby mode. bits 7 to 0?next data enable 15 to 8 (nder15 to nder8): these bits enable or disable tpc output groups 3 and 2 (tp 15 to tp 8 ) on a bit-by-bit basis. bits 7 to 0 nder15 to nder 8 description 0 tpc outputs tp 15 to tp 8 are disabled (ndr15 to ndr8 are not transferred to pb 7 to pb 0 ) (initial value) 1 tpc outputs tp 15 to tp 8 are enabled (ndr15 to ndr8 are transferred to pb 7 to pb 0 ) 10. programmable timing pattern controller (tpc) rev.4.00 aug. 20, 2007 page 295 of 638 rej09b0395-0400 10.2.9 tpc output control register (tpcr) tpcr is an 8-bit readable/writable register that selects output trigger signals for tpc outputs on a group-by-group basis. bit initial value read/write 0 g0cms0 1 r/w 1 g0cms1 1 r/w 2 g1cms0 1 r/w 3 g1cms1 1 r/w 4 g2cms0 1 r/w 5 g2cms1 1 r/w 6 g3cms0 1 r/w 7 g3cms1 1 r/w group 3 c ompare mat c h sele c t 1 and 0 these bits select the compare match event that tri gg ers tpc output g roup 3 (tp 15 to tp 12 ) group 2 c ompare mat c h sele c t 1 and 0 these bits select the compare match event that tri gg ers tpc output g roup 2 (tp 11 to tp 8 ) group 1 c ompare mat c h sele c t 1 and 0 these bits select the compare match event that tri gg ers tpc output g roup 1 (tp 7 to tp 4 ) group 0 c ompare mat c h sele c t 1 and 0 these bits select the compare match event that tri gg ers tpc output g roup 0 (tp 3 to tp 0 ) tpcr is initialized to h'ff by a reset and in hardware standby mode. it is not initialized in software standby mode. 10. programmable timing pattern controller (tpc) rev.4.00 aug. 20, 2007 page 296 of 638 rej09b0395-0400 bits 7 and 6?group 3 compare match select 1 and 0 (g3cms1, g3cms0): these bits select the compare match event that triggers tpc output group 3 (tp 15 to tp 12 ). bit 7 g 3cms1 bit 6 g 3cms0 description 0 0 tpc output group 3 (tp 15 to tp 12 ) is triggered by compare match in 16-bit timer channel 0 1 tpc output group 3 (tp 15 to tp 12 ) is triggered by compare match in 16-bit timer channel 1 1 0 tpc output group 3 (tp 15 to tp 12 ) is triggered by compare match in 16-bit timer channel 2 1 tpc output group 3 (tp 15 to tp 12 ) is triggered by compare match in 16-bit timer channel 2 (initial value) bits 5 and 4?group 2 compare match select 1 and 0 (g2cms1, g2cms0): these bits select the compare match event that triggers tpc output group 2 (tp 11 to tp 8 ). bit 5 g 2cms1 bit 4 g 2cms0 description 0 0 tpc output group 2 (tp 11 to tp 8 ) is triggered by compare match in 16-bit timer channel 0 1 tpc output group 2 (tp 11 to tp 8 ) is triggered by compare match in 16-bit timer channel 1 1 0 tpc output group 2 (tp 11 to tp 8 ) is triggered by compare match in 16-bit timer channel 2 1 tpc output group 2 (tp 11 to tp 8 ) is triggered by compare match in 16-bit timer channel 2 (initial value) 10. programmable timing pattern controller (tpc) rev.4.00 aug. 20, 2007 page 297 of 638 rej09b0395-0400 bits 3 and 2?group 1 compare match select 1 and 0 (g1cms1, g1cms0): these bits select the compare match event that triggers tpc output group 1 (tp 7 to tp 4 ). bit 3 g 1cms1 bit 2 g 1cms0 description 0 0 tpc output group 1 (tp 7 to tp 4 ) is triggered by compare match in 16-bit timer channel 0 1 tpc output group 1 (tp 7 to tp 4 ) is triggered by compare match in 16-bit timer channel 1 1 0 tpc output group 1 (tp 7 to tp 4 ) is triggered by compare match in 16-bit timer channel 2 1 tpc output group 1 (tp 7 to tp 4 ) is triggered by compare match in 16-bit timer channel 2 (initial value) bits 1 and 0?group 0 compare match select 1 and 0 (g0cms1, g0cms0): these bits select the compare match event that triggers tpc output group 0 (tp 3 to tp 0 ). bit 1 g 0cms1 bit 0 g 0cms0 description 0 0 tpc output group 0 (tp 3 to tp 0 ) is triggered by compare match in 16-bit timer channel 0 1 tpc output group 0 (tp 3 to tp 0 ) is triggered by compare match in 16-bit timer channel 1 1 0 tpc output group 0 (tp 3 to tp 0 ) is triggered by compare match in 16-bit timer channel 2 1 tpc output group 0 (tp 3 to tp 0 ) is triggered by compare match in 16-bit timer channel 2 (initial value) 10. programmable timing pattern controller (tpc) rev.4.00 aug. 20, 2007 page 298 of 638 rej09b0395-0400 10.2.10 tpc output mode register (tpmr) tpmr is an 8-bit readable/writable register that selects normal or non-overlapping tpc output for each group. bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 g3nov 0 r/w 0 g0nov 0 r/w 2 g2nov 0 r/w 1 g1nov 0 r/w group 3 non-overlap selects non-overlappin g tpc output for g roup 3 (tp to tp ) reserved bits group 2 non-overlap selects non-overlappin g tpc output for g roup 2 (tp to tp ) group 1 non-overlap selects non-overlappin g tpc output for g roup 1 (tp to tp ) group 0 non-overlap selects non-overlappin g tpc output for g roup 0 (tp to tp ) 15 12 11 8 74 30 the output trigger period of a non-overlapping tpc output waveform is set in general register b (grb) in the 16-bit timer channel selected for output triggering. the non-overlap margin is set in general register a (gra). the output values change at compare match a and b. for details see section 10.3.4, non-overlapping tpc output. tpmr is initialized to h'f0 by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 4?reserved: these bits cannot be modified and are always read as 1. 10. programmable timing pattern controller (tpc) rev.4.00 aug. 20, 2007 page 299 of 638 rej09b0395-0400 bit 3?group 3 non-overlap (g3nov): selects normal or non-overlapping tpc output for group 3 (tp 15 to tp 12 ). bit 3 g 3nov description 0 normal tpc output in group 3 (output values change at compare match a in the selected 16-bit timer channel) (initial value) 1 non-overlapping tpc output in group 3 (independent 1 and 0 output at compare match a and b in the selected 16-bit timer channel) bit 2?group 2 non-overlap (g2nov): selects normal or non-overlapping tpc output for group 2 (tp 11 to tp 8 ). bit 2 g 2nov description 0 normal tpc output in group 2 (output values change at compare match a in the selected 16-bit timer channel) (initial value) 1 non-overlapping tpc output in group 2 (independent 1 and 0 output at compare match a and b in the selected 16-bit timer channel) bit 1?group 1 non-overlap (g1nov): selects normal or non-overlapping tpc output for group 1 (tp 7 to tp 4 ). bit 1 g 1nov description 0 normal tpc output in group 1 (output values change at compare match a in the selected 16-bit timer channel) (initial value) 1 non-overlapping tpc output in group 1 (independent 1 and 0 output at compare match a and b in the selected 16-bit timer channel) bit 0?group 0 non-overlap (g0nov): selects normal or non-overlapping tpc output for group 0 (tp 3 to tp 0 ). bit 0 g 0nov description 0 normal tpc output in group 0 (output values change at compare match a in the selected 16-bit timer channel) (initial value) 1 non-overlapping tpc output in group 0 (independent 1 and 0 output at compare match a and b in the selected 16-bit timer channel) 10. programmable timing pattern controller (tpc) rev.4.00 aug. 20, 2007 page 300 of 638 rej09b0395-0400 10.3 operation 10.3.1 overview when corresponding bits in paddr or pbddr and ndera or nderb are set to 1, tpc output is enabled. the tpc output initially consists of the corresponding padr or pbdr contents. when a compare-match event se lected in tpcr occurs, the corresponding ndra or ndrb bit contents are transferred to padr or pbdr to update the output values. figure 10.2 illustrates the tpc output operation. table 10.3 summarizes the tpc operating conditions. ddr nder qq tpc output pin dr ndr c qd qd internal data bus output tri gg er si g nal figure 10.2 tpc output operation table 10.3 tpc operating conditions nder ddr pin function 0 0 generic input port 1 generic output port 1 0 generic input port (but the dr bit is a read-only bit, and when compare match occurs, the ndr bit value is transferred to the dr bit) 1 tpc pulse output sequential output of up to 16-bit patterns is possible by writing new output data to ndra and ndrb before the next compare match. for information on non-overlapping operation, see section 10.3.4, non-overlapping tpc output. 10. programmable timing pattern controller (tpc) rev.4.00 aug. 20, 2007 page 301 of 638 rej09b0395-0400 10.3.2 output timing if tpc output is enabled, ndra/ndrb contents are transferred to padr/pbdr and output when the selected compare matc h event occurs. figure 10.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match a. tcnt gra compare match a si g nal ndrb pbdr tp to tp 815 n n n m m n + 1 n n figure 10.3 timing of transfer of next data register contents and output (example) 10. programmable timing pattern controller (tpc) rev.4.00 aug. 20, 2007 page 302 of 638 rej09b0395-0400 10.3.3 normal tpc output sample setup procedure for normal tpc output: figure 10.4 shows a sample procedure for setting up normal tpc output. normal tpc output set next tpc output data compare match? no ye s set next tpc output data 16-bit timer setup 16-bit timer setup port and tpc setup 10 11 9 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. set tior to make gra an output compare re g ister (with output inhibited). set the tpc output tri gg er period. select the counter clock source with bits tpsc2 to tpsc0 in tcr. select the counter clear source with bits cclr1 and cclr0. enable the imfa interrupt in tisra. set the initial output values in the dr bits of the input/output port pins to be used for tpc output. set the ddr bits of the input/output port pins to be used for tpc output to 1. set the nder bits of the pins to be used for tpc output to 1. select the 16-bit timer compare match event to be used as the tpc output tri gg er in tpcr. set the next tpc output values in the ndr bits. set the str bit to 1 in tstr to start the timer counter. at each imfa interrupt, set the next output values in the ndr bits. 1 2 3 4 5 6 7 8 select gr functions set gra value select countin g operation select interrupt request start counter set initial output data select port output enable tpc output select tpc output tri gg er figure 10.4 setup procedure fo r normal tpc output (example) 10. programmable timing pattern controller (tpc) rev.4.00 aug. 20, 2007 page 303 of 638 rej09b0395-0400 example of normal tpc output (example of five-phase pulse output): figure 10.5 shows an example in which the tpc is used for cyclic five-phase pulse output. gra h'0000 ndrb pbdr tp 15 tp 14 tp 13 tp 12 tp 11 1. 2. 3. 4. time 80 tcnt tcnt value c0 40 60 20 30 10 18 08 88 80 c0 compare match the 16-bit timer channel to be used as the output tri gg er channel is set up so that gra is an output compare re g ister and the counter will be cleared by compare match a. the tri gg er period is set in gra. the imiea bit is set to 1 in tisra to enable the compare match a interrupt. h'f8 is written in pbddr and nderb, and bits g3cms1, g3cms0, g2cms1, and g2cms0 are set in tpcr to select compare match in the 16-bit timer channel set up in step 1 as the output tri gg er. output data h'80 is written in ndrb. the timer counter in this 16-bit timer channel is started. when compare match a occurs, the ndrb contents are transferred to pbdr and output. the compare match/input capture a (imfa) interrupt service routine writes the next output data (h'c0) in ndrb. five-phase overlappin g pulse output (one or two phases active at a time) can be obtained by writin g h'40, h'60, h'20, h'30, h'10, h'18, h'08, h'88? at successive imfa interrupts. 00 80 c0 40 60 20 30 10 18 08 88 80 c0 40 figure 10.5 normal tpc output example (five-phase pulse output) 10. programmable timing pattern controller (tpc) rev.4.00 aug. 20, 2007 page 304 of 638 rej09b0395-0400 10.3.4 non-overlapping tpc output sample setup procedure for non-overlapping tpc output: figure 10.6 shows a sample procedure for setting up non-overlapping tpc output. non-overlappin g tpc output set next tpc output data compare match a? no ye s set next tpc output data start counter 16-bit timer setup 16-bit timer setup port and tpc setup set initial output data set up tpc output enable tpc transfer select tpc transfer tri gg er select non-overlappin g g roups 1 2 3 4 12 10 11 5 6 7 8 9 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. set tior to make gra and grb output compare re g isters (with output inhibited). set the tpc output tri gg er period in grb and the non-overlap mar g in in gra. select the counter clock source with bits tpsc2 to tpsc0 in tcr. select the counter clear source with bits cclr1 and cclr0. enable the imfa interrupt in tisra. set the initial output values in the dr bits of the input/output port pins to be used for tpc output. set the ddr bits of the input/output port pins to be used for tpc output to 1. set the nder bits of the pins to be used for tpc output to 1. in tpcr, select the 16-bit timer compare match event to be used as the tpc output tri gg er. in tpmr, select the g roups that will operate in non-overlap mode. set the next tpc output values in the ndr bits. set the str bit to 1 in tstr to start the timer counter. at each imfa interrupt, write the next output value in the ndr bits. select gr functions set gr values select countin g operation select interrupt requests figure 10.6 setup procedure for non-overlapping tpc output (example) 10. programmable timing pattern controller (tpc) rev.4.00 aug. 20, 2007 page 305 of 638 rej09b0395-0400 example of non-overlapping tpc output (example of four-phase complementary non- overlapping output): figure 10.7 shows an example of the use of tpc output for four-phase complementary non-overlapping pulse output. grb h'0000 ndrb pbdr tp 15 tp 14 tp 13 tp 12 tp 11 tp 10 tp 9 tp 8 time 95 00 65 95 59 56 95 65 05 65 41 59 50 56 14 95 05 65 tcnt period is set in grb. the non-overlap mar g in is set in gra. the imiea bit is set to 1 in tisra to enable imfa interrupts. h'ff is written in pbddr and nderb, and bits g3cms1, g3cms0, g2cms1, and g2cms0 are set in tpcr to select compare match in the 16-bit timer channel set up in step 1 as the output tri gg er. bits g3nov and g2nov are set to 1 in tpmr to select non-overlappin g output. output data h'95 is written in ndrb. tcnt value non-overlap mar g in the 16-bit timer channel to be used as the output tri gg er channel is set up so that gra and grb are output compare re g isters and the counter will be cleared by compare match b. the tpc output tri gg er 1. 2. 3. 4. the timer counter in this 16-bit timer channel is started. when compare match b occurs, outputs chan g e from 1 to 0. when compare match a occurs, outputs chan g e from 0 to 1 (the chan g e from 0 to 1 is delayed by the value of gra). the imfa interrupt service routine writes the next output data (h'65) in ndrb. four-phase complementary non-overlappin g pulse output can be obtained by writin g h'59, h'56, h'95? at successive imfa interrupts. gra figure 10.7 non-overlapping tpc output example (four-phase complementary non-overlapping pulse output) 10. programmable timing pattern controller (tpc) rev.4.00 aug. 20, 2007 page 306 of 638 rej09b0395-0400 10.3.5 tpc output triggering by input capture tpc output can be triggered by 16-bit timer input capture as well as by compare match. if gra functions as an input capture register in the 16 -bit timer channel selected in tpcr, tpc output will be triggered by the input capture si gnal. figure 10.8 shows the timing. tioc pin input capture si g nal ndr dr n n m figure 10.8 tpc output triggering by input capture (example) 10. programmable timing pattern controller (tpc) rev.4.00 aug. 20, 2007 page 307 of 638 rej09b0395-0400 10.4 usage notes 10.4.1 operation of tpc output pins tp 0 to tp 15 are multiplexed with 16-bit timer, address bus, and other pin functions. when 16-bit timer, or address bus output is enabled, the corresponding pins cannot be used for tpc output. the data transfer from ndr bits to dr bits takes place, however, rega rdless of the usage of the pin. pin functions should be changed only under conditi ons in which the output trigger event will not occur. 10.4.2 note on non-overlapping output during non-overlapping operation, the transfer of ndr bit values to dr bits takes place as follows. 1. ndr bits are always transferred to dr bits at compare match a. 2. at compare match b, ndr bits are transferred onl y if their value is 0. bits are not transferred if their value is 1. figure 10.9 illustrates the non-overlapping tpc output operation. ddr nder qq tpc output pin dr ndr c qd qd compare match a compare match b figure 10.9 non-overlapping tpc output 10. programmable timing pattern controller (tpc) rev.4.00 aug. 20, 2007 page 308 of 638 rej09b0395-0400 therefore, 0 data can be transferred ahead of 1 data by making compare match b occur before compare match a. ndr contents should not be altered during the interval from compare match b to compare match a (the non-overlap margin). this can be accomplished by having the imfa inte rrupt service routine wr ite the next data in ndr. the next data must be written before the next compare match b occurs. figure 10.10 shows the timing relationships. compare match a compare match b ndr write ndr ndr write dr 0/1 output 0/1 output 0 output 0 output do not write to ndr in this interval do not write to ndr in this interval write to ndr in this interval write to ndr in this interval figure 10.10 non-overlapping operation and ndr write timing 11. watchdog timer rev.4.00 aug. 20, 2007 page 309 of 638 rej09b0395-0400 section 11 watchdog timer 11.1 overview the h8/3008 has an on-chip watchdog timer (wdt). the wdt has two selectable functions: it can operate as a watchdog timer to supervise system operation, or it can operate as an interval timer. as a watchdog timer, it generates a reset signal for the h8/3008 chip if a system crash allows the timer counter (tcnt) to overflow befo re being rewritten. in interval timer operation, an interval timer interrupt is requested at each tcnt overflow. 11.1.1 features wdt features are listed below. ? selection of eight counter clock sources /2, /32, /64, /128, /256, /512, /2048, or /4096 ? interval timer option ? timer counter overflow generates a reset signal or interrupt. the reset signal is generated in watchdog timer operation. an interval timer interrupt is generated in interval timer operation. ? watchdog timer reset signal resets the entire h8/3008 internally, and can also be output externally. the reset signal generated by timer counter overflow during watchdog timer operation resets the entire h8/3008 internally. an external reset signal can be output from the reso pin to reset other system devices simultaneously. 11. watchdog timer rev.4.00 aug. 20, 2007 page 310 of 638 rej09b0395-0400 11.1.2 block diagram figure 11.1 shows a block diagram of the wdt. /2 /32 /64 /128 /256 /512 /2048 /4096 tcnt tcsr rstcsr reset control interrupt si g nal reset (internal, external) (interval timer) interrupt control overflow clock clock selector read/ write control internal data bus internal clock sources le g end: tcnt: tcsr: rstcsr: timer counter timer control/status re g ister reset control/status re g ister figure 11.1 wdt block diagram 11.1.3 pin configuration table 11.1 describes the wdt output pin. table 11.1 wdt pin name abbreviation i/o function reset output reso output * external output of the watchdog timer reset signal note: * open-drain output. 11. watchdog timer rev.4.00 aug. 20, 2007 page 311 of 638 rej09b0395-0400 11.1.4 register configuration table 11.2 summarizes the wdt registers. table 11.2 wdt registers address * 1 write * 2 read name abbreviation r/w initial value h'fff8c h'fff8c timer control/status register tcsr r/(w) * 3 h'18 h'fff8d timer counter tcnt r/w h'00 h'fff8e h'fff8f reset control/status register rstcsr r/(w) * 3 h'3f notes: 1. lower 20 bits of the address in advanced mode. 2. write word data starting at this address. 3. only 0 can be written in bit 7, to clear the flag. 11.2 register descriptions 11.2.1 timer counter (tcnt) tcnt is an 8-bit readab le and writable up-counter. bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w note: the method for writing to tcnt is different from that for general registers to prevent inadvertent overwriting. for details see section 11.2.4, notes on register access. when the tme bit is set to 1 in tcsr, tcnt st arts counting pulses generated from an internal clock source selected by bits cks2 to cks0 in tcsr. when the count overflows (changes from h'ff to h'00), the ovf bit is set to 1 in tcsr. tc nt is initialized to h'00 by a reset and when the tme bit is cleared to 0. 11. watchdog timer rev.4.00 aug. 20, 2007 page 312 of 638 rej09b0395-0400 11.2.2 timer control/sta tus register (tcsr) tcsr is an 8-bit readable and writable register. its functions include selecting the timer mode and clock source. bit initial value read/write 7 ovf 0 r/(w) 6 wt/ it 0 r/w 5 tme 0 r/w 4 ? 1 ? 3 ? 1 ? 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w overflow flag status fla g indicatin g overflow clo c k sele c t these bits select the tcnt clock source timer mode sele c t selects the mode timer enable selects whether tcnt runs or halts reserved bits * notes: the method for writing to tcsr is different from that for general registers to prevent inadvertent overwriting. for details see section 11.2.4, notes on register access. * only 0 can be written, to clear the flag. bits 7 to 5 are initialized to 0 by a reset and in standby mode. bits 2 to 0 are initialized to 0 by a reset. in software standby mode bits 2 to 0 are not initialized, but retain their previous values. bit 7?overflow flag (ovf): this status flag indicates that the timer counter has overflowed from h'ff to h'00. bit 7 ovf description 0 [clearing condition] cleared by reading ovf when ovf = 1, then writing 0 in ovf (initial value) 1 [setting condition] set when tcnt changes from h'ff to h'00 11. watchdog timer rev.4.00 aug. 20, 2007 page 313 of 638 rej09b0395-0400 bit 6?timer mode select (wt/ it ): selects whether to use the wdt as a watchdog timer or interval timer. if used as an interval timer, the wdt generates an interval timer interrupt request when tcnt overflows. if used as a watchdog timer, the wdt generates a reset signal when tcnt overflows. bit 6 wt/ it description 0 interval timer: requests interval timer interrupts (initial value) 1 watchdog timer: generates a reset signal bit 5?timer enable (tme): selects whether tcnt runs or is halted. when wt/ it = 1, clear the software standby bit (ssby) to 0 in sysc r before setting tme. when setting ssby to 1, tme should be cleared to 0. bit 5 tme description 0 tcnt is initialized to h'00 and halted (initial value) 1 tcnt is counting bits 4 and 3?reserved: these bits cannot be modified and are always read as 1. bits 2 to 0?clock select 2 to 0 (cks2 to cks0): these bits select one of eight internal clock sources, obtained by prescaling the system clock ( ), for input to tcnt. bit 2 cks2 bit 1 cks1 bit 0 cks0 description 0 0 0 /2 (initial value) 1 /32 1 0 /64 1 /128 1 0 0 /256 1 /512 1 0 /2048 1 /4096 11. watchdog timer rev.4.00 aug. 20, 2007 page 314 of 638 rej09b0395-0400 11.2.3 reset control/status register (rstcsr) rstcsr is an 8-bit readable and writable register that indicates when a reset signal has been generated by watchdog timer overflow, and controls external output of the reset signal. bit initial value read/write 7 wrst 0 r/(w) 6 rstoe 0 r/w 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 0 ? 1 ? 2 ? 1 ? 1 ? 1 ? * wat c hdog timer reset indicates that a reset si g nal has been g enerated reserved bits reset output enable enables or disables external output of the reset si g nal notes: the method for writing to rstcsr is different from that for general registers to prevent inadvertent overwriting. for details see section 11.2.4, notes on register access. * only 0 can be written in bit 7, to clear the flag. bits 7 and 6 are initialized by input of a reset signal at the res pin. they are not initialized by reset signals generated by watchdog timer overflow. bit 7?watchdog timer reset (wrst): during watchdog timer operation, this bit indicates that tcnt has overflowed and generated a reset signal. this reset signal resets the entire h8/3008 chip internally. if bit rstoe is set to 1, this reset signal is also output (low) at the reso pin to initialize external system devices. note that there is no reso pin in the versions with on-chip flash memory. bit 7 wrst description 0 [clearing conditions] ? reset signal at res pin. ? read wrst when wrst =1, then write 0 in wrst. (initial value) 1 [setting condition] set when tcnt overflow generates a reset signal during watchdog timer operation 11. watchdog timer rev.4.00 aug. 20, 2007 page 315 of 638 rej09b0395-0400 bit 6?reset output enable (rstoe): enables or disables external output at the reso pin of the reset signal generated if tcnt overflows during watchdog timer operation. note that there is no reso pin in the versions with on-chip flash memory. bit 6 rstoe description 0 reset signal is not output externally (initial value) 1 reset signal is output externally bits 5 to 0?reserved: these bits cannot be modified and are always read as 1. 11.2.4 notes on register access the watchdog timer's tcnt, tcsr, and rstcsr registers differ from other registers in being more difficult to write. the procedures for writing and reading these registers are given below. writing to tcnt and tcsr: these registers must be written by a word transfer instruction. they cannot be written by byte instructions. figure 11.2 shows the format of data written to tcnt and tcsr. tcnt and tcsr both have the same write address. the write data must be contained in the lower byte of the written word. the upper byte must contain h'5a (password for tcnt) or h'a5 (password for tcsr). this transf ers the write data from the lower byte to tcnt or tcsr. 15 8 7 0 h'5a write data address h'fff8c * 15 8 7 0 h'a5 write data address h'fff8c * tcnt write tcsr write note: lower 20 bits of the address in advanced mode. * figure 11.2 format of data written to tcnt and tcsr 11. watchdog timer rev.4.00 aug. 20, 2007 page 316 of 638 rej09b0395-0400 writing to rstcsr: rstcsr must be written by a word transfer instruction. it cannot be written by byte transfer instructions. figure 11.3 shows the format of data written to rstcsr. to write 0 in the wrst bit, the write data must have h'a5 in the upper byte and h'00 in the lower byte. the data (h'00) in the lower byte is written to rstcsr, clearing the wrst bit to 0. to write to the rstoe bit, the upper byte must contain h'5a and the lower byte must contain the write data. writing this word transfers a write data value into the rstoe bit. 15 8 7 0 h'a5 h'00 address h'fff8e * 15 8 7 0 h'5a write data address h'fff8e * writin g 0 in wrst bit writin g to rstoe bit note: lower 20 bits of the address in advanced mode. * figure 11.3 format of data written to rstcsr reading tcnt, tcsr, and rstcsr: for reads of tcnt, tcsr, and rstcsr, address h'fff8c is assigned to tcsr, address h'fff8d to tcnt, and address h'fff8f to rstcsr. these registers are therefore read like other registers. byte transfer instructions can be used for reading. table 11.3 lists the read addresses of tcnt, tcsr, and rstcsr. table 11.3 read addresses of tcnt, tcsr, and rstcsr address * register h'fff8c tcsr h'fff8d tcnt h'fff8f rstcsr note: * lower 20 bits of the address in advanced mode. 11. watchdog timer rev.4.00 aug. 20, 2007 page 317 of 638 rej09b0395-0400 11.3 operation operations when the wdt is used as a watchdog timer and as an interval timer are described below. 11.3.1 watchdog timer operation figure 11.4 illustrates watchdog timer operation. to use the wdt as a watchdog timer, set the wt/ it and tme bits to 1 in tcsr. software must prevent tcnt overflow by rewriting the tcnt value (normally by writing h'00) before overflow occurs. if tcnt fails to be rewritten and overflows due to a system crash etc., the h8/3008 is internally reset for a duration of 518 states. the watchdog reset signal can be externally output from the reso pin to reset external system devices. the reset signal is output externally for 132 states. external output can be enabled or disabled by the rstoe bit in rstcsr. a watchdog reset has the same vector as a reset generated by input at the res pin. software can distinguish a res reset from a watchdog reset by checking the wrst bit in rstcsr. if a res reset and a watchdog reset occur simultaneously, the res reset takes priority. h'ff h'00 reso wdt overflow start h'00 written in tcnt reset tme set to 1 h'00 written in tcnt internal reset si g nal 518 states 132 states tcnt count value ovf = 1 figure 11.4 operation in watchdog timer mode 11. watchdog timer rev.4.00 aug. 20, 2007 page 318 of 638 rej09b0395-0400 11.3.2 interval timer operation figure 11.5 illustrates interval timer operation. to use the wdt as an interval timer, clear bit wt/ it to 0 and set bit tme to 1 in tcsr. an interv al timer interrupt request is generated at each tcnt overflow. this function can be used to generate interval timer interrupts at regular intervals. tcnt count value time t interval timer interrupt interval timer interrupt interval timer interrupt interval timer interrupt wt/ = 0 tme = 1 it h'ff h'00 figure 11.5 interval timer operation 11.3.3 timing of setting of overflow flag (ovf) figure 11.6 shows the timing of setting of the ovf flag. the ovf flag is set to 1 when tcnt overflows. at the same time, a reset signal is gene rated in watchdog timer operation, or an interval timer interrupt is generated in interval timer operation. tcnt overflow si g nal ovf h'ff h'00 figure 11.6 timing of setting of ovf 11. watchdog timer rev.4.00 aug. 20, 2007 page 319 of 638 rej09b0395-0400 11.3.4 timing of setting of watchdog timer reset bit (wrst) the wrst bit in rstcsr is valid when bits wt/ it and tme are both set to 1 in tcsr. figure 11.7 shows the timing of setting of wrst and the internal reset timing. the wrst bit is set to 1 when tcnt overflows and ovf is set to 1. at the same time an internal reset signal is generated for the entire h8/3008 chip. this internal reset signal clears ovf to 0, but the wrst bit remains set to 1. the reset routine must therefore clear the wrst bit. tcnt overflow si g nal ovf wrst h'ff h'00 wdt internal reset figure 11.7 timing of setting of wrst bit and internal reset 11. watchdog timer rev.4.00 aug. 20, 2007 page 320 of 638 rej09b0395-0400 11.4 interrupts during interval timer operation, an overflow generates an interval timer interrupt (wovi). the interval timer interrupt is requested when ever the ovf flag is set to 1 in tcsr. 11.5 usage notes contention between tcnt write and increment: if a timer counter clock pulse is generated during the t 3 state of a write cycle to tcnt, the write takes priority and the timer count is not incremented. see figure 11.8. tcnt tcnt nm counter write data t 3 t 2 t 1 cpu: tcnt write cycle internal write si g nal tcnt input clock figure 11.8 contention betw een tcnt write and count up changing cks2 to cks0 bit: halt tcnt by clearing the tme bit to 0 in tcsr before changing the values of bits cks2 to cks0. 12. serial communication interface rev.4.00 aug. 20, 2007 page 321 of 638 rej09b0395-0400 section 12 serial communication interface 12.1 overview the h8/3008 has a serial communication interface (sci) with two independe nt channels. the two channels have identical functions. the sci can communicate in both asynchronous and synchronous mode. it also has a multiprocessor communication function for serial communication among two or more processors. when the sci is not used, it can be halted to conserve power. each sci channel can be halted independently. for details, see section 18.6, module standby function. the sci also has a smart card interface function co nforming to the iso/iec 7816-3 (identification card) standard. this function supports serial communication with a smart card. switching between the normal serial comm unication interface and the smart card interface is carried out by means of a register setting. 12.1.1 features sci features are listed below. ? selection of synchronous or asynchronous mode for serial communication asynchronous mode serial data communication is synchronized one character at a time. the sci can communicate with a universal asynchronous receiver/tr ansmitter (uart), asynchronous communication interface adapter (acia), or othe r chip that employs standard asynchronous communication. it can also communicate with two or more other processors using the multiprocessor communication function. there are twelve sel ectable serial data transfer formats. ? data length: 7 or 8 bits ? stop bit length: 1 or 2 bits ? parity: even/odd/none ? multiprocessor bit: 1 or 0 ? receive error detection: parity , overrun, and framing errors ? break detection: by reading the rxd level directly when a framing error occurs synchronous mode serial data communication is synchronized with a clock signal. the sci can communicate with other chips having a synchronous communication function. there is a single serial data communication format. 12. serial communication interface rev.4.00 aug. 20, 2007 page 322 of 638 rej09b0395-0400 ? data length: 8 bits ? receive error detec tion: overrun errors ? full-duplex communication the transmitting and receiving sections are inde pendent, so the sci can transmit and receive simultaneously. the transmitting and receiving s ections are both double- buffered, so serial data can be transmitted and received continuously. ? the following settings can be made for the serial data to be transferred: ? lsb-first or msb-first transfer ? inversion of data logic level ? built-in baud rate generator with selectable bit rates ? selectable transmit/receive clock sources: internal clock from baud rate generator, or external clock from the sck pin ? four types of interrupts transmit-data-empty, transmit-end, receive-data-fu ll, and receive-error interrupts are requested independently. features of the smart card interface are listed below. ? asynchronous communication ? data length: 8 bits ? parity bits generated and checked ? error signal output in receive mode (parity error) ? error signal detect and automatic data retransmit in transmit mode ? supports both direct convention and inverse convention ? built-in baud rate generator with selectable bit rates ? three types of interrupts transmit-data-empty, receive-data-full, and tr ansmit/receive-error interrupts are requested independently. 12. serial communication interface rev.4.00 aug. 20, 2007 page 323 of 638 rej09b0395-0400 12.1.2 block diagram figure 12.1 shows a block diagram of the sci. rdr rsr tdr tsr ssr scr smr scmr brr / 4 /16 /64 rxd txd sck tei txi rxi eri le g end: rsr: receive shift re g ister rdr: receive data re g ister tsr: transmit shift re g ister tdr: transmit data re g ister smr: serial mode re g ister scr: serial control re g ister ssr: serial status re g ister brr: bit rate re g ister scmr: smart card mode re g ister module data bus bus interface internal data bus parity g enerate parity check transmit/receive control baud rate g enerator clock external clock figure 12.1 sci block diagram 12. serial communication interface rev.4.00 aug. 20, 2007 page 324 of 638 rej09b0395-0400 12.1.3 pin configuration the sci has serial pins for each channel as listed in table 12.1. table 12.1 sci pins channel name abbreviation i/o function 0 serial clock pin sck 0 input/output sci 0 clock input/output receive data pin rxd 0 input sci 0 receive data input transmit data pin txd 0 output sci 0 transmit data output 1 serial clock pin sck 1 input/output sci 1 clock input/output receive data pin rxd 1 input sci 1 receive data input transmit data pin txd 1 output sci 1 transmit data output 12. serial communication interface rev.4.00 aug. 20, 2007 page 325 of 638 rej09b0395-0400 12.1.4 register configuration the sci has internal registers as listed in table 12.2. these registers select asynchronous or synchronous mode, specify the data format and bit rate, control the transmitter and receiver sections, and specify switching between the serial communication interface and smart card interface. table 12.2 sci registers channel address * 1 name abbreviation r/w initial value 0 h'fffb0 serial mode register smr r/w h'00 h'fffb1 bit rate register brr r/w h'ff h'fffb2 serial control register scr r/w h'00 h'fffb3 transmit data register tdr r/w h'ff h'fffb4 serial status register ssr r/(w) * 2 h'84 h'fffb5 receive data register rdr r h'00 h'fffb6 smart card mode register scmr r/w h'f2 1 h'fffb8 serial mode register smr r/w h'00 h'fffb9 bit rate register brr r/w h'ff h'fffba serial control register scr r/w h'00 h'fffbb transmit data register tdr r/w h'ff h'fffbc serial status register ssr r/(w) * 2 h'84 h'fffbd receive data register rdr r h'00 h'fffbe smart card mode register scmr r/w h'f2 notes: 1. indicates the lower 20 bits of the address in advanced mode. 2. only 0 can be written, to clear flags. 12. serial communication interface rev.4.00 aug. 20, 2007 page 326 of 638 rej09b0395-0400 12.2 register descriptions 12.2.1 receive shift register (rsr) rsr is the register that receives serial data. bit 7 ? 6 ? 5 ? 4 ? 3 ? 2 ? 1 ? 0 ? read/write the sci loads serial data input at the rxd pin in to rsr in the order received, lsb (bit 0) first, thereby converting the data to parallel data. wh en one byte of data has been received, it is automatically transferred to rdr. the cpu cannot read or write rsr directly. 12.2.2 receive data register (rdr) rdr is the register that st ores received serial data. bit 7654321 0 initial value read/write r 00000 0 0 0 r r r r r r r when the sci has received one byte of serial data , it transfers the receive d data from rsr into rdr for storage, completing the r eceive operation. rsr is then ready to receive the next data. this double-buffering allows data to be received continuously. rdr is a read-only register. its contents cannot be modified by the cpu. rdr is initialized to h'00 by a reset and in standby mode. 12. serial communication interface rev.4.00 aug. 20, 2007 page 327 of 638 rej09b0395-0400 12.2.3 transmit shift register (tsr) tsr is the register that transmits serial data. bit 7 ? 6 ? 5 ? 4 ? 3 ? 2 ? 1 ? 0 ? read/write the sci loads transmit data from tdr to tsr, then transmits the data serially from the txd pin, lsb (bit 0) first. after transmitting one data byte, the sci automatically loads the next transmit data from tdr into tsr and starts transmitting it. if the tdre flag is set to 1 in ssr, however, the sci does not load the tdr contents into tsr. the cpu cannot read or write rsr directly. 12.2.4 transmit data register (tdr) tdr is an 8-bit register that stor es data for serial transmission. bit 7 6 54 3 2 1 0 initial value read/write r/w 11 1111 11 r/w r/w r/w r/w r/w r/w r/w when the sci detects that tsr is empty, it moves transmit data written in tdr from tdr into tsr and starts serial transmission. continuous se rial transmission is po ssible by writing the next transmit data in tdr during serial transmission from tsr. the cpu can always read and write tdr. tdr is initialized to h'ff by a reset and in standby mode. 12. serial communication interface rev.4.00 aug. 20, 2007 page 328 of 638 rej09b0395-0400 12.2.5 serial mode register (smr) smr is an 8-bit register that sp ecifies the sci's serial communica tion format and selects the clock source for the baud rate generator. c/ a chr pe o/ e stop mp cks1 cks0 r/w 000 0 0000 r/w r/w r/w r/w r/w r/w r/w initial value read/write bit 76 54 32 1 0 clo c k sele c t 1/0 these bits select the baud rate g enerator's clock source communi c ation mode selects asynchronous or synchronous mode chara c ter length selects character len g th in asynchronous mode parity enable selects whether a parity bit is added parity mode selects even or odd parity stop bit length selects the stop bit len g th multipro c essor mode selects the multiprocessor function the cpu can always read and write smr. smr is initialized to h'00 by a reset and in standby mode. bit 7?communication mode (c/ a )/gsm mode (gm): the function of this bit differs for the normal serial communication interface and for the smart card interface. its function is switched with the smif bit in scmr. 12. serial communication interface rev.4.00 aug. 20, 2007 page 329 of 638 rej09b0395-0400 for serial communication interface (smif bit in scmr cleared to 0): selects whether the sci operates in asynchronous or synchronous mode. bit 7 c/ a description 0 asynchronous mode (initial value) 1 synchronous mode for smart card interface (smif bit in scmr set to 1): selects gsm mode for the smart card interface. bit 7 gm description 0 the tend flag is set 12.5 etu after the start bit (initial value) 1 the tend flag is set 11.0 etu after the start bit note: etu: elementary time unit (time required to transmit one bit) bit 6?character length (chr): selects 7-bit or 8-bits data length in asynchronous mode. in synchronous mode, the data length is 8 bits regardless of the chr setting, bit 6 chr description 0 8-bit data (initial value) 1 7-bit data * note: * when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted. bit 5?parity enable (pe): in asynchronous mode, this bit enables or disables the addition of a parity bit to transmit data , and the checking of the parity bit in receive data. in synchronous mode, the parity bit is neither added nor checked, regardless of the pe bit setting. bit 5 pe description 0 parity bit not added or checked (initial value) 1 parity bit added and checked * note: * when pe bit is set to 1, an even or odd parity bit is added to transmit data according to the even or odd parity mode selection by the o/ e bit, and the parity bit in receive data is checked to see that it matches the even or odd mode selected by the o/ e bit. 12. serial communication interface rev.4.00 aug. 20, 2007 page 330 of 638 rej09b0395-0400 bit 4?parity mode (o/ e ): specifies whether even parity or odd parity is used for parity addition and checking. the o/ e bit setting is only valid when the pe bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. the o/ e bit setting is ignored in synchronous mode, or when parity addition and checking is disabled in asynchronous mode. bit 4 o/ e description 0 even parity * 1 (initial value) 1 odd parity * 2 notes: 1. when even parity is selected, the parity bit added to transmit data makes an even number of 1s in the transmitted character and parity bit combined. receive data must have an even number of 1s in the received character and parity bit combined. 2. when odd parity is selected, the parity bi t added to transmit data makes an odd number of 1s in the transmitted character and parity bit combined. receive data must have an odd number of 1s in the received character and parity bit combined. bit 3?stop bit length (stop): selects one or two stop bits in asynchronous mode. this setting is used only in asynchronous mode. in synchronous mode no stop bit is added, so the stop bit setting is ignored. bit 3 stop description 0 1 stop bit * 1 (initial value) 1 2 stop bits * 2 notes: 1. one stop bit (with value 1) is added to the end of each transmitted character. 2. two stop bits (with value 1) are added to the end of each transmitted character. in receiving, only the first stop bit is checked, regardless of th e stop bit setting. if the second stop bit is 1, it is treated as a stop bit. if the second stop bit is 0, it is treated as the start bit of the next incoming character. 12. serial communication interface rev.4.00 aug. 20, 2007 page 331 of 638 rej09b0395-0400 bit 2?multiprocessor mode (mp): selects a multiprocessor format. when a multiprocessor format is selected, parity settings made by the pe and o/ e bits are ignored. the mp bit setting is valid only in asynchronous mode. it is ignored in synchronous mode. for further information on the multiprocessor communication function, see section 12.3.3, multiprocessor communication. bit 2 mp description 0 multiprocessor function disabled (initial value) 1 multiprocessor format selected bits 1 and 0?clock select 1 and 0 (cks1, cks0): these bits select the clock source for the on- chip baud rate generator. four clock sources can be selected by the cks1 and cks0 bits: , /4, /16, and /64. for the relationship between the clock source, bit rate register setting, and baud rate, see section 12.2.8, bit rate register (brr). bit 1 cks1 bit 0 cks0 description 0 0 (initial value) 0 1 /4 1 0 /16 1 1 /64 12. serial communication interface rev.4.00 aug. 20, 2007 page 332 of 638 rej09b0395-0400 12.2.6 serial control register (scr) scr register enables or disables the sci transmitter and receiver, enables or disables serial clock output in asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock source. bit 7 6 5 4 3210 tie rie te re mpie teie cke1 cke0 initial value read/write r/w 0 00000 0 0 r/w r/w r/w r/w r/w r/w r/w transmit-end interrupt enable enables or disables transmit-end interrupts (tei) multipro c essor interrupt enable enables or disables multiprocessor interrupts re c eive enable enables or disables the receiver transmit enable enables or disables the transmitter re c eive interrupt enable enables or disables receive-data-full interrupts (rxi) and receive-error interrupts (eri) transmit interrupt enable enables or disables transmit-data-empty interrupts (txi) clo c k enable 1/0 these bits select the sci clock source the cpu can always read and write scr. scr is initialized to h'00 by a reset and in standby mode. 12. serial communication interface rev.4.00 aug. 20, 2007 page 333 of 638 rej09b0395-0400 bit 7?transmit interrupt enable (tie): enables or disables the transmit-data-empty interrupt (txi) requested when the tdre flag in ssr is set to 1 due to transfer of serial transmit data from tdr to tsr. bit 7 tie description 0 transmit-data-empty interrupt request (txi) is disabled * (initial value) 1 transmit-data-empty interrupt request (txi) is enabled note: * txi interrupt requests can be cleared by reading the value 1 from the tdre flag, then clearing it to 0; or by clearing the tie bit to 0. bit 6?receive interrupt enable (rie): enables or disables the r eceive-data-full interrupt (rxi) requested when the rdrf flag in ssr is set to 1 due to transfer of serial receive data from rsr to rdr; also enables or disables th e receive-error interrupt (eri). bit 6 rie description 0 receive-data-full (rxi) and receive-error (eri) interrupt requests are disabled * (initial value) 1 receive-data-full (rxi) and receive-error (eri) interrupt requests are enabled note: * rxi and eri interrupt requests can be cleared by reading the value 1 from the rdrf, fer, per, or orer flag, then clearing the flag to 0; or by clearing the rie bit to 0. bit 5?transmit enable (te): enables or disables the start of sci serial transmitting operations. bit 5 te description 0 transmitting disabled * 1 (initial value) 1 transmitting enabled * 2 notes: 1. the tdre flag is fixed at 1 in ssr. 2. in the enabled state, serial transmission starts when the tdre flag in ssr is cleared to 0 after writing of transmit data into tdr. select the transmit format in smr before setting the te bit to 1. 12. serial communication interface rev.4.00 aug. 20, 2007 page 334 of 638 rej09b0395-0400 bit 4?receive enable (re): enables or disables the start of sci serial receiving operations. bit 4 re description 0 receiving disabled * 1 (initial value) 1 receiving enabled * 2 notes: 1. clearing the re bit to 0 does not affect the rdrf, fer, per, and orer flags. these flags retain their previous values. 2. in the enabled state, serial receiving starts when a start bit is detected in asynchronous mode, or serial clock input is detected in synchronous mode. select the receive format in smr before setting the re bit to 1. bit 3?multiprocessor interrupt enable (mpie): enables or disables multiprocessor interrupts. the mpie bit setting is valid only in asynchronous mode, and only if the mp bit is set to 1 in smr. the mpie bit setting is ignored in synchronous mode or when the mp bit is cleared to 0. bit 3 mpie description 0 multiprocessor interrupts are disabled (nor mal receive operation) (initial value) [clearing conditions] ? the mpie bit is cleared to 0 ? mpb = 1 in received data 1 multiprocessor interrupts are enabled * receive-data-full interrupts (rxi), receive-error interrupts (eri), and setting of the rdrf, fer, and orer status flags in ssr are disabled until data with the multiprocessor bit set to 1 is received. note: * the sci does not transfer receive data from rsr to rdr, does not detect receive errors, and does not set the rdrf, fer, and orer flags in ssr. when it receives data in which mpb = 1, the sci sets the mpb bit to 1 in ssr, automatically clears the mpie bit to 0, enables rxi and eri interrupts (if the tie and rie bits in scr are set to 1), and allows the fer and orer flags to be set. 12. serial communication interface rev.4.00 aug. 20, 2007 page 335 of 638 rej09b0395-0400 bit 2?transmit-end interrupt enable (teie): enables or disables the transmit-end interrupt (tei) requested if tdr does not contain valid transmit data when the msb is transmitted. bit 2 teie description 0 transmit-end interrupt requests (tei) are disabled * (initial value) 1 transmit-end interrupt requests (tei) are enabled * note: * tei interrupt requests can be cleared by reading the value 1 from the tdre flag in ssr, then clearing the tdre flag to 0, thereby also clearing the tend flag to 0; or by clearing the teie bit to 0. bits 1 and 0?clock enable 1 and 0 (cke1, cke0): the function of these bits differs for the normal serial communication interface and for the smart card interface. their function is switched with the smif bit in scmr. for serial communication interface (smif bit in scmr cleared to 0): these bits select the sci clock source and enable or disable clock output from the sck pin. depending on the settings of cke1 and cke0, the sck pin can be used for generic input/output, serial clock output, or serial clock input. the cke0 setting is valid only in asynchronous mode, and only when the sci is internally clocked (cke1 = 0). the cke0 setting is ignored in synchronous mode, or when an external clock source is selected (cke1 = 1). select the sci operating mode in smr before setting the cke1 and cke0 bits . for further details on selection of the sci clock source, see table 12.9 in section 12.3, operation. bit 1 cke1 bit 0 cke0 description 0 0 asynchronous mode internal clock, sck pin available for generic input/output * 1 synchronous mode internal clock, sck pin used for serial clock output * 1 0 1 asynchronous mode internal clock, sck pin used for clock output * 2 synchronous mode internal clock, sck pin used for serial clock output 1 0 asynchronous mode external clock, sck pin used for clock input * 3 synchronous mode external clock, sck pin used for serial clock input 1 1 asynchronous mode external clock, sck pin used for clock input * 3 synchronous mode external clock, sck pin used for serial clock input notes: 1. initial value 2. the output clock frequency is the same as the bit rate. 3. the input clock frequency is 16 times the bit rate. 12. serial communication interface rev.4.00 aug. 20, 2007 page 336 of 638 rej09b0395-0400 for smart card interface (smif bit in scmr set to 1): these bits, together with the gm bit in smr, determine whether the sck pin is used for generic input/output or as the serial clock output pin. smr gm bit 1 cke1 bit 0 cke0 description 0 0 0 sck pin available for generic input/output (initial value) 0 0 1 sck pin used for clock output 1 0 0 sck pin output fixed low 1 0 1 sck pin used for clock output 1 1 0 sck pin output fixed high 1 1 1 sck pin used for clock output 12. serial communication interface rev.4.00 aug. 20, 2007 page 337 of 638 rej09b0395-0400 12.2.7 serial status register (ssr) ssr is an 8-bit register containing multiprocessor bit values, and status flags that indicate the operating status of the sci. initial value read/write rr/w 0 1000100 bit 76 54 32 1 0 multipro c essor bit transfer value of multiprocessor bit to be transmitted r/(w) ? 1 r/(w) ? 1 r/(w) ? 1 r/(w) ? 1 r/(w) ? 1 r tdre rdrf orer fer/ers per tend mpb mpbt multipro c essor bit stores the received multiprocessor bit value transmit end ? 2 status fla g indicatin g end of transmission parity error status fla g indicatin g detection of a receive parity error framing error (fer)/error signal status (ers) ? 2 status fla g indicatin g detection of a receive framin g error, or fla g indicatin g detection of an error si g nal overrun error status fla g indicatin g detection of a receive overrun error re c eive data register full status fla g indicatin g that data has been received and stored in rdr transmit data register empty status fla g indicatin g that transmit data has been transferred from tdr into tsr and new data can be written in tdr notes: 1. only 0 can be written, to clear the fla g . 2. function differs between the normal serial communication interface and the smart card interface. 12. serial communication interface rev.4.00 aug. 20, 2007 page 338 of 638 rej09b0395-0400 the cpu can always read and write ssr, but cannot write 1 in the tdre, rdrf, orer, per, and fer flags. these flags can be cleared to 0 only if they have first been read while set to 1. the tend and mpb flags are read-only bits that cannot be written. ssr is initialized to h'84 by a reset and in standby mode. bit 7?transmit data register empty (tdre): indicates that the sci has loaded transmit data from tdr into tsr and the next serial data can be written in tdr. bit 7 tdre description 0 tdr contains valid transmit data [clearing condition] read tdre when tdre = 1, then write 0 in tdre 1 tdr does not contain valid transmit data (initial value) [setting conditions] ? the chip is reset or enters standby mode ? the te bit in scr is cleared to 0 ? tdr contents are loaded into tsr, so new data can be written in tdr bit 6?receive data register full (rdrf): indicates that rdr cont ains new receive data. bit 6 rdrf description 0 rdr does not contain new receive data (initial value) [clearing conditions] ? the chip is reset or enters standby mode ? read rdrf when rdrf = 1, then write 0 in rdrf 1 rdr contains new receive data [setting condition] serial data is received normally and transferred from rsr to rdr note: the rdr contents and the rdrf flag are not affected by detection of receive errors or by clearing of the re bit to 0 in scr. they retain their previous values. if the rdrf flag is still set to 1 when reception of the next data ends, an overrun error will occur and the receive data will be lost. 12. serial communication interface rev.4.00 aug. 20, 2007 page 339 of 638 rej09b0395-0400 bit 5?overrun error (orer): indicates that data reception ended abnormally due to an overrun error. bit 5 orer description 0 receiving is in progress or has ended normally * 1 (initial value) [clearing conditions] ? the chip is reset or enters standby mode ? read orer when orer = 1, then write 0 in orer 1 a receive overrun error occurred * 2 [setting condition] reception of the next serial data ends when rdrf = 1 notes: 1. clearing the re bit to 0 in scr does not affect the orer flag, which retains its previous value. 2. rdr continues to hold the receive data prior to the overrun error, so subsequent receive data is lost. serial receiving cannot continue while the orer flag is set to 1. in synchronous mode, serial transmitting is also disabled. bit 4?framing error (fer)/error signal status (ers): the function of this bit differs for the normal serial communication interface and for the smart card interface. its function is switched with the smif bit in scmr. for serial communication interface (smif bit in scmr cleared to 0): indicates that data reception ended abnormally due to a framing error in asynchronous mode. bit 4 fer description 0 receiving is in progress or has ended normally * 1 (initial value) [clearing conditions] ? the chip is reset or enters standby mode ? read fer when fer = 1, then write 0 in fer 1 a receive framing error occurred [setting condition] the stop bit at the end of the receive data is checked for a value of 1, and is found to be 0. * 2 notes: 1. clearing the re bit to 0 in scr does not affect the fer flag, which retains its previous value. 2. when the stop bit length is 2 bits, only the first bit is checked for a value of 1. the second stop bit is not checked. when a framing error occurs the sci transfers the receive data into rdr but does not set the rdrf flag. serial receiving cannot continue while the fer flag is set to 1. in synchronous mode, serial transmitting is also disabled. 12. serial communication interface rev.4.00 aug. 20, 2007 page 340 of 638 rej09b0395-0400 for smart card interface (smif bit in scmr set to 1): indicates the status of the error signal sent back from the receiving side during transmi ssion. framing errors are not detected in smart card interface mode. bit 4 ers description 0 normal reception, no error signal * (initial value) [clearing conditions] ? the chip is reset or enters standby mode ? read ers when ers = 1, then write 0 in ers 1 an error signal has been sent from the receiving side indicating detection of a parity error [setting condition] the error signal is low when sampled note: * clearing the te bit to 0 in scr does not affect the ers flag, which retains its previous value. bit 3?parity error (per): indicates that reception of data with parity added ended abnormally due to a parity error in asynchronous mode. bit 3 per description 0 receiving is in progress or has ended normally * 1 (initial value) [clearing conditions] ? the chip is reset or enters standby mode ? read per when per = 1, then write 0 in per 1 a receive parity error occurred * 2 [setting condition] the number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of o/ e in smr notes: 1. clearing the re bit to 0 in scr does not affect the per flag, which retains its previous value. 2. when a parity error occurs the sci transfers the receive data into rdr but does not set the rdrf flag. serial receiving cannot continue while the per flag is set to 1. in synchronous mode, serial transmitting is also disabled. bit 2?transmit end (tend): the function of this bit differs for the normal serial communication interface and for the smart card interface. its function is switched with the smif bit in scmr. 12. serial communication interface rev.4.00 aug. 20, 2007 page 341 of 638 rej09b0395-0400 for serial communication interface (smif bit in scmr cleared to 0): indicates that when the last bit of a serial character was transmitted tdr did not contain valid transmit data, so transmission has ended. the tend flag is a read-only bit and cannot be written. bit 2 tend description 0 transmission is in progress [clearing condition] read tdre when tdre = 1, then write 0 in tdre 1 end of transmission (initial value) [setting conditions] ? the chip is reset or enters standby mode ? the te bit in scr is cleared to 0 ? tdre is 1 when the last bit of a 1-byte serial transmit character is transmitted for smart card interface (smif bit in scmr set to 1): indicates that when the last bit of a serial character was transmitted tdr did not contain valid transmit data, so transmission has ended. the tend flag is a read -only bit and cannot be written. bit 2 tend description 0 transmission is in progress [clearing condition] read tdre when tdre = 1, then write 0 in tdre 1 end of transmission (initial value) [setting conditions] ? the chip is reset or enters standby mode ? the te bit is cleared to 0 in scr and the fer/ers bit is also cleared to 0 ? tdre is 1 and fer/ers is 0 (normal transmission) 2.5 etu (when gm = 0) or 1.0 etu (when gm = 1) after a 1-byte serial character is transmitted note: etu: elementary time unit (time required to transmit one bit) 12. serial communication interface rev.4.00 aug. 20, 2007 page 342 of 638 rej09b0395-0400 bit 1?multiprocessor bit (mpb): stores the value of the multiprocessor bit in the receive data when a multiprocessor format is used in asynchronous mode. mpb is a read-only bit, and cannot be written. bit 1 mpb description 0 multiprocessor bit value in receive data is 0 * (initial value) 1 multiprocessor bit value in receive data is 1 note: * if the re bit in scr is cleared to 0 when a multiprocessor format is selected, mpb retains its previous value. bit 0?multiprocessor bit transfer (mpbt): stores the value of the multiprocessor bit added to transmit data when a multiprocessor format in selected for transmitting in asynchronous mode. the mpbt bit setting is ignored in synchronous mode, when a multiprocessor format is not selected, or when the sci cannot transmit. bit 0 mpbt description 0 multiprocessor bit value in transmit data is 0 (initial value) 1 multiprocessor bit value in transmit data is 1 12.2.8 bit rate register (brr) brr is an 8-bit register that sets the serial transmit/receive bit rate in accordance with the baud rate generator operating clock selected by bits cks0 and cks1 in smr. bit initial value read/write 7 r/w r/w r/w r/w r/w r/w r/w r/w 6 1 11 1 11 11 5 4 32 1 0 brr can be read or written to by the cpu at all times. brr is initialized to h'ff by a reset and in standby mode. as baud rate generator control is performed inde pendently for each channel, different values can be set for each channel. 12. serial communication interface rev.4.00 aug. 20, 2007 page 343 of 638 rej09b0395-0400 table 12.3 shows examples of brr settings in asynchronous mode. table 12.4 shows examples of brr settings in synchronous mode. table 12.3 examples of bit rates and brr settings in asynchronous mode (mhz) bit rate 2 2.097152 2.4576 3 (bit/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 1 141 0.03 1 148 ? 0.04 1 174 ? 0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 ? 0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 ? 2.48 0 15 0.00 0 19 ? 2.34 9600 0 6 ? 6.99 0 6 ? 2.48 0 7 0.00 0 9 ? 2.34 19200 0 2 8.51 0 2 13.78 0 3 0.00 0 4 ? 2.34 31250 0 1 0.00 0 1 4.86 0 1 22.88 0 2 0.00 38400 0 1 ? 18.62 0 1 ? 14.67 0 1 0.00 ? ? ? (mhz) bit rate 3.6864 4 4.9152 5 (bit/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 ? 0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 ? 1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 0 6 ? 6.99 0 7 0.00 0 7 1.73 31250 ? ? ? 0 3 0.00 0 4 ? 1.70 0 4 0.00 38400 0 2 0.00 0 2 8.51 0 3 0.00 0 3 1.73 12. serial communication interface rev.4.00 aug. 20, 2007 page 344 of 638 rej09b0395-0400 (mhz) bit rate 6 6.144 7.3728 8 (bit/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 106 ? 0.44 2 108 0.08 2 130 ? 0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 ? 2.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 ? 2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 0 6 5.33 0 7 0.00 38400 0 4 ? 2.34 0 4 0.00 0 5 0.00 0 6 ? 6.99 (mhz) bit rate 9.8304 10 12 12.288 (bit/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 174 ? 0.26 2 177 ? 0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 ? 1.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 ? 2.34 0 19 0.00 31250 0 9 ? 1.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 ? 2.34 0 9 0.00 12. serial communication interface rev.4.00 aug. 20, 2007 page 345 of 638 rej09b0395-0400 (mhz) bit rate 13 14 14.7456 16 (bit/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 230 ? 0.08 2 248 ? 0.17 3 64 0.70 3 70 0.03 150 2 168 0.16 2 181 0.16 2 191 0.00 2 207 0.16 300 2 84 ? 0.43 2 90 0.16 2 95 0.00 2 103 0.16 600 1 168 0.16 1 181 0.16 1 191 0.00 1 207 0.16 1200 1 84 ? 0.43 1 90 0.16 1 95 0.00 1 103 0.16 2400 0 168 0.16 0 181 0.16 0 191 0.00 0 207 0.16 4800 0 84 ? 0.43 0 90 0.16 0 95 0.00 0 103 0.16 9600 0 41 0.76 0 45 ? 0.93 0 47 0.00 0 51 0.16 19200 0 20 0.76 0 22 ? 0.93 0 23 0.00 0 25 0.16 31250 0 12 0.00 0 13 0.00 0 14 ? 1.70 0 15 0.00 38400 0 10 ? 3.82 0 10 3.57 0 11 0.00 0 12 0.16 (mhz) bit rate 18 20 25 (bit/s) n n error ( % ) n n error ( % ) n n error ( % ) 110 3 79 ? 0.12 3 88 ? 0.25 3 110 ? 0.02 150 2 233 0.16 3 64 0.16 3 80 ? 0.47 300 2 116 0.16 2 129 0.16 2 162 0.15 600 1 233 0.16 2 64 0.16 2 80 ? 0.47 1200 1 116 0.16 1 129 0.16 1 162 0.15 2400 0 233 0.16 1 64 0.16 1 80 ? 0.47 4800 0 116 0.16 0 129 0.16 0 162 0.15 9600 0 58 ? 0.69 0 64 0.16 0 80 ? 0.47 19200 0 28 1.02 0 32 ? 1.36 0 40 ? 0.76 31250 0 17 0.00 0 19 0.00 0 24 0.00 38400 0 14 ? 2.34 0 15 1.73 0 19 1.73 12. serial communication interface rev.4.00 aug. 20, 2007 page 346 of 638 rej09b0395-0400 table 12.4 examples of bit rates and brr settings in synchronous mode bit (mhz) rate 2 4 8 10 13 16 18 20 25 (bit/s) n n n n n n n n n n n n n n n n n n 110 3 70 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 250 2 124 2 249 3 124 ? ? 3 202 3 249 ? ? ? ? ? ? 500 1 249 2 124 2 249 ? ? 3 101 3 124 3 140 3 155 ? ? 1k 1 124 1 249 2 124 ? ? 2 202 2 249 3 69 3 77 3 97 2.5k 0 199 1 99 1 199 1 249 2 80 2 99 2 112 2 124 2 155 5k 0 99 0 199 1 99 1 124 1 162 1 199 1 224 1 249 2 77 10k 0 49 0 99 0 199 0 249 1 80 1 99 1 112 1 124 1 155 25k 0 19 0 39 0 79 0 99 0 129 0 159 0 179 0 199 0 249 50k 0 9 0 19 0 39 0 49 0 64 0 79 0 89 0 99 0 124 100k 0 4 0 9 0 19 0 24 ? ? 0 39 0 44 0 49 0 62 250k 0 1 0 3 0 7 0 9 0 12 0 15 0 17 0 19 0 24 500k 0 0 * 0 1 0 3 0 4 ? ? 0 7 0 8 0 9 ? ? 1m 0 0 * 0 1 ? ? ? ? 0 3 0 4 0 4 ? ? 2m 0 0 * ? ? ? ? 0 1 ? ? ? ? ? ? 2.5m ? ? 0 0 * ? ? ? ? ? ? ? ? ? ? 4m 0 0 * ? ? ? ? ? ? legend: blank: no setting available ? : setting possible, but error occurs * : continuous transmission/reception not possible note: settings with an error of 1 % or less are recommended. 12. serial communication interface rev.4.00 aug. 20, 2007 page 347 of 638 rej09b0395-0400 the brr setting is calculated as follows: asynchronous mode: n = 64 2 2n ? 1 b 10 6 ? 1 synchronous mode: n = 8 2 2n ? 1 b 10 6 ? 1 legend: b: bit rate (bit/s) n: brr setting for baud rate generator (0 n 255) : system clock frequency (mhz) n: baud rate generator input clock (n = 0, 1, 2, 3) (for the clock sources and values of n, see the following table.) smr settings n clock source cks1 cks0 0 0 0 1 /4 0 1 2 /16 1 0 3 /64 1 1 the bit rate error in asynchronous mode is calculated as follows: error ( % ) = (n + 1) b 64 2 2n ? 1 ? 1 100 10 6 12. serial communication interface rev.4.00 aug. 20, 2007 page 348 of 638 rej09b0395-0400 table 12.5 shows the maximum bit rates in asynchronous mode for various system clock frequencies. tables 12.6 and 12.7 show the maximum bit rates with external clock input. table 12.5 maximum bit rates for vari ous frequencies (asynchronous mode) settings (mhz) maximum bit rate (bit/s) n n 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 5 156250 0 0 6 187500 0 0 6.144 192000 0 0 7.3728 230400 0 0 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 17.2032 537600 0 0 18 562500 0 0 20 625000 0 0 25 781250 0 0 12. serial communication interface rev.4.00 aug. 20, 2007 page 349 of 638 rej09b0395-0400 table 12.6 maximum bit rates with external clock input (asynchronous mode) (mhz) external input clock (m hz) maximum bit rate (bit/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 5 1.2500 78125 6 1.5000 93750 6.144 1.5360 96000 7.3728 1.8432 115200 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 12 3.0000 187500 12.288 3.0720 192000 14 3.5000 218750 14.7456 3.6864 230400 16 4.0000 250000 17.2032 4.3008 268800 18 4.5000 281250 20 5.0000 312500 25 6.2500 390625 12. serial communication interface rev.4.00 aug. 20, 2007 page 350 of 638 rej09b0395-0400 table 12.7 maximum bit rates with external clock input (synchronous mode) (mhz) external input clock (m hz) maximum bit rate (bit/s) 2 0.3333 333333.3 4 0.6667 666666.7 6 1.0000 1000000.0 8 1.3333 1333333.3 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3 25 4.1667 4166666.7 12.3 operation 12.3.1 overview the sci can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. a sm art card interface is also supported as a serial communication function for an ic card interface. selection of asynchronous or synchronous mode and the transmission format for the normal serial communication interface is made in smr, as s hown in table 12.8. the sci clock source is selected by the c/ a bit in smr and the cke1 and cke0 bits in scr, as shown in table 12.9. for details of the procedures for switching between lsb-first and msb-first mode and inverting the data logic level, see section 13.2.1, smart card mode register (scmr). for selection of the smart card interface format, see section 13.3.3, data format. 12. serial communication interface rev.4.00 aug. 20, 2007 page 351 of 638 rej09b0395-0400 asynchronous mode ? data length is selectable: 7 or 8 bits ? parity and multiprocessor bits are selectable, and so is the stop bit length (1 or 2 bits). these selections determine the communica tion format and character length. ? in receiving, it is possible to de tect framing errors, parity errors, overrun errors, and the break state. ? an internal or external clock can be selected as the sci clock source. ? when an internal clock is selected, the sci operates using the on-chip baud rate generator, and can output a serial clock signal with a frequency matching the bit rate. ? when an external clock is sel ected, the external clock input must have a frequency 16 times the bit rate. (the on-chip baud rate generator is not used.) synchronous mode ? the communication format has a fixed 8-bit data length. ? in receiving, it is possible to detect overrun errors. ? an internal or external clock can be selected as the sci clock source. ? when an internal clock is selected, the sci operates using the on-chip baud rate generator, and can output a serial clock signal to external devices. ? when an external clock is selected, the sci operates on the input serial clock. the on-chip baud rate generator is not used. smart card interface ? one frame consists of 8-bit data and a parity bit. ? in transmitting, a guard time of at least two elementary time units (2 etu) is provided between the end of the parity bit and the start of he next frame. (an elementary time unit is the time required to transmit one bit.) ? in receiving, if a parity error is detected, a lo w error signal level is out put for 1 etu, beginning 10.5 etu after the start bit.. ? in transmitting, if an error signal is received, the same data is automatically transmitted again after at least 2 etu. ? only asynchronous communication is supported. there is no synchronous communication function. for details of smart card interface operation, see section 13, smart card interface. 12. serial communication interface rev.4.00 aug. 20, 2007 page 352 of 638 rej09b0395-0400 table 12.8 smr settings and serial communication formats smr settings sci communication format bit 7 c/ a bit 6 chr bit 2 mp bit 5 pe bit 3 stop mode data length multi- processor bit parity bit stop bit length 0 0 0 0 0 8-bit data absent absent 1 bit 1 2 bits 1 0 asyn- chronous mode present 1 bit 1 2 bits 1 0 0 7-bit data absent 1 bit 1 2 bits 1 0 present 1 bit 1 2 bits 0 1 ? 0 8-bit data present absent 1 bit ? 1 2 bits 1 ? 0 7-bit data 1 bit ? 1 asyn- chronous mode (multi- processor format) 2 bits 1 ? ? ? ? syn- chronous mode 8-bit data absent none table 12.9 smr and scr settings and sci clock so urce selection smr scr setting sci transmit/receive clock bit 7 c/ a bit 1 cke1 bit 0 cke0 mode clock source sck pin function 0 0 0 internal sci does not use the sck pin 1 asynchronous mode outputs clock with frequency matching the bit rate 1 0 external 1 inputs clock with frequency 16 times the bit rate 1 0 0 internal outputs the serial clock 1 synchronous mode 1 0 external inputs the serial clock 1 12. serial communication interface rev.4.00 aug. 20, 2007 page 353 of 638 rej09b0395-0400 12.3.2 operation in asynchronous mode in asynchronous mode, each transmitted or received character begins with a start bit and ends with one or two stop bits. serial communication is synchronized one character at a time. the transmitting and receiving sections of the sci are independent, so full-duplex communication is possible. the transmitter and the receiver are bo th double-buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. figure 12.2 shows the general format of asynchronous serial communication. in asynchronous serial communication the communicati on line is normally held in the mark (high) state. the sci monitors the line and starts se rial communication when the line goes to the space (low) state, indicating a start bit. one serial character consists of a start bit (low), data (lsb first), parity bit (high or low), and one or two stop bits (high), in that order. when receiving in asynchronous mode, the sci synchr onizes at the falling edge of the start bit. the sci samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. receive data is latched at the center of each bit. 1 d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 idle (mark) state 1 (msb) (lsb) 0 1 serial data start bit 1 bit transmit or receive data 7 or 8 bits one unit of data (character or frame) 1 bit, or none parity bit 1 or 2 bits stop bit(s) figure 12.2 data format in asynchronous communication (example: 8-bit data with parity and 2 stop bits) communication formats: table 12.10 shows the 12 communica tion formats that can be selected in asynchronous mode. the format is selected by settings in smr. 12. serial communication interface rev.4.00 aug. 20, 2007 page 354 of 638 rej09b0395-0400 table 12.10 serial communication formats (asynchronous mode) 7-bit data stop stop mpb stop mpb stop p stop stop p stop stop smr settin g s chr pe mp stop 00 0 0 00 0 1 01 0 0 01 0 1 10 0 0 10 0 1 11 0 0 11 0 1 0 ? 10 0 ? 11 1 ? 10 1 ? 11 serial communication format and frame len g th 123456789101112 stop 8-bit data s 8-bit data s stop p 8-bit data s 8-bit data s stop 7-bit data s 7-bit data s 7-bit data s s 8-bit data s stop stop mpb 8-bit data s 7-bit data s 7-bit data s p stop stop stop stop stop mpb legend: s: start bit stop: stop bit p: parity bit mpb: multiprocessor bit 12. serial communication interface rev.4.00 aug. 20, 2007 page 355 of 638 rej09b0395-0400 clock: an internal clock generated by the on-chip ba ud rate generator or an external clock input from the sck pin can be selected as the sci tran smit/receive clock. the clock source is selected by the c/ a bit in smr and bits cke1 and cke0 in scr. for details of sci clock source selection, see table 12.9. when an external clock is input at the sck pin, it must have a frequency 16 times the desired bit rate. when the sci is operated on an internal clock, it can output a clock signal at the sck pin. the frequency of this output clock is equal to the bit rate. the phase is aligned as shown in figure 12.3 so that the rising edge of the clock occurs at the center of each transmit data bit. d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 0 1 frame figure 12.3 phase relationship between output clock and serial data (asynchronous mode) transmitting and receiving data: ? sci initialization (asynchronous mode): before transmitting or receiving data, clear the te and re bits to 0 in scr, then initialize the sci as follows. when changing the communication mode or form at, always clear the te and re bits to 0 before following the procedure given below. clearing te to 0 sets the tdre flag to 1 and initializes tsr. clearing re to 0, however, does not initialize the rdrf, per, fer, and orer flags, or rdr, which retain their previous contents. when an external clock is used the clock should not be stopped during initialization or subsequent operation, since operation will be unreliable in this case. 12. serial communication interface rev.4.00 aug. 20, 2007 page 356 of 638 rej09b0395-0400 figure 12.4 shows a sample flowchart for initializing the sci. start of initialization set value in brr select communication format in smr 1-bit interval elapsed? wait (4) (3) (2) (1) yes no 12. serial communication interface rev.4.00 aug. 20, 2007 page 357 of 638 rej09b0395-0400 ? transmitting serial data (asynchronous mode): figure 12.5 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. yes yes 12. serial communication interface rev.4.00 aug. 20, 2007 page 358 of 638 rej09b0395-0400 in transmitting serial data, the sci operates as follows: ? the sci monitors the tdre flag in ssr. when the tdre flag is cleared to 0, the sci recognizes that tdr contains new data, and loads this data from tdr into tsr. ? after loading the data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmitting. if the tie bit is set to 1 in scr, the sci requests a transmit-data-empty interrupt (txi) at this time. serial transmit data is transmitted in the following order from the txd pin: ? start bit: one 0 bit is output. ? transmit data: 7 or 8 bits are output, lsb first. ? parity bit or multiprocessor bit: one parity bit (even or odd parity), or one multiprocessor bit is output. formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. ? stop bit(s): one or two 1 bits (stop bits) are output. ? mark state: output of 1 bits continues until the start bit of the next transmit data. ? the sci checks the tdre flag wh en it outputs the stop bit. if the tdre flag is 0, the sci loads new data from tdr into tsr, outputs the stop bit, then begins serial transmission of the next frame. if the tdre flag is 1, the sci sets the tend flag to 1 in ssr, outputs the stop bit, then continues output of 1 bits in the mark state. if the teie bit is set to 1 in scr, a transmit- end interrupt (tei) is requested at this time figure 12.6 shows an example of sci transmit operation in asynchronous mode. 0/1 d0 d1 d7 0/1 1 1 0 start bit 0d0d1 d7 1 1 data parity bit stop bit start bit data parity bit stop bit tdre tend idle state (mark state) tei interrupt request txi interrupt request txi interrupt handler writes data in tdr and clears tdre fla g to 0 txi interrupt request 1 frame figure 12.6 example of sci transmit operation in asynchronous mode (8-bit data with parity and one stop bit) 12. serial communication interface rev.4.00 aug. 20, 2007 page 359 of 638 rej09b0395-0400 ? receiving serial data (asynchr onous mode): figure 12.7 s hows a sample flowchart for receiving serial data and indicates the procedure to follow. yes yes no no 12. serial communication interface rev.4.00 aug. 20, 2007 page 360 of 638 rej09b0395-0400 yes 12. serial communication interface rev.4.00 aug. 20, 2007 page 361 of 638 rej09b0395-0400 in receiving, the sci operates as follows: ? the sci monitors the communication line. when it detects a start bit (0 bit), the sci synchronizes internally and starts receiving. ? receive data is stored in rsr in order from lsb to msb. ? the parity bit and stop bit are received. after receiving these bits, the sci carries out the following checks: ? parity check: the number of 1s in the receive data must match the even or odd parity setting of in the o/ e bit in smr. ? stop bit check: the stop bit value must be 1. if there are two stop bits, only the first is checked. ? status check: the rdrf flag must be 0, indica ting that the receive data can be transferred from rsr into rdr. if these all checks pass, the rdrf fl ag is set to 1 and the received data is stored in rdr. if one of the checks fails (receive error*), the sci operates as shown in table 12.11. note: * when a receive error occurs, further receiving is disabled. in receiving, the rdrf flag is not set to 1. be sure to clear the error flags to 0. ? when the rdrf flag is set to 1, if the rie bit is set to 1 in scr, a receive-data-full interrupt (rxi) is requested. if the orer, per, or fer flag is set to 1 and the rie bit in scr is also set to 1, a receive-error interrupt (eri) is requested. table 12.11 receive error conditions receive error abbreviation condition data transfer overrun error orer receiving of next data ends while rdrf flag is still set to 1 in ssr receive data is not transferred from rsr to rdr framing error fer stop bit is 0 receive data is transferred from rsr to rdr parity error per parity of received data differs from even/odd parity setting in smr receive data is transferred from rsr to rdr 12. serial communication interface rev.4.00 aug. 20, 2007 page 362 of 638 rej09b0395-0400 figure 12.8 shows an example of sci r eceive operation in asynchronous mode. 0/1 d0 d1 d7 0/1 1 1 0 start bit 0d0d1 d7 1 1 data data parity bit parity bit stop bit stop bit start bit rdrf fer idle (mark) state framin g error, eri interrupt request rxi interrupt request rxi interrupt handler reads data in rdr and clears rdrf fla g to 0 1 frame figure 12.8 example of sci receive operation (8-bit data with parity and one stop bit) 12.3.3 multiprocessor communication the multiprocessor communication function enables several processors to share a single serial communication line. the processors communicate in asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). in multiprocessor communication, each receiving processor is addressed by an id. a serial communication cycle consists of an id-sending cycl e that identifies the receiving processor, and a data-sending cycle. the multiprocessor bit disti nguishes id-sending cycl es from data-sending cycles. the transmitting processor starts by sending the id of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. when they receive data with the multiprocessor bit set to 1, receiving processors compare the data with their ids. processors with ids not matching the received data skip further incoming data until they again receive data with the multiprocessor bit set to 1. multiple processors can send and receive data in this way. figure 12.9 shows an example of communication among different processors using a multiprocessor format. 12. serial communication interface rev.4.00 aug. 20, 2007 page 363 of 638 rej09b0395-0400 communication formats: four formats are available. parity bit settings are ignored when a multiprocessor format is selected. for details see table 12.10. clock: see the description of asynchronous mode. (id = 04) (id = 01) (id = 02) (id = 03) transmittin g processor receivin g processor b receivin g processor a receivin g processor c receivin g processor d h'01 (mpb = 1) serial data h'aa (mpb = 0) serial communication line id-sendin g cycle: receivin g processor address data-sendin g cycle: data sent to receivin g processor specified by id le g end: mpb : multiprocessor bit figure 12.9 example of communication among processors using multiprocessor format (sending data h'aa to receiving processor a) transmitting and receiving data: ? transmitting multiprocessor serial data: figure 12.10 shows a sample flowchart for transmitting multiprocessor serial data and indicates the procedure to follow. 12. serial communication interface rev.4.00 aug. 20, 2007 page 364 of 638 rej09b0395-0400 tend = 1 no no read tend fla g in ssr yes yes yes yes no no 12. serial communication interface rev.4.00 aug. 20, 2007 page 365 of 638 rej09b0395-0400 in transmitting serial data, the sci operates as follows: ? the sci monitors the tdre flag in ssr. when the tdre flag is cleared to 0, the sci recognizes that tdr contains new data, and loads this data from tdr into tsr. ? after loading the data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmitting. if the tie bit is set to 1 in scr, the sci requests a transmit-data-empty interrupt (txi) at this time. serial transmit data is transmitted in the following order from the txd pin: ? start bit: one 0 bit is output. ? transmit data: 7 or 8 bits are output, lsb first. ? multiprocessor bit: one multiprocessor bit (mpbt value) is output. ? stop bit(s): one or two 1 bits (stop bits) are output. ? mark state: output of 1 bits continues until the start bit of the next transmit data. ? the sci checks the tdre flag wh en it outputs the stop bit. if the tdre flag is 0, the sci loads new data from tdr into tsr, outputs the stop bit, then begins serial transmission of the next frame. if the tdre flag is 1, the sci sets the tend flag to 1 in ssr, outputs the stop bit, then continues output of 1 bits in the mark state. if the teie bit is set to 1 in scr, a transmit- end interrupt (tei) is requested at this time figure 12.11 shows an example of sci transmit operation using a multiprocessor format. d0 d1 d7 0/1 1 1 0 start bit 0 d0 d1 d7 0/1 1 data multi- processor bit stop bit start bit data multi- processor bit stop bit tdre tend idle (mark) state tei interrupt request txi interrupt request txi interrupt handler writes data in tdr and clears tdre fla g to 0 txi interrupt request 1 frame figure 12.11 example of sci transmit operation (8-bit data with multiprocessor bit and one stop bit) ? receiving multiprocessor serial data: figure 12.12 shows a sample flowchart for receiving multiprocessor serial data and indicates the procedure to follow. 12. serial communication interface rev.4.00 aug. 20, 2007 page 366 of 638 rej09b0395-0400 read rdrf fla g in ssr no yes yes yes no yes yes no no no read orer and fer fla g s in ssr (3) (1) (2) (4) (1) (2) (3) (4) (5) rdrf = 1 fer orer = 1 fer orer = 1 start receivin g own id? 12. serial communication interface rev.4.00 aug. 20, 2007 page 367 of 638 rej09b0395-0400 yes yes no no 12. serial communication interface rev.4.00 aug. 20, 2007 page 368 of 638 rej09b0395-0400 figure 12.13 shows an example of sci receive operation using a multiprocessor format. id2 data2 idle (mark) state not own id, so mpie bit is set to 1 a g ain a. own id does not match data b. own id matches data d0 d1 d7 1 1 0 start bit start bit stop bit stop bit 0 d0 d1 d7 0 1 1 data (id1) data (data1) start bit stop bit stop bit data (data2) mpie idle (mark) state 1 mpb rdrf rdr value rdr value rxi interrupt request (multiprocessor interrupt) rxi interrupt handler reads rdr data and clears rdrf fla g to 0 no rxi interrupt request, rdr not updated id1 mpb d0 d1 d7 1 1 0 start bit 0 d0 d1 d7 0 1 1 data (id2) mpie 1 mpb rdrf rxi interrupt request (multiprocessor interrupt) mpb detection mpie = 0 rxi interrupt handler reads rdr data and clears rdrf fla g to 0 own id, so receivin g continues, with data received by rxi interrupt handler mpb id1 mpie bit is set to 1 a g ain mpb detection mpie = 0 figure 12.13 example of sci receive operation (8-bit data with multiprocessor bit and one stop bit) 12. serial communication interface rev.4.00 aug. 20, 2007 page 369 of 638 rej09b0395-0400 12.3.4 synchronous operation in synchronous mode, the sci transmits and receive s data in synchronization with clock pulses. this mode is suitable for high-speed serial communication. the sci transmitter and receiver share the same clock but are otherwise independent, so full- duplex communication is possible. the transmitter and the receiver are also double-buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. figure 12.14 shows the general format in synchronous serial communication. don't care one unit (character or frame) of transfer data msb bit 0 bit 1 bit 3 bit 2 bit 4 bit 5 bit 6 bit 7 lsb don't care serial clock serial data * * note: * hi g h except in continuous transmittin g or receivin g figure 12.14 data format in synchronous communication in synchronous serial communica tion, each data bit is placed on the communication line from one falling edge of the serial clock to the next. data is guaranteed valid at the rise of the serial clock. in each character, the serial data bits are transferred in order from lsb (first) to msb (last). after output of the msb, the communication line remains in the state of the msb. in synchronous mode the sci receives data by synchronizing w ith the rise of the serial clock. communication format: the data length is fixed at 8 bits. no parity bit or multiprocessor bit can be added. clock: an internal clock generated by the on-chip ba ud rate generator or an external clock input from the sck pin can be selected by means of the c/ a bit in smr and the cke1 and cke0 bits in scr. see table 12.6 for details of sci clock source selection. when the sci operates on an internal clock, it outputs the clock source at the sck pin. eight clock pulses are output per transmitted or receive d character. when the sci is not transmitting or receiving, the clock signal remains in the high st ate. if receiving in single-character units is required, an external clock should be selected. 12. serial communication interface rev.4.00 aug. 20, 2007 page 370 of 638 rej09b0395-0400 transmitting and receiving data: ? sci initialization (synchronous mode): before tr ansmitting or receiving data, clear the te and re bits to 0 in scr, then initialize the sci as follows. when changing the communication mode or form at, always clear the te and re bits to 0 before following the procedure given below. clearing te to 0 sets the tdre flag to 1 and initializes tsr. clearing re to 0, however, does not initialize the rdrf, per, fer, and orer flags, or rdr, which retain their previous contents. figure 12.15 shows a sample flowchart for initializing the sci. 12. serial communication interface rev.4.00 aug. 20, 2007 page 371 of 638 rej09b0395-0400 ? transmitting serial data (synchronous mode): figure 12.16 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. 12. serial communication interface rev.4.00 aug. 20, 2007 page 372 of 638 rej09b0395-0400 in transmitting serial data, the sci operates as follows. ? the sci monitors the tdre flag in ssr. when the tdre flag is cleared to 0, the sci recognizes that tdr contains new data, and loads this data from tdr into tsr. ? after loading the data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmitting. if the tie bit is set to 1 in scr, the sci requests a transmit-data-empty interrupt (txi) at this time. if clock output is selected, the sci outputs eight serial clock pulses. if an external clock source is selected, the sci outputs data in synchronization with the input clock. data is output from the txd pin in order from lsb (bit 0) to msb (bit 7). ? the sci checks the tdre fl ag when it outputs the msb (bit 7). if the tdre flag is 0, the sci loads data from tdr into tsr and begins serial transmission of the next frame. if the tdre flag is 1, the sci sets the tend flag to 1 in ssr, and after transmitting the msb, holds the txd pin in the msb state. if the teie bit is set to 1 in scr, a transmit-end interrupt (tei) is requested at this time ? after the end of serial transmission, the sck pin is held in a constant state. figure 12.17 shows an example of sci transmit operation. bit 0 bit 1 bit 7 bit 0 bit 1 bit 6 bit 7 serial clock serial data 1 frame txi interrupt request txi interrupt handler writes data in tdr and clears tdre fla g to 0 txi interrupt request tei interrupt request transmit direction tend tdre figure 12.17 example of sci transmit operation 12. serial communication interface rev.4.00 aug. 20, 2007 page 373 of 638 rej09b0395-0400 ? receiving serial data (synchr onous mode): figure 12.18 shows a sample flowchart for receiving serial data an d indicates the procedure to follo w. when switching from asynchronous to synchronous mode, make sure that the orer, per, and fer flags are cleared to 0. if the fer or per flag is set to 1 the rdrf flag will not be set and both transmitting and receiving will be disabled. yes yes no no 12. serial communication interface rev.4.00 aug. 20, 2007 page 374 of 638 rej09b0395-0400 12. serial communication interface rev.4.00 aug. 20, 2007 page 375 of 638 rej09b0395-0400 figure 12.19 shows an example of sci receive operation. serial clock serial data rxi interrupt handler reads data in rdr and clears rdrf fla g to 0 rxi interrupt request rxi interrupt request overrun error, eri interrupt request orer rdrf bit 7 bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 1 frame figure 12.19 example of sci receive operation 12. serial communication interface rev.4.00 aug. 20, 2007 page 376 of 638 rej09b0395-0400 ? transmitting and receiving data simultaneously (synchronous mode): figure 12.20 shows a sample flowchart for transmitting and receiving serial data simultaneously and indicates the procedure to follow. yes no no 12. serial communication interface rev.4.00 aug. 20, 2007 page 377 of 638 rej09b0395-0400 12.4 sci interrupts the sci has four interrupt request sources: tran smit-end interrupt (tei), receive-error (eri), receive-data-full (rxi), and transm it-data-empty interrupt (txi). table 12.12 lists the interrupt sources and indicates their priority. these interrupt s can be enabled or disabled by the tie, rie, and teie bits in scr. each interrupt request is sent separately to the interrupt controller. a txi interrupt is requested when the tdre flag is set to 1 in ssr. a tei interrupt is requested when the tend flag is set to 1 in ssr. an rxi interrupt is requested when the rdrf fl ag is set to 1 in ssr. an eri interrupt is requested when the orer, per, or fer flag is set to 1 in ssr. table 12.12 sci interrupt sources interrupt source description priority eri receive error (orer, fer, or per) high rxi receive data register full (rdrf) txi transmit data register empty (tdre) tei transmit end (tend) low 12. serial communication interface rev.4.00 aug. 20, 2007 page 378 of 638 rej09b0395-0400 12.5 usage notes 12.5.1 notes on use of sci note the following points when using the sci. tdr write and tdre flag: the tdre flag in ssr is a stat us flag indicating the loading of transmit data from tdr to tsr. the sci sets the tdre flag to 1 when it transfers data from tdr to tsr. data can be written into tdr regardless of the state of the tdre flag. if new data is written in tdr when the tdre flag is 0, the old data stored in tdr will be lost because this data has not yet been transferred to tsr. before writing transmit data in tdr, be sure to check that the tdre flag is set to 1. simultaneous multiple receive errors: table 12.13 shows the state of the ssr status flags when multiple receive errors occur simultaneously. when an overrun error occurs the rsr contents are not transferred to rdr, so receive data is lost. table 12.13 ssr status flags and transfer of receive data ssr status flags rdrf orer fer per receive data transfer rsr rdr receive errors 1 1 0 0 overrun error 0 0 1 0 framing error 0 0 0 1 parity error 1 1 1 0 overrun error + framing error 1 1 0 1 overrun error + parity error 0 0 1 1 framing error + parity error 1 1 1 1 overrun error + framing error + parity error legend: : receive data is transferred from rsr to rdr. : receive data is not transferred from rsr to rdr. 12. serial communication interface rev.4.00 aug. 20, 2007 page 379 of 638 rej09b0395-0400 break detection and processing: break signals can be detected by reading the rxd pin directly when a framing error (fer) is detected. in the break state the input from the rxd pin consists of all 0s, so the fer flag is set and the parity error flag (per) may also be set. in the break state the sci receiver continues to operate, so if the fer flag is cleared to 0 it will be set to 1 again. sending a break signal: the input/output condition and level of the txd pin are determined by dr and ddr bits. this feature can be used to send a break signal. after the serial transmitter is initialized, the dr value substitutes for the mark state until the te bit is set to 1 (the txd pin function is not sel ected until the te bit is set to 1). the ddr and dr bits should therefore be set to 1 beforehand. to send a break signal during serial transmission, clear the dr bit to 0 , then clear the te bit to 0. when the te bit is cleared to 0 the transmitter is initialized, regardless of its current state, so the txd pin becomes an input/output outputting the value 0. receive error flags and transmitter operation (s ynchronous mode only): when a receive error flag (orer, per, or fer) is set to 1 th e sci will not start transmitting, even if the tdre flag is cleared to 0. be sure to clear the receive error flags to 0 wh en starting to transmit. note that clearing the re bit to 0 does not cl ear the receive error flags to 0. receive data sampling timing in asyn chronous mode and receive margin: in asynchronous mode the sci operates on a base clock with 16 times the bit rate frequency. in receiving, the sci synchronizes internally with the fa ll of the start bit, which it sa mples on the base clock. receive data is latched at the rising edge of the eighth base clock pulse. see figure 12.21. 15 0 internal base clock 8 clocks 7 0 receive data (rxd) synchronization samplin g timin g data samplin g timin g 15 0 d 0 d 1 start bit 16 clocks 7 figure 12.21 receive data samplin g timing in asynchronous mode 12. serial communication interface rev.4.00 aug. 20, 2007 page 380 of 638 rej09b0395-0400 the receive margin in asynchronous mode can therefore be expressed as shown in equation (1). m = (0.5 ? 1 2n d ? 0.5 n ) ? (l ? 0.5) f ? (1 + f) 100 % . . . . . . . . (1) legend: m: receive margin ( % ) n: ratio of clock frequency to bit rate (n = 16) d: clock duty cycle (d = 0 to 1.0) l: frame length (l = 9 to 12) f: absolute deviation of clock frequency from equation (1), if f = 0 and d = 0.5, the receive margin is 46.875 % , as given by equation (2). when d = 0.5 and f = 0: m = (0.5 ? 2 16 ) 100 % 1 = 46.875 % . . . . . . . . (2) this is a theoretical value. a reasonable margin to allow in system designs is 20 % to 30 % . restrictions on use of an external clock source: ? when an external clock source is used for the serial clock, after updates tdr, allow an inversion of at least five system clock ( ) cycles before input of the serial clock to start transmitting. if the serial clock is input within four states of the tdr update, a malfunction may occur. (see figure 12.22) sck d0 d1 d2 d3 d4 d5 d6 d7 tdre t note: in operation with an external clock source, be sure that t >4 states. figure 12.22 example of synchronous transmission 12. serial communication interface rev.4.00 aug. 20, 2007 page 381 of 638 rej09b0395-0400 switching from sck pin function to port pin function: ? problem in operation: when switching the sck pin function to the output port function (high- level output) by making the following settings while ddr = 1, dr = 1, c/ a = 1, cke1 = 0, cke0 = 0, and te = 1 (synchronous mode), low-level output occurs for one half-cycle. 1. end of serial data transmission 2. te bit = 0 3. c/ a bit = 0 ... switchover to port output 4. occurrence of low-level output (see figure 12.23) sck/port data te c/ a cke1 cke0 bit 7 bit 6 1. end of transmission 4. low-level output 3.c/ a = 0 2.te = 0 half-cycle low-level output figure 12.23 operation when switching from sck pin function to port pin function 12. serial communication interface rev.4.00 aug. 20, 2007 page 382 of 638 rej09b0395-0400 ? sample procedure for avoiding low-level output: as this sample procedure temporarily places the sck pin in the input state, the sck/por t pin should be pulled up beforehand with an external circuit. with ddr = 1, dr = 1, c/ a = 1, cke1 = 0, cke0 = 0, and te = 1, make the following settings in the order shown. 1. end of serial data transmission 2. te bit = 0 3. cke1 bit = 1 4. c/ a bit = 0 ... switchover to port output 5. cke1 bit = 0 sck/port data te c/ a cke1 cke0 bit 7 bit 6 1. end of transmission 3.cke1 = 1 5.cke1 = 0 4.c/ a = 0 2.te = 0 hi g h-level outputte figure 12.24 operation when switching from sck pin function to port pin function (example of preventing low-level output) 13. smart card interface rev.4.00 aug. 20, 2007 page 383 of 638 rej09b0395-0400 section 13 smart card interface 13.1 overview the sci supports an ic card (smart card) interface handling iso/iec7816-3 (identification card) character transmission as a serial co mmunication interface expansion function. switchover between the normal serial communicati on interface and the smart card interface is controlled by a register setting. 13.1.1 features features of the smart card interface supp orted by the h8/3008 are listed below. ? asynchronous communication ? data length: 8 bits ? parity bit generation and checking ? transmission of error signal (parity error) in receive mode ? error signal detection and automatic data retransmission in transmit mode ? direct convention and inverse convention both supported ? built-in baud rate generator allows any bit rate to be selected ? three interrupt sources ? there are three interrupt sources?transmit-data-empty, receive-data-full, and transmit/receive error?that can issue requests independently. 13. smart card interface rev.4.00 aug. 20, 2007 page 384 of 638 rej09b0395-0400 13.1.2 block diagram figure 13.1 shows a block diagram of the smart card interface. bus interface tdr rsr rdr module data bus tsr scmr ssr scr transmission/ reception control brr baud rate g enerator internal data bus rxd txd sck parity g eneration parity check clock external clock /4 /16 /64 txi rxi eri smr le g end: scmr: smart card mode re g ister rsr: receive shift re g ister rdr: receive data re g ister tsr: transmit shift re g ister tdr: transmit data re g ister smr: serial mode re g ister scr: serial control re g ister ssr: serial status re g ister brr: bit rate re g ister figure 13.1 block diagram of smart card interface 13. smart card interface rev.4.00 aug. 20, 2007 page 385 of 638 rej09b0395-0400 13.1.3 pin configuration table 13.1 shows the smart card interface pins. table 13.1 smart card interface pins pin name abbreviation i/o function serial clock pin sck i/o clock input/output receive data pin rxd input receive data input transmit data pin txd output transmit data output 13.1.4 register configuration the smart card interface has the internal registers listed in table 13.2. the brr, tdr, and rdr registers have their normal seri al communication interface functions , as described in section 12, serial communication interface. table 13.2 smart card interface registers channel address * 1 name abbreviation r/w initial value 0 h'fffb0 serial mode register smr r/w h'00 h'fffb1 bit rate register brr r/w h'ff h'fffb2 serial control register scr r/w h'00 h'fffb3 transmit data register tdr r/w h'ff h'fffb4 serial status register ssr r/(w) * 2 h'84 h'fffb5 receive data register rdr r h'00 h'fffb6 smart card mode register scmr r/w h'f2 1 h'fffb8 serial mode register smr r/w h'00 h'fffb9 bit rate register brr r/w h'ff h'fffba serial control register scr r/w h'00 h'fffbb transmit data register tdr r/w h'ff h'fffbc serial status register ssr r/(w) * 2 h'84 h'fffbd receive data register rdr r h'00 h'fffbe smart card mode register scmr r/w h'f2 notes: 1. lower 20 bits of the address in advanced mode. 2. only 0 can be written in bits 7 to 3, to clear the flags. 13. smart card interface rev.4.00 aug. 20, 2007 page 386 of 638 rej09b0395-0400 13.2 register descriptions this section describes the new or modified registers and bit functi ons in the smart card interface. 13.2.1 smart card mode register (scmr) scmr is an 8-bit readable/writable register that selects smart card interface functions. 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 sdir 0 r/w 0 smif 0 r/w 2 sinv 0 r/w 1 ? 1 ? bit initial value read/write reserved bits reserved bit smart c ard interfa c e mode sele c t enables or disables the smart card interface function smart c ard data invert inverts data lo g ic levels smart c ard data transfer dire c tion selects the serial/parallel conversion format scmr is initialized to h'f2 by a reset and in standby mode. bits 7 to 4?reserved: read-only bits, always read as 1. bit 3?smart card data transfer direction (sdir): selects the serial/parallel conversion format.* 1 bit 3 sdir description 0 tdr contents are transmitted lsb-first (initial value) receive data is stored lsb-first in rdr 1 tdr contents are transmitted msb-first receive data is stored msb-first in rdr 13. smart card interface rev.4.00 aug. 20, 2007 page 387 of 638 rej09b0395-0400 bit 2?smart card data invert (sinv): specifies inversion of the data logic level. this function is used in combination with the sdir bit to communicate with inverse-convention cards.* 2 the sinv bit does not affect the logic level of the parity bit. for parity settings, see section 13.3.4, register settings. bit 2 sinv description 0 unmodified tdr contents are transmitted (initial value) receive data is stored unmodified in rdr 1 inverted tdr contents are transmitted receive data is inverted before storage in rdr bit 1?reserved: read-only bit, always read as 1. bit 0?smart card interface mode select (smif): enables the smart car d interface function. bit 0 smif description 0 smart card interface function is disabled (initial value) 1 smart card interface function is enabled notes: 1. the function for switching between lsb-first and msb-first mode can also be used with the normal serial communication inte rface. note that when the communication format data length is set to 7 bits and msb-first mode is selected for the serial data to be transferred, bit 0 of tdr is not transmitted, and only bits 7 to 1 of the received data are valid. 2. the data logic level inversion function can also be used with the normal serial communication interface. note th at, when inverting the serial data to be transferred, parity transmission and parity checking is based on the number of high-level periods at the serial data i/o pin, and not on the register value. 13. smart card interface rev.4.00 aug. 20, 2007 page 388 of 638 rej09b0395-0400 13.2.2 serial status register (ssr) the function of ssr bit 4 is modified in smart ca rd interface mode. this change also causes a modification to the setting conditions for bit 2 (tend). 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 ers 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r bit initial value read/write transmit end status fla g indicatin g end of transmission error signal status (ers) status fla g indicatin g that an error si g nal has been received note: * only 0 can be written, to clear the fla g . bits 7 to 5: these bits operate as in normal serial co mmunication. for details see section 12.2.7, serial status register (ssr). bit 4?error signal status (ers): in smart card interface mode, this flag indicates the status of the error signal sent from the receiving device to the transmitting device. the smart card interface does not detection framing errors. bit 4 ers description 0 indicates normal transmission, with no error signal returned (initial value) [clearing conditions] ? the chip is reset, or enters standby mode or module stop mode ? software reads ers while it is set to 1, then writes 0. 1 indicates that the receiving device sent an error signal reporting a parity error [setting condition] a low error signal was sampled. note: clearing the te bit to 0 in scr does not affect the ers flag, which retains its previous value. 13. smart card interface rev.4.00 aug. 20, 2007 page 389 of 638 rej09b0395-0400 bits 3 to 0: these bits operate as in normal serial co mmunication. for details see section 12.2.7, serial status register (ssr). the setting conditions for transmit end (tend), however, are modified as follows. bit 2 tend description 0 transmission is in progress [clearing condition] software reads tdre while it is set to 1, then writes 0 in the tdre flag. 1 end of transmission [setting conditions] (initial value) ? the chip is reset or enters standby mode. ? the te bit and fer/ers bit are both cleared to 0 in scr. ? tdre is 1 and fer/ers is 0 at a time 2.5 etu after the last bit of a 1-byte serial character is transmitted (normal transmission). note: an etu (elementary time unit) is the time needed to transmit one bit. 13.2.3 serial mode register (smr) the function of smr bit 7 is modified in smart card interface mode. this change also causes a modification to the function of bits 1 and 0 in the serial control register (scr). 7 gm 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w bit initial value read/write bit 7?gsm mode (gm): with the normal smart card interface, this bit is cleared to 0. setting this bit to 1 selects gsm mode, an additional mode for controlling the timing for setting the tend flag that indicates completion of transmission, and the type of clock output used. the details of the additional clock output control mode are specified by the cke1 and cke0 bits in the serial control register (scr). 13. smart card interface rev.4.00 aug. 20, 2007 page 390 of 638 rej09b0395-0400 bit 7 gm description 0 normal smart card interface mode operation ? the tend flag is set 12.5 etu after the beginning of the start bit. ? clock output on/off control only. (initial value) 1 gsm mode smart card interface mode operation ? the tend flag is set 11.0 etu after the beginning of the start bit. ? clock output on/off and fixed-high/fixed-low control. bits 6 to 0: these bits operate as in normal serial co mmunication. for details see section 12.2.5, serial mode register (smr). 13.2.4 serial control register (scr) the function of scr bits 1 and 0 is modified in smart card interface mode. 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w bit initial value read/write bits 7 to 2: these bits operate as in normal serial co mmunication. for details see section 12.2.6, serial control register (scr). bits 1 and 0?clock enable 1 and 0 (cke1, cke0): these bits select the sci clock source and enable or disable clock output from the sck pin. in smart card interface mode, it is possible to specify a fixed high level or fixed low level for the clock output, in addition to the usual switching between enabling and disabling of the clock output. bit 7 gm bit 1 cke1 bit 0 cke0 description 0 0 0 internal clock/sck pin is i/o port (initial value) 1 internal clock/sck pin is clock output 1 0 internal clock/sck pin is fixed at low output 1 internal clock/sck pin is clock output 1 0 internal clock/sck pin is fixed at high output 1 internal clock/sck pin is clock output 13. smart card interface rev.4.00 aug. 20, 2007 page 391 of 638 rej09b0395-0400 13.3 operation 13.3.1 overview the main features of the smar t card interface are as follows. ? one frame consists of 8-bit data plus a parity bit. ? in transmission, a guard time of at least 2 etu (elementary time units: the time for transfer of one bit) is provided between the end of the parity bit and the start of the next frame. ? if a parity error is detected during reception, a low error signal level is output for 1 etu period 10.5 etu after the start bit. ? if an error signal is detected during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer. ? only asynchronous communication is supported; there is no synchronous communication function. 13.3.2 pin connections figure 13.2 shows a pin connection diag ram for the smart card interface. in communication with a smart card, since both transmission and reception are carried out on a single data transmission line, the txd pin and rxd pin should both be connected to this line. the data transmission line should be pulled up to v cc with a resistor. when the smart card uses the clock generated on the smart card interface, the sck pin output is input to the clk pin of the smart card. if the smart card uses an internal clock, this connection is unnecessary. the reset signal should be output from one of the h8/3008's generic ports. in addition to these pin connections, power and ground connections will normally also be necessary. 13. smart card interface rev.4.00 aug. 20, 2007 page 392 of 638 rej09b0395-0400 txd rxd sck px (port) h8/3008 chip v cc i/o data line clock line reset line clk rst card-processin g device smart card figure 13.2 smart card interface connection diagram note: setting both te and re to 1 without connecting a smart card enables closed transmission/reception, allowing self -diagnosis to be carried out. 13.3.3 data format figure 13.3 shows the smart card interface data format . in reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting device to request retransmission of the data. in transmission, the error signal is sampled and the same data is retransmitted. 13. smart card interface rev.4.00 aug. 20, 2007 page 393 of 638 rej09b0395-0400 ds d0 d1 d2 d3 d4 d5 d6 d7 dp no parity error output from transmittin g device ds d0 d1 d2 d3 d4 d5 d6 d7 dp parity error output from transmittin g device de output from receivin g device le g end: ds: start bit d0 to d7: data bits dp: parity bit de: error si g nal figure 13.3 smart card interface data format the operating sequence is as follows. 1. when the data line is not in use it is in the high-impedance state, and is fixed high with a pull- up resistor. 2. the transmitting device starts transfer of one frame of data. the data frame starts with a start bit (ds, low-level), followed by 8 data bits (d0 to d7) and a parity bit (dp). 3. with the smart card interface, the data line then retu rns to the high-impedance state. the data line is pulled high with a pull-up resistor. 4. the receiving device carries out a parity check . if there is no parity error and the data is received normally, the receiving device waits for r eception of the next data. if a parity error occurs, however, the receiving device outputs an error signal (de, low-level) to request retransmission of the data. after outputting the error signal for the prescribed length of time, the receiving device places the signal line in the high-impedance state again. the signal line is pulled high again by a pull-up resistor. 5. if the transmitting device does not receive an er ror signal, it proceeds to transmit the next data frame. if it receives an error signal, however, it re turns to step 2 and transmits the same data again. 13. smart card interface rev.4.00 aug. 20, 2007 page 394 of 638 rej09b0395-0400 13.3.4 register settings table 13.3 shows a bit map of the registers used in the smart card interface. bits indicated as 0 or 1 must be set to the value shown. the setting of other bits is described in this section. table 13.3 smart card int erface register settings bit register address * 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 smr h'fffb0 gm 0 1 o/e 1 0 cks1 cks0 brr h'fffb1 brr7 brr6 brr5 b rr4 brr3 brr2 brr1 brr0 scr h'fffb2 tie rie te re 0 0 cke1 * 2 cke0 tdr h'fffb3 tdr7 tdr6 tdr5 t dr4 tdr3 tdr2 tdr1 tdr0 ssr h'fffb4 tdre rdrf orer ers per tend 0 0 rdr h'fffb5 rdr7 rdr6 rdr5 rdr4 rdr3 rdr2 rdr1 rdr0 scmr h'fffb6 ? ? ? ? sdir sinv ? smif legend: ?: unused bit. notes: 1. lower 20 bits of the address in advanced mode. 2. when gm is cleared to 0 in smr, the cke1 bit must also be cleared to 0. serial mode regist er (smr) settings: clear the gm bit to 0 when using the normal smart card interface mode, or set to 1 when using gsm mode. clear the o/ e bit to 0 if the smart card is of the direct convention type, or set to 1 if of the inverse convention type. bits cks1 and cks0 select the clock source of the built-in baud rate generator. see section 13.3.5, clock. bit rate register (brr) settings: brr is used to set the bit rate. see section 13.3.5, clock, for the method of calculating the value to be set. serial control register (scr) settings: the tie, rie, te, and re bits have their normal serial communication functions. see section 12, serial communication interface, for details. the cke1 and cke0 bits specify clock output. to disable clock output, clear these bits to 00; to enable clock output, set these bits to 01. clock output is performed when the gm bit is set to 1 in smr. clock output can also be fixed low or high. smart card mode register (scmr) settings: clear both the sdir bit and sinv bit cleared to 0 if the smart card is of the direct convention type, and set both to 1 if of the inverse convention type. to use the smart card inte rface, set the smif bit to 1. 13. smart card interface rev.4.00 aug. 20, 2007 page 395 of 638 rej09b0395-0400 the register settings and examples of starting character waveforms are shown below for two smart cards, one following the direct convention and one the inverse convention. 1. direct convention (sdir = sinv = o/ e = 0) ds d0 d1 d2 d3 d4 d5 d6 d7 dp azzazzzaaz (z) (z) state with the direct convention type, the logic 1 level corresponds to state z and the logic 0 level to state a, and transfer is performed in lsb-first order. in the example ab ove, the first character data is h'3b. the parity bit is 1, following the even parity rule designated for smart cards. 2. inverse convention (sdir = sinv = o/ e = 1) ds d7 d6 d5 d4 d3 d2 d1 d0 dp azzaaaaaaz (z) (z) state with the inverse convention type, the logic 1 level corresponds to state a and the logic 0 level to state z, and transfer is performed in ms b-first order. in the example above, the first character data is h'3f. the par ity bit is 0, corresponding to state z, following the even parity rule designated for smart cards. in the h8/3008, inversion specified by the sinv bit applies only to the data bits, d7 to d0. for parity bit inversion, the o/ e bit in smr must be set to odd parity mode. this applies to both transmission and reception. 13. smart card interface rev.4.00 aug. 20, 2007 page 396 of 638 rej09b0395-0400 13.3.5 clock only an internal clock generated by the on-c hip baud rate generator can be used as the transmit/receive clock for the smart card interface. the bit rate is set with the bit rate register (brr) and the cks1 and cks0 bits in the serial mode register (smr). the equation for calculating the bit rate is shown below. table 13.5 shows some sample bit rates. if clock output is selected with cke0 set to 1, a clock with a frequency of 372 times the bit rate is output from the sck pin. b = 1488 2 2n ? 1 (n + 1) 10 6 where, n: brr setting (0 n 255) b: bit rate (bit/s) : operating frequency (mhz) n: see table 13.4 table 13.4 n-values of cks1 and cks0 settings n cks1 cks0 0 0 0 1 1 2 1 0 3 1 note: if the gear function is used to divide the clock frequency, use the divided frequency to calculate the bit rate. the equation above applies directly to 1/1 frequency division. table 13.5 bit rates (bits/s) for various brr settings (when n = 0) (mhz) n 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00 25.00 0 9600.0 13440.9 14400.0 17473.1 19200.0 21505.4 24193.5 26881.7 33602.2 1 4800.0 6720.4 7200.0 8736.6 9600.0 10752.7 12096.8 13440.9 16801.1 2 3200.0 4480.3 4800.0 5824.4 6400.0 7168.5 8064.5 8960.6 11200.7 note: bit rates are rounded off to two decimal places. 13. smart card interface rev.4.00 aug. 20, 2007 page 397 of 638 rej09b0395-0400 the following equation calculates the bit rate register (brr) setting from the operating frequency and bit rate. n is an integer from 0 to 255, specifying the value with the smaller error. n = 1488 2 2n ? 1 b 10 6 ? 1 table 13.6 brr settings for typical bit rates (bits/s) (when n = 0) (mhz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00 25.00 bit/s n error n error n error n error n error n error n error n error n error 9600 0 0.00 1 30 1 25 1 8.99 1 0.00 1 12.01 2 15.99 2 6.66 3 12.49 table 13.7 maximum bit rates for various f requencies (smart ca rd interface mode) (mhz) maximum bit rate (bits/s) n n 7.1424 9600 0 0 10.00 13441 0 0 10.7136 14400 0 0 13.00 17473 0 0 14.2848 19200 0 0 16.00 21505 0 0 18.00 24194 0 0 20.00 26882 0 0 25.00 33602 0 0 the bit rate error is given by the following equation: error ( % ) = 1488 2 2n ? 1 b (n + 1) 10 6 ? 1 100 13. smart card interface rev.4.00 aug. 20, 2007 page 398 of 638 rej09b0395-0400 13.3.6 transmitting and receiving data initialization: before transmitting or receiving data, the sm art card interface must be initialized as described below. initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1. clear the te and re bits to 0 in the serial control register (scr). 2. clear error flags ers, per, and orer to 0 in the serial status register (ssr). 3. set the parity bit (o/ e ) and baud rate generator select bits (cks1 and cks0) in the serial mode register (smr). clear the c/ a , chr, and mp bits to 0, and set the stop and pe bits to 1. 4. set the smif, sdir, and sinv bits in the smart card mode register (scmr). when the smif bit is set to 1, the txd pin and rxd pin are both switched from port to sci pin functions and go to the high-impedance state. 5. set a value corresponding to the desired bit rate in the bit rate register (brr). 6. set the cke0 bit in scr. clear the tie, rie, te, re, mpie, teie, and cke1 bits to 0. if the cke0 bit is set to 1, the clock is output from the sck pin. 7. wait at least one bit interval, then set the tie, rie, te, and re bits in scr. do not set the te bit and re bit at the same time, except for self-diagnosis. transmitting serial data: as data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal sci. figure 13.5 shows a sample transmission processing flowchart. 1. perform smart card interface mode initializa tion as described in initialization above. 2. check that the ers error fl ag is cleared to 0 in ssr. 3. repeat steps 2 and 3 until it can be confirmed that the tend flag is set to 1 in ssr. 4. write the transmit data in tdr, clear the tdre flag to 0, and perform the transmit operation. the tend flag is cleared to 0. 5. to continue transmitting data, go back to step 2. 6. to end transmission, clear the te bit to 0. the above processing may include interrupt handling. if transmission ends and the tend flag is set to 1 while the tie bit is set to 1 and interrupt requests are enabled, a transmit-data-empty interrupt (txi) will be requested. if an error occurs in transmission and the ers flag is set to 1 while the rie bit is set to 1 and interrupt requests are enabled, a transmit/receive-error interrupt (eri) will be requested. the timing of tend flag setting depends on the gm bit in smr. 13. smart card interface rev.4.00 aug. 20, 2007 page 399 of 638 rej09b0395-0400 figure 13.4 shows timing of tend flag setting. for details, see interrupt operations in this section. serial data (1) gm = 0 tend (2) gm = 1 tend ds dp de guard time 11.0 etu 12.5 etu figure 13.4 timing of tend flag setting 13. smart card interface rev.4.00 aug. 20, 2007 page 400 of 638 rej09b0395-0400 initialization no yes clear te bit to 0 start transmittin g start no no no yes yes yes yes no end write transmit data in tdr, and clear tdre fla g to 0 in ssr error handlin g error handlin g tend = 1? all data transmitted? tend = 1? fer/ers = 0? fer/ers = 0? figure 13.5 sample transmission processing flowchart 13. smart card interface rev.4.00 aug. 20, 2007 page 401 of 638 rej09b0395-0400 1. data write tdr tsr (shift re g ister) data 1 2. transfer from tdr to tsr data 1 data 1 data remains in tdr data 1 3. serial data output note: when the ers fla g is set, it should be cleared until transfer of the last bit (d7 in lsb-first transmission, d0 in msb-first transmission) of the retransmit data to be transmitted next has been completed. in case of normal transmission: tend fla g is set in case of transmit error: ers fla g is set steps 2 and 3 above are repeated until the tend fla g is set. i/o si g nal output data 1 figure 13.6 relation between transmit operation and internal registers i/o data when gm = 0 guard time de ds da db dc dd de df d g dh dp 12.5 etu 11.0 etu when gm = 1 txi (tend interrupt) figure 13.7 timing of tend flag setting 13. smart card interface rev.4.00 aug. 20, 2007 page 402 of 638 rej09b0395-0400 receiving serial data: data reception in smart card mode uses the same processing procedure as for the normal sci. figure 13.8 shows a sample reception processing flowchart. 1. perform smart card interface mode initializa tion as described in initialization above. 2. check that the orer flag and per flag are cleared to 0 in ssr. if either is set, perform the appropriate receive error handling, then cl ear both the orer and the per flag to 0. 3. repeat steps 2 and 3 until it can be confirmed that the rdrf flag is set to 1. 4. read the receive data from rdr. 5. to continue receiving data, clear the rd rf flag to 0 and go back to step 2. 6. to end reception, clear the re bit to 0. initialization read rdr and clear rdrf fla g to 0 in ssr clear re bit to 0 start receivin g start error handlin g no no no yes yes orer = 0 and per = 0? rdrf = 1? all data received? yes figure 13.8 sample recepti on processing flowchart the above procedure may include interrupt handling. 13. smart card interface rev.4.00 aug. 20, 2007 page 403 of 638 rej09b0395-0400 if reception ends and the rdrf flag is set to 1 while the rie bit is set to 1 and interrupt requests are enabled, a receive-data-full interrupt (rxi) w ill be requested. if an error occurs in reception and either the orer flag or the per flag is se t to 1, a transmit/receive-error interrupt (eri) will be requested. for details, see interrupt operations in this section. if a parity error occurs during reception and the per flag is set to 1, the received data is transferred to rdr, so the erroneous data can be read. switching modes: when switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing re to 0 and setting te to 1. the rdrf, per, or orer flag can be us ed to check that the receive operation has been completed. when switching from transmit mode to receive mode , first confirm that the transmit operation has been completed, then start from initialization, clearing te to 0 and setting re to 1. the tend flag can be used to ch eck that the transmit operation has been completed. fixing clock output: when the gm bit is set to 1 in smr, clock output can be fixed by means of the cke1 and cke0 bits in scr. the minimum clock pulse width can be set to the specified width in this case. figure 13.9 shows the timing for fixing clock output. in this example, gm = 1, cke1 = 0, and the cke0 bit is controlled. specified pulse width cke1 value sck specified pulse width scr write (cke0 = 1) scr write (cke0 = 0) figure 13.9 timing for fixing cock output 13. smart card interface rev.4.00 aug. 20, 2007 page 404 of 638 rej09b0395-0400 interrupt operations: the smart card interface has three inte rrupt sources: transmit-data-empty (txi), transmit/receive-error (eri), and receive -data-full (rxi). the transmit-end interrupt request (tei) is not available in smart card mode. a txi interrupt is requested when the tend flag is set to 1 in ssr. an rxi interrupt is requested when the rdrf flag is set to 1 in ssr. an eri interrupt is requested when the orer, per, or ers flag is set to 1 in ssr. these relationships are shown in table 13.8. table 13.8 smart card interface mode op erating states and interrupt sources operating state flag enable bit interrupt source transmit mode normal operation tend tie txi error ers rie eri receive mode normal operation rdrf rie rxi error per, orer rie eri examples of operation in gsm mode: when switching between smart card interface mode and software standby mode, use the following procedures to maintain the clock duty cycle. ? switching from smart card interface mode to software standby mode 1. set the p9 4 data register (dr) and data direction register (ddr) to the values for the fixed output state in software standby mode. 2. write 0 in the te and re bits in the serial control register (scr) to stop transmit/receive operations. at the same time, set the cke1 bit to the value for the fixed output state in software standby mode. 3. write 0 in the cke0 bit in scr to stop the clock. 4. wait for one serial clock cycle. during this period, the duty cycle is preserved and clock output is fixed at the specified level. 5. write h'00 in the serial mode register (smr) and smart card mode register (scmr). 6. make the transition to the software standby state. ? returning from software standby mode to smart card interface mode 1'. clear the software standby state. 2'. set the cke1 bit in scr to the value for the fixed output state at the start of software standby (the current p9 4 pin state). 3'. set smart card interface mode and output the cloc k. clock signal generation is started with the normal duty cycle. 13. smart card interface rev.4.00 aug. 20, 2007 page 405 of 638 rej09b0395-0400 software standby normal operation normal operation 1 2 3 4 5 6 1' 2' 3' figure 13.10 procedure for stopping and restarting the clock use the following procedure to secure the clock duty cycle after powering on. 1. the initial state is port input and high impedan ce. use pull-up or pull-down resistors to fix the potential. 2. fix at the output specified by the cke1 bit in scr. 3. set smr and scmr, and switch to smart card interface mode operation. 4. set the cke0 bit to 1 in scr to start clock output. 13. smart card interface rev.4.00 aug. 20, 2007 page 406 of 638 rej09b0395-0400 13.4 usage notes the following points should be noted when using the sci as a smart card interface. receive data sampling timing and receive margin in sm art card interface mode: in smart card interface mode, the sci operates on a base cloc k with a frequency of 372 times the transfer rate. in reception, the sci synchronizes internally with the fall of the start bit, which it samples on the base clock. receive data is latched at the rising edge of the 186th ba se clock pulse. the timing is shown in figure 13.11. internal base clock 372 clocks 186 clocks receive data (rxd) synchronization samplin g timin g d0 d1 data samplin g timin g 185 371 0 371 185 0 0 start bit figure 13.11 receive data sampling ti ming in smart card interface mode 13. smart card interface rev.4.00 aug. 20, 2007 page 407 of 638 rej09b0395-0400 the receive margin can theref ore be expressed as follows. receive margin in smart card interface mode: m = (0.5 ? 1 2n d ? 0.5 n ) ? (l ? 0.5) f ? (1 + f) 100 % legend: m: receive margin ( % ) n: ratio of clock frequency to bit rate (n = 372) d: clock duty cycle (d = 0 to 1.0) l: frame length (l =10) f: absolute deviation of clock frequency from the above equation, if f = 0 and d = 0.5, the receive margin is as follows. when d = 0.5 and f = 0: m = (0.5 ? 1/2 372) 100 % = 49.866 % retransmission: retransmission is performed by the sci in receive mode and transmit mode as described below. ? retransmission when sci is in receive mode figure 13.12 illustrates retransmission when the sci is in receive mode. 1. if an error is found when the received parity b it is checked, the per bit is automatically set to 1. if the rie bit in scr is set to the enable st ate, an eri interrupt is requested. the per bit should be cleared to 0 in ssr before the next parity bit sampling timing. 2. the rdrf bit in ssr is not set for the frame in which the error has occurred. 3. if an error is found when the received parity bit is checked, the per bit is not set to 1 in ssr. 4. if no error is found when the received parity b it is checked, the receive operation is assumed to have been completed normally, and the rdrf bit is automatically set to 1 in ssr. if the rie bit in scr is set to the enable state, an rxi interrupt is requested. 5. when a normal frame is received, the data pi n is held in three-state at the error signal transmission timing. 13. smart card interface rev.4.00 aug. 20, 2007 page 408 of 638 rej09b0395-0400 d0 d1 d2 d3 d4 d5 d6 d7 dp de ds d0 d1 d2 d3 d4 d5 d6 d7 dp (de) ds d0 d1 d2 d3 d4 ds frame n + 1 retransmitted frame frame n rdrf [1] per [2] [3] [4] figure 13.12 retransmission in sci receive mode ? retransmission when sci is in transmit mode figure 13.13 illustrates retransmission when the sci is in transmit mode. 6. if an error signal is sent back from the r eceiving device after transmission of one frame is completed, the ers bit is set to 1 in ssr. if the rie bit in scr is set to the enable state, an eri interrupt is requested. the ers bit should be cleared to 0 in ssr before the next parity bit sampling timing. 7. the tend bit in ssr is not set for the frame for which the error signal was received. 8. if an error signal is not sent back from the receiving device, the ers flag is not set in ssr. 9. if an error signal is not sent back from the receiving device, transmission of one frame, including retransmission, is assumed to have been completed, and the tend bit is set to 1 in ssr. if the tie bit in scr is set to the en able state, a txi interrupt is requested. d0 d1 d2 d3 d4 d5 d6 d7 dp de ds d0 d1 d2 d3 d4 d5 d6 d7 dp (de) ds d0 d1 d2 d3 d4 ds frame n + 1 retransmitted frame frame n tdre tend [6] ers transfer from tdr to tsr transfer from tdr to tsr transfer from tdr to tsr [7] [9] [8] figure 13.13 retransmission in sci transmit mode 13. smart card interface rev.4.00 aug. 20, 2007 page 409 of 638 rej09b0395-0400 note on block transfer mode support: the smart card interface in stalled in the h8/3008 supports an ic card (smart card) interface with provision for iso/iec7816-3 t = 0 (character transmission). therefore, block transfer operations are not supported (error signal transmission, detection, and automatic data retransmission are not performed). 13. smart card interface rev.4.00 aug. 20, 2007 page 410 of 638 rej09b0395-0400 14. a/d converter rev.4.00 aug. 20, 2007 page 411 of 638 rej09b0395-0400 section 14 a/d converter 14.1 overview the h8/3008 includes a 10-bit successive-approximations a/d converter with a selection of up to eight analog input channels. when the a/d converter is not used, it can be halted independently to conserve power. for details see section 18.6, module standby function. the h8/3008 supports 70/134-state conversion as a high-speed conversion mode. note that it differs in this respect from the h8/3048 group, which supports 134/266-state conversion. 14.1.1 features a/d converter features are listed below. ? 10-bit resolution ? eight input channels ? selectable analog conversion voltage range the analog voltage conversion range can be programmed by input of an analog reference voltage at the v ref pin. ? high-speed conversion conversion time: minimum 5.36 s per channel ? two conversion modes single mode: a/d conversion of one channel scan mode: continuous a/d conversion on one to four channels ? four 16-bit data registers a/d conversion results are transferred for storage into data registers corresponding to the channels. ? sample-and-hold function ? three conversion start sources the a/d converter can be activated by software, an external trigger, or an 8-bit timer compare match. ? a/d interrupt requested at end of conversion at the end of a/d conversion, an a/d end interrupt (adi) can be requested. 14. a/d converter rev.4.00 aug. 20, 2007 page 412 of 638 rej09b0395-0400 14.1.2 block diagram figure 14.1 shows a block diagram of the a/d converter. module data bus bus interface internal data bus addra addrb addrc addrd adcsr adcr successive- approximations re g ister 10-bit d/a analo g multi- plexer sample-and- hold circuit comparator + ? control circuit /4 /8 adi interrupt si g nal av v av cc ref ss an an an an an an an an 0 1 2 3 4 5 6 7 le g end: adcr: adcsr: addra: addrb: addrc: addrd: a/d control re g ister a/d control/status re g ister a/d data re g ister a a/d data re g ister b a/d data re g ister c a/d data re g ister d adtrg adte compare match a0 8tcsr0 8-bit timer figure 14.1 a/d converter block diagram 14. a/d converter rev.4.00 aug. 20, 2007 page 413 of 638 rej09b0395-0400 14.1.3 pin configuration table 14.1 summarizes the a/d converter's input pins. the eight analog input pins are divided into two groups: group 0 (an 0 to an 3 ), and group 1 (an 4 to an 7 ). av cc and av ss are the power supply for the analog circuits in the a/d converter. v ref is the a/d conversion reference voltage. table 14.1 a/d converter pins pin name abbreviation i/o function analog power supply pin av cc input analog power supply analog ground pin av ss input analog ground and reference voltage reference voltage pin v ref input analog reference voltage analog input pin 0 an 0 input group 0 analog inputs analog input pin 1 an 1 input analog input pin 2 an 2 input analog input pin 3 an 3 input analog input pin 4 an 4 input group 1 analog inputs analog input pin 5 an 5 input analog input pin 6 an 6 input analog input pin 7 an 7 input a/d external trigger input pin adtrg input external trigger input for starting a/d conversion 14. a/d converter rev.4.00 aug. 20, 2007 page 414 of 638 rej09b0395-0400 14.1.4 register configuration table 14.2 summarizes the a/d converter's registers. table 14.2 a/d converter registers address * 1 name abbreviation r/w initial value h'fffe0 a/d data register a h addrah r h'00 h'fffe1 a/d data register a l addral r h'00 h'fffe2 a/d data register b h addrbh r h'00 h'fffe3 a/d data register b l addrbl r h'00 h'fffe4 a/d data register c h addrch r h'00 h'fffe5 a/d data register c l addrcl r h'00 h'fffe6 a/d data register d h addrdh r h'00 h'fffe7 a/d data register d l addrdl r h'00 h'fffe8 a/d control/status register adcsr r/(w) * 2 h'00 h'fffe9 a/d control register adcr r/w h'7e notes: 1. lower 20 bits of the address in advanced mode. 2. only 0 can be written in bit 7, to clear the flag. 14. a/d converter rev.4.00 aug. 20, 2007 page 415 of 638 rej09b0395-0400 14.2 register descriptions 14.2.1 a/d data registers a to d (addra to addrd) bit addrn initial value 14 ad8 0 r 12 ad6 0 r 10 ad4 0 r 8 ad2 0 r 6 ad0 0 r 0 ? 0 r 4 ? 0 r 2 ? 0 r 15 ad9 0 r 13 ad7 0 r 11 ad5 0 r 9 ad3 0 r 7 ad1 0 r 1 ? 0 r 5 ? 0 r 3 ? 0 r a/d c onversion data 10-bit data g ivin g an a/d conversion result reserved bits read/write note: n = a to d the four a/d data registers (addra to addrd) are 16-bit read-only registers that store the results of a/d conversion. an a/d conversion produces 10-bit data, which is transferred for storage into the a/d data register corresponding to the selected channel. the upper 8 bits of the result are stored in the upper byte of the a/d data register. the lower 2 bits are stored in the lower byte. bits 5 to 0 of an a/d data register are reserved bits that are always r ead as 0. table 14.3 indicates the pairings of analog input channels and a/d data registers. the cpu can always read the a/d data registers. the upper byte can be read directly, but the lower byte is read through a temporary register (temp). for details see section 14.3, cpu interface. the a/d data registers are initialized to h'0000 by a reset and in standby mode. table 14.3 analog input channels and a/d data registers (addra to addrd) analog input channel group 0 group 1 a/d data register an 0 an 4 addra an 1 an 5 addrb an 2 an 6 addrc an 3 an 7 addrd 14. a/d converter rev.4.00 aug. 20, 2007 page 416 of 638 rej09b0395-0400 14.2.2 a/d control/status register (adcsr) bit initial value read/write 7 adf 0 r/(w) 6 adie 0 r/w 5 adst 0 r/w 4 scan 0 r/w 3 cks 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w * note: only 0 can be written, to clear the fla g . * a/d end flag indicates end of a/d conversion a/d interrupt enable enables and disables a/d end interrupts a/d start starts or stops a/d conversion s c an mode selects sin g le mode or scan mode clo c k sele c t selects the a/d conversion time channel sele c t 2 to 0 these bits select analo g input channels adcsr is an 8-bit readable/writable register that selects the mode and controls the a/d converter. adcsr is initialized to h'00 by a reset and in standby mode. bit 7?a/d end flag (adf): indicates the end of a/d conversion. bit 7 adf description 0 [clearing condition] read adf when adf = 1, then write 0 in adf. (initial value) 1 [setting conditions] ? single mode: a/d conversion ends ? scan mode: a/d conversion ends in all selected channels 14. a/d converter rev.4.00 aug. 20, 2007 page 417 of 638 rej09b0395-0400 bit 6?a/d interrupt enable (adie): enables or disables the inte rrupt (adi) requested at the end of a/d conversion. bit 6 adie description 0 a/d end interrupt request (adi) is disabled (initial value) 1 a/d end interrupt request (adi) is enabled bit 5?a/d start (adst): starts or stops a/d conversion. the adst bit remains set to 1 during a/d conversion. it can also be set to 1 by external trigger input at the adtrg pin, or by an 8-bit timer compare match. bit 5 adst description 0 a/d conversion is stopped (initial value) 1 single mode: a/d conversion starts; adst is automatically cleared to 0 when conversion ends. scan mode: a/d conversion starts and continues, cycling among the selected channels, until adst is cleared to 0 by software, by a reset, or by a transition to standby mode. bit 4?scan mode (scan): selects single mode or scan mode. for further information on operation in these modes, see section 14.4, operation. clear the adst bit to 0 before switching the conversion mode. bit 4 scan description 0 single mode (initial value) 1 scan mode bit 3?clock select (cks): selects the a/d conversion time. clear the adst bit to 0 before switching the conversion time. bit 3 cks description 0 conversion time = 134 states (maximum) (initial value) 1 conversion time = 70 states (maximum) 14. a/d converter rev.4.00 aug. 20, 2007 page 418 of 638 rej09b0395-0400 bits 2 to 0?channel select 2 to 0 (ch2 to ch0): these bits and the scan bit select the analog input channels. clear the adst bit to 0 before changing the channel selection. group selection channel selection description ch2 ch1 ch0 single mode scan mode 0 0 0 an 0 (initial value) an 0 1 an 1 an 0 , an 1 1 0 an 2 an 0 to an 2 1 an 3 an 0 to an 3 1 0 0 an 4 an 4 1 an 5 an 4 , an 5 1 0 an 6 an 4 to an 6 1 an 7 an 4 to an 7 14.2.3 a/d control register (adcr) bit initial value read/write 7 trge 0 r/w 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 0 ? 0 r/w 2 ? 1 ? 1 ? 1 ? trigger enable enables or disables startin g of a/d conversion by an external tri gg er or 8-bit timer compare match reserved bits adcr is an 8-bit readable/writable register that enables or disables starting of a/d conversion by external trigger input or an 8-bit timer compare match signal. adcr is initialized to h'7f by a reset and in standby mode. 14. a/d converter rev.4.00 aug. 20, 2007 page 419 of 638 rej09b0395-0400 bit 7?trigger enable (trge): enables or disables starting of a/d conversion by an external trigger or 8-bit timer compare match. bit 7 trge description 0 starting of a/d conversion by an external trigger or 8-bit timer compare match is disabled (initial value) 1 a/d conversion is started at the falling edge of the external trigger signal ( adtrg ) or by an 8-bit timer compare match external trigger pin and 8-bit timer selection is performed by the 8-bit timer. for details, see section 9, 8-bit timers. bits 6 to 1?reserved: these bits cannot be modified and are always read as 1. bit 0?reserved: this bit can be read or written, but must not be set to 1. 14.3 cpu interface addra to addrd are 16-bit registers, but they are connected to the cpu by an 8-bit data bus. therefore, although the upper byte can be be accesse d directly by the cpu, the lower byte is read through an 8-bit temporary register (temp). an a/d data register is read as follows. when the upper byte is read, the upper-byte value is transferred directly to the cpu and the lower-byte value is transferred into temp. next, when the lower byte is read, the temp conten ts are transferred to the cpu. when reading an a/d data register, always read th e upper byte before the lower byte. it is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. figure 14.2 shows the data flow fo r access to an a/d data register. 14. a/d converter rev.4.00 aug. 20, 2007 page 420 of 638 rej09b0395-0400 upper-byte read bus interface module data bus cpu (h'aa) addrnh (h'aa) addrnl (h'40) lower-byte read note: n = a to d bus interface module data bus cpu (h'40) addrnh (h'aa) addrnl (h'40) temp (h'40) temp (h'40) figure 14.2 a/d data register a ccess operation (r eading h'aa40) 14. a/d converter rev.4.00 aug. 20, 2007 page 421 of 638 rej09b0395-0400 14.4 operation the a/d converter operates by successive approxi mations with 10-bit resolution. it has two operating modes: single mode and scan mode. 14.4.1 single mode (scan = 0) single mode should be selected when only one a/d conversion on one channel is required. a/d conversion starts when the adst bit is set to 1 by software, or by external trigger input. the adst bit remains set to 1 during a/d conversion and is automatically cleared to 0 when conversion ends. when conversion ends the adf flag is set to 1. if the adie bit is also set to 1, an adi interrupt is requested at this time. to clea r the adf flag to 0, first read adcsr, then write 0 in adf. when the mode or analog input channel must be switched during analog conversion, to prevent incorrect operation, first clear the adst bit to 0 in adcsr to halt a/d conversion. after making the necessary changes, set the adst bit to 1 to start a/d conversion again. the adst bit can be set at the same time as the mode or channel is changed. typical operations when channel 1 (an 1 ) is selected in single mode are described next. figure 14.3 shows a timing diagram for this example. 1. single mode is selected (scan = 0), input channel an 1 is selected (ch2 = ch1 = 0, ch0 = 1), the a/d interrupt is enabled (adie = 1), and a/d conversion is started (adst = 1). 2. when a/d conversion is completed, the result is transferred into addrb. at the same time the adf flag is set to 1, the adst bit is cleared to 0, and the a/d converter becomes idle. 3. since adf = 1 and adie = 1, an adi interrupt is requested. 4. the a/d interrupt handling routine starts. 5. the routine reads adcsr, then writes 0 in the adf flag. 6. the routine reads and proce sses the conversion result (addrb). 7. execution of the a/d interrupt handling routine ends. after that, if the adst bit is set to 1, a/d conversion starts again and steps 2 to 7 are repeated. 14. a/d converter rev.4.00 aug. 20, 2007 page 422 of 638 rej09b0395-0400 adie adst adf state of channel 0 (an ) set set set clear clear idle idle idle idle a/d conversion (1) a/d conversion (2) idle read conversion result a/d conversion result (1) read conversion result a/d conversion result (2) note: vertical arrows ( ) indicate instructions executed by software. 0 1 2 3 a/d conversion starts * * * * * * addra addrb addrc addrd state of channel 1 (an ) state of channel 2 (an ) state of channel 3 (an ) idle figure 14.3 example of a/d converter operation (single mode, channel 1 selected) 14. a/d converter rev.4.00 aug. 20, 2007 page 423 of 638 rej09b0395-0400 14.4.2 scan mode (scan = 1) scan mode is useful for monitoring analog inputs in a group of one or more channels. when the adst bit is set to 1 by software or external trigger input, a/d conversion starts on the first channel in the group (an 0 when ch2 = 0, an 4 when ch2 = 1). when two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (an 1 or an 5 ) starts immediately. a/d convers ion continues cyclically on the selected channels until the adst bit is cleared to 0. the conversion results are tr ansferred for storage into the a/d data registers corresponding to the channels. when the mode or analog input channel selecti on must be changed during analog conversion, to prevent incorrect operation, first clear the adst bit to 0 in adcsr to halt a/d conversion. after making the necessary changes, se t the adst bit to 1. a/d conve rsion will start again from the first channel in the group. the adst bit can be set at the same time as the mode or channel selection is changed. typical operations when three channels in group 0 (an 0 to an 2 ) are selected in scan mode are described next. figure 14.4 shows a timing diagram for this example. 1. scan mode is selected (scan = 1), scan gro up 0 is selected (ch2 = 0), analog input channels an 0 to an 2 are selected (ch1 = 1, ch0 = 0), and a/d conversion is started (adst = 1). 2. when a/d conversion of the first channel (an 0 ) is completed, the result is transferred into addra. next, conversion of the second channel (an 1 ) starts automatically. 3. conversion proceeds in the same way through the third channel (an 2 ). 4. when conversion of all selected channels (an 0 to an 2 ) is completed, the adf flag is set to 1 and conversion of the first channel (an 0 ) starts again. if the adie bit is set to 1, an adi interrupt is requested when a/d conversion ends. 5. steps 2 to 4 are repeated as long as the adst bit remains set to 1. when the adst bit is cleared to 0, a/d conversion stops. after that, if the adst bit is set to 1, a/d conversion starts again from the first channel (an 0 ). 14. a/d converter rev.4.00 aug. 20, 2007 page 424 of 638 rej09b0395-0400 adst adf state of channel 0 (an ) 0 1 2 3 continuous a/d conversion set clear * 1 clear * 1 idle a/d conversion (1) idle idle idle a/d conversion (4) idle a/d conversion (2) idle a/d conversion (5) idle a/d conversion (3) idle idle transfer a/d conversion result (1) a/d conversion result (4) a/d conversion result (2) a/d conversion result (3) 1. 2. a/d conversion time notes: * 2 * 1 addra addrb addrc addrd state of channel 1 (an ) state of channel 2 (an ) state of channel 3 (an ) vertical arrows ( ) indicate instructions executed by software. data currently bein g converted is i g nored. figure 14.4 example of a/d converter operation (scan mode, channels an 0 to an 2 selected) 14. a/d converter rev.4.00 aug. 20, 2007 page 425 of 638 rej09b0395-0400 14.4.3 input sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit. the a/d converter samples the analog input at a time t d after the adst bit is set to 1, then starts conversion. figure 14.5 shows the a/d conversion timing. table 14.4 indicates the a/d conversion time. as indicated in figure 14.5, the a/d conversion time includes t d and the input sampling time. the length of t d varies depending on the timing of the write access to adcsr. the total conversion time therefore varies within the ranges indicated in table 14.4. in scan mode, the values given in table 14.4 apply to the first conversion. in the second and subsequent conversions the conversion time is fixed at 128 states when cks = 0 or 66 states when cks = 1. 14. a/d converter rev.4.00 aug. 20, 2007 page 426 of 638 rej09b0395-0400 address bus write si g nal input samplin g timin g adf (1) (2) t d t spl t conv le g end: (1): (2): t : t : t : d spl conv adcsr write cycle adcsr address synchronization delay input samplin g time a/d conversion time figure 14.5 a/d conversion timing table 14.4 a/d conversion time (single mode) cks = 0 cks = 1 symbol min typ max min typ max synchronization delay t d 6 ? 9 4 ? 5 input sampling time t spl ? 31 ? ? 15 ? a/d conversion time t conv 131 ? 134 69 ? 70 note: values in the table are numbers of states. 14. a/d converter rev.4.00 aug. 20, 2007 page 427 of 638 rej09b0395-0400 14.4.4 external trigger input timing a/d conversion can be externally triggered. when the trge bit is set to 1 in adcr and the 8-bit timer's adte bit is cleared to 0, external trigger input is enabled at the adtrg pin. a high-to- low transition at the adtrg pin sets the adst bit to 1 in adcsr, starting a/d conversion. other operations, in both single and scan modes, are the same as if the adst bit had been set to 1 by software. figure 14.6 shows the timing. adtrg internal tri gg er si g nal adst a/d conversion figure 14.6 external trigger input timing 14.5 interrupts the a/d converter generates an interrupt (adi) at the end of a/d conversion. the adi interrupt request can be enabled or disabled by the adie bit in adcsr. 14. a/d converter rev.4.00 aug. 20, 2007 page 428 of 638 rej09b0395-0400 14.6 usage notes when using the a/d converter, note the following points: 1. analog input voltage range during a/d conversion, the voltages input to the analog input pins an n should be in the range av ss an n v ref . 2. relationships of av cc and av ss to v cc and v ss av cc , av ss , v cc , and v ss should be related as follows: av ss = v ss . av cc and av ss must not be left open, even if the a/d converter is not used. 3. v ref programming range the reference voltage input at the v ref pin should be in the range v ref av cc . 4. note on board design in board layout, separate the digital circuits from the analog circuits as much as possible. particularly avoid layouts in which the signal lines of digital circuits cross or closely approach the signal lines of analog circuits. induction and other effects may cause the analog circuits to operate incorrectly, or may adversely affect the accuracy of a/d conversion. the analog input signals (an 0 to an 7 ), analog reference voltage (v ref ), and analog supply voltage (av cc ) must be separated from digital circuits by the analog ground (av ss ). the analog ground (av ss ) should be connected to a stable digital ground (v ss ) at one point on the board. 5. note on noise to prevent damage from surges and other abnormal voltages at the analog input pins (an 0 to an 7 ) and analog reference voltage pin (v ref ), connect a protection circuit like the one in figure 14.7 between av cc and av ss . the bypass capacitors connected to av cc and v ref and the filter capacitors connected to an 0 to an 7 must be connected to av ss . if filter capacitors like the ones in figure 14.7 are connected, the voltage values input to the analog input pins (an 0 to an 7 ) will be smoothed, which may give rise to erro r. error can also occur if a/d conversion is frequently performed in scan mode so that the current that charges and discharges the capacitor in the sample-and-hold circuit of the a/d converter becomes greater than that input to the analog input pins via input impedance (rin). the circuit constants should therefore be selected carefully. 14. a/d converter rev.4.00 aug. 20, 2007 page 429 of 638 rej09b0395-0400 av cc * 1 * 1 v ref an 0 to an 7 av ss notes: 1. 2. rin: input impedance rin * 2 100 0.1 f 0.01 f 10 f figure 14.7 example of analog input protection circuit table 14.5 analog input pin ratings item min max unit analog input capacitance ? 20 pf allowable signal-source impedance ? 10 * k note: * when conversion time = 134 states, v cc = 4.0 v to 5.5 v, and 13 mhz. for details, see section 19. electrical characteristics. 20 pf to a/d converter an 0 to an 7 10 k figure 14.8 analog input pin equivalent circuit note: numeric values are appr oximate, except in table 14.5 14. a/d converter rev.4.00 aug. 20, 2007 page 430 of 638 rej09b0395-0400 6. a/d conversion accuracy definitions a/d conversion accuracy in the h8/3008 is defined as follows: ? resolution digital output code length of a/d converter ? offset error deviation from ideal a/d conversion characteristic of analog input voltage required to raise digital output from minimum voltage value 0000000000 to 0000000001 (figure 14.10) ? full-scale error deviation from ideal a/d conversion characteristic of analog input voltage required to raise digital output from 1111111110 to 1111111111 (figure 14.10) ? quantization error intrinsic error of the a/d converter; 1/2 lsb (figure 14.9) ? nonlinearity error deviation from ideal a/d conversion characteris tic in range from zero volts to full scale, exclusive of offset error, full-s cale error, and quantization error. ? absolute accuracy deviation of digital value from analog input value, including offset error, full-scale error, quantization error, and nonlinearity error. 14. a/d converter rev.4.00 aug. 20, 2007 page 431 of 638 rej09b0395-0400 111 110 101 100 011 010 001 000 1/8 2/8 3/8 4/8 5/8 6/8 7/8 fs quantization error analo g input volta g e di g ital output ideal a/d conversion characteristic figure 14.9 a/d converter accuracy definitions (1) 14. a/d converter rev.4.00 aug. 20, 2007 page 432 of 638 rej09b0395-0400 fs offset error nonlinearity error actual a/d conversion characteristic analo g input volta g e di g ital output ideal a/d conversion characteristic full-scale error figure 14.10 a/d converter accuracy definitions (2) 7. allowable signal-source impedance the analog inputs of the h8/3008 are designed to assure accurate conversion of input signals with a signal-source impedance not exceeding 10 k . the reason for this rating is that it enables the input capacitor in the sample-and-hold circuit in the a/d converter to charge within the sampling time. if the sensor output impedance exceeds 10 k , charging may be inadequate and the accuracy of a/d conversion cannot be guaranteed. if a large external capacitor is provided in single mode, then the internal 10-k input resistance becomes the only significant load on th e input. in this case the impedance of the signal source is not a problem. a large external capacitor, however, acts as a low-pass filter. this may make it impossible to track analog signals with high dv/dt (e.g. a variation of 5 mv/ s) (figure 14.11). to convert high-speed analog signals or to use scan mode, insert a low-impedance buffer. 8. effect on absolute accuracy attaching an external capacitor creates a coupling with ground, so if there is noise on the ground line, it may degrade absolute accuracy . the capacitor must be connected to an electrically stable ground, such as av ss . 14. a/d converter rev.4.00 aug. 20, 2007 page 433 of 638 rej09b0395-0400 if a filter circuit is used, be careful of interference with digital signals on the same board, and make sure the circuit does not act as an antenna. equivalent circuit of a/d converter h8/3008 20 pf cin = 15 pf 10 k up to 10 k low-pass filter c up to 0.1 f sensor output impedance sensor input figure 14.11 analog input circuit (example) 14. a/d converter rev.4.00 aug. 20, 2007 page 434 of 638 rej09b0395-0400 15. d/a converter rev.4.00 aug. 20, 2007 page 435 of 638 rej09b0395-0400 section 15 d/a converter 15.1 overview the h8/3008 includes a d/a converter with two channels. 15.1.1 features d/a converter features are listed below. ? eight-bit resolution ? two output channels ? conversion time: maximum 10 s (with 20-pf capacitive load) ? output voltage: 0 v to v ref ? d/a outputs can be sustained in software standby mode 15. d/a converter rev.4.00 aug. 20, 2007 page 436 of 638 rej09b0395-0400 15.1.2 block diagram figure 15.1 shows a block diagram of the d/a converter. dadr0 dadr1 dacr dastcr v av da da av ref cc ss 0 1 le g end: dacr: dadr0: dadr1: dastcr: 8-bit d/a module data bus bus interface internal data bus control circuit d/a control re g ister d/a data re g ister 0 d/a data re g ister 1 d/a standby control re g ister figure 15.1 d/a converter block diagram 15. d/a converter rev.4.00 aug. 20, 2007 page 437 of 638 rej09b0395-0400 15.1.3 pin configuration table 15.1 summarizes the d/a converter's input and output pins. table 15.1 d/a converter pins pin name abbreviation i/o function analog power supply pin av ss input analog power supply and reference voltage analog ground pin av ss input analog ground and reference voltage analog output pin 0 da 0 output analog output, channel 0 analog output pin 1 da 1 output analog output, channel 1 reference voltage input pin v ref input analog reference voltage 15.1.4 register configuration table 15.2 summarizes the d/a converter's registers. table 15.2 d/a converter registers address * name abbreviation r/w initial value h'fff9c d/a data register 0 dadr0 r/w h'00 h'fff9d d/a data register 1 dadr1 r/w h'00 h'fff9e d/a control register dacr r/w h'1f h'ee01a d/a standby control register dastcr r/w h'fe note: * lower 20 bits of the address in advanced mode. 15. d/a converter rev.4.00 aug. 20, 2007 page 438 of 638 rej09b0395-0400 15.2 register descriptions 15.2.1 d/a data registers 0 and 1 (dadr0, dadr1) bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w the d/a data registers (dadr0 and dadr1) are 8-b it readable/writable registers that store the data to be converted. when analog output is enabled, the d/a data register values are constantly converted and output at the analog output pins. the d/a data registers are initialized to h'00 by a reset and in standby mode. when the daste bit is set to 1 in the d/a standby control register (dastcr), the d/a registers are not initialized in software standby mode. 15.2.2 d/a control register (dacr) bit initial value read/write 7 daoe1 0 r/w 6 daoe0 0 r/w 5 dae 0 r/w 4 ? 1 ? 3 ? 1 ? 2 ? 1 ? 1 ? 1 ? 0 ? 1 ? d/a output enable 1 d/a output enable 0 d/a enable controls d/a conversion and analo g output controls d/a conversion and analo g output controls d/a conversion dacr is an 8-bit readable/writable register that controls the operation of the d/a converter. dacr is initialized to h'1f by a reset and in standby mode. when the daste bit is set to 1 in the d/a standby control register (dastcr), the d/a registers are not initialized in software standby mode. 15. d/a converter rev.4.00 aug. 20, 2007 page 439 of 638 rej09b0395-0400 bit 7?d/a output enable 1 (daoe1): controls d/a conversion and analog output. bit 7 daoe1 description 0 da 1 analog output is disabled 1 channel-1 d/a conversion and da 1 analog output are enabled bit 6?d/a output enable 0 (daoe0): controls d/a conversion and analog output. bit 6 daoe0 description 0 da 0 analog output is disabled 1 channel-0 d/a conversion and da 0 analog output are enabled bit 5?d/a enable (dae): controls d/a convers ion, together with bits daoe0 and daoe1. when the dae bit is cleared to 0, analog conversion is controlled independently in channels 0 and 1. when the dae bit is set to 1, analog conversion is controlled together in channels 0 and 1. output of the conversion results is always controlled independently by daoe0 and daoe1. bit 7 daoe1 bit 6 daoe0 bit 5 dae description 0 0 ? d/a conversion is disabled in channels 0 and 1 0 1 0 d/a conversion is enabled in channel 0 d/a conversion is disabled in channel 1 0 1 1 d/a conversion is enabled in channels 0 and 1 1 0 0 d/a conversion is disabled in channel 0 d/a conversion is enabled in channel 1 1 0 1 d/a conversion is enabled in channels 0 and 1 1 1 ? d/a conversion is enabled in channels 0 and 1 when the dae bit is set to 1, even if bits daoe0 and daoe1 in dacr and the adst bit in adcsr are cleared to 0, the same current is drawn from the analog power supply as during a/d and d/a conversion. bits 4 to 0?reserved: these bits cannot be modified and are always read as 1. 15. d/a converter rev.4.00 aug. 20, 2007 page 440 of 638 rej09b0395-0400 15.2.3 d/a standby control register (dastcr) dastcr is an 8-bit readable/writable register th at enables or disables d/a output in software standby mode. bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 0 daste 0 r/w 2 ? 1 ? 1 ? 1 ? reserved bits d/a standby enable enables or disables d/a output in software standby mode dastcr is initialized to h'fe by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 1?reserved: these bits cannot be modified and are always read as 1. bit 0?d/a standby enable (daste): enables or disables d/a output in software standby mode. bit 0 daste description 0 d/a output is disabled in software standby mode (initial value) 1 d/a output is enabled in software standby mode 15.3 operation the d/a converter has two built-in d/a convers ion circuits that can perform conversion independently. d/a conversion is performed constantly while enabled in dacr. if the dadr0 or dadr1 value is modified, conversion of the new data begins immediately. the conversion results are output when bits daoe0 and daoe1 are set to 1. 15. d/a converter rev.4.00 aug. 20, 2007 page 441 of 638 rej09b0395-0400 an example of d/a conversion on channel 0 is given next. timing is indicated in figure 15.2. 1. data to be converted is written in dadr0. 2. bit daoe0 is set to 1 in dacr. d/a conversion starts and da 0 becomes an output pin. the converted result is output after the conversion time. v re f the o u tp u t val u e i s dadr c ontent s 2 5 6 output of this conversion result continues until the value in dadr0 is modified or the daoe0 bit is cleared to 0. 3. if the dadr0 value is modified, conversion star ts immediately, and the result is output after the conversion time. 4. when the daoe0 bit is cleared to 0, da0 becomes an input pin. dadr0 write cycle dacr write cycle dadr0 write cycle dacr write cycle address dadr0 daoe0 da 0 conversion data 1 conversion data 2 hi g h-impedance state conversion result 1 conversion result 2 t dconv t dconv le g end: t : d/a conversion time dconv figure 15.2 example of d/a converter operation 15. d/a converter rev.4.00 aug. 20, 2007 page 442 of 638 rej09b0395-0400 15.4 d/a output control in the h8/3008, d/a converter output can be enabled or disabled in software standby mode. when the daste bit is set to 1 in dastcr, d/a converter output is enabled in software standby mode. the d/a converter registers retain the values they held prior to th e transition to software standby mode. when d/a output is enabled in software standby mode, the reference supply current is the same as during normal operation. 16. ram rev.4.00 aug. 20, 2007 page 443 of 638 rej09b0395-0400 section 16 ram 16.1 overview the h8/3008 has high-speed static ram on-chip. the ram is connected to the cpu by a 16-bit data bus. the cpu accesses both byte data and word data in two states, making the ram useful for rapid data transfer. the on-chip ram can be enabled or disabled with the ram enable bit (rame) in the system control register (syscr). when the on-chip ram is disabled, that area is assigned to external space in the expanded modes. the on-chip ram speci fications for the h8/300 8 are shown in table 16.1. table 16.1 h8/3008 on-chip ram specifications ram size 4 kbytes address assignment modes 1, 2 h'fef20 to h'fff1f modes 3, 4 h'ffef20 to h'ffff1f 16. ram rev.4.00 aug. 20, 2007 page 444 of 638 rej09b0395-0400 16.1.1 block diagram figure 16.1 shows a block diagram of the on-chip ram. h'fef20 * h'fef22 * h'fff1e * h'fef21 * h'fef23 * h'fff1f * internal data bus (upper 8 bits) internal data bus (lower 8 bits) bus interface syscr on-chip ram even addresses odd addresses le g end: syscr: system control re g ister note: * the lower 20 bits of the address are shown. figure 16.1 ram block diagram 16.1.2 register configuration the on-chip ram is controlled by syscr. table 16.2 gives the address and initial value of syscr. table 16.2 system control register address * name abbreviation r/w initial value h'ee012 system control register syscr r/w h'09 note: * lower 20 bits of the address in advanced mode. 16. ram rev.4.00 aug. 20, 2007 page 445 of 638 rej09b0395-0400 16.2 system control register (syscr) bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ue 1 r/w 2 nmieg 0 r/w 1 ssoe 0 r/w 0 rame 1 r/w software standby standby timer select 2 to 0 user bit enable nmi edge select software standby output port enable ram enable bit enables or disables on-chip ram one function of syscr is to enable or disabl e access to the on-chip ram. the on-chip ram is enabled or disabled by the rame bit in syscr. for details about the other bits, see section 3.3, system control register (syscr). bit 0?ram enable (rame): enables or disables the on-chip ram. the rame bit is initialized at the rising e dge of the input at the res pin. it is not initialized in software standby mode. bit 0 rame des c ription 0 on-chip ram is disabled 1 on-chip ram is enabled (initial value) 16. ram rev.4.00 aug. 20, 2007 page 446 of 638 rej09b0395-0400 16.3 operation when the rame bit is set to 1, the on-chip ram is enabled. accesses to the addresses shown in table 16.1 are directed to the on-chip ram. in modes 1 to 4 (expanded modes), when the rame bit is cleared to 0, the off- chip address space is accessed. since the on-chip ram is connected to the cpu by an internal 16-bit data bus, it can be written and read by word access. it can also be written and read by byte access. byte data is accessed in two states using the upper 8 bits of the data bus. word data starting at an even address is accessed in two states using all 16 bits of the data bus. 17. clock pulse generator rev.4.00 aug. 20, 2007 page 447 of 638 rej09b0395-0400 section 17 clock pulse generator 17.1 overview the h8/3008 has a built-in clock pulse generator (cpg) that generates the system clock ( ) and other internal clock signals ( /2 to /4096). after duty adjustment, a frequency divider divides the clock frequency to generate the system clock ( ). the system clock is output at the pin* 1 and furnished as a master clock to prescalers that supply clock signals to the on-chip supporting modules. frequency division ratios of 1/1, 1/2, 1/4, and 1/8 can be selected for the frequency divider by settings in a division control register (divcr)* 2 . power consumption in the chip is reduced in almost direct proportion to the frequency division ratio. notes: 1. usage of the pin differs depending on the chip operating mode and the pstop bit setting in the module standby control register (mstcr). for details, see section 18.7, system clock output disabling function. 2. the division ratio of the frequency divider can be changed dynamically during operation. the clock output at the pin also changes when the division ratio is changed. the frequency output at the pin is shown below. = extal n where, extal: frequency of crystal resonator or external clock signal n: frequency division ratio (n = 1/1, 1/2, 1/4, or 1/8) 17. clock pulse generator rev.4.00 aug. 20, 2007 page 448 of 638 rej09b0395-0400 17.1.1 block diagram figure 17.1 shows a block diagram of the clock pulse generator. xtal extal cpg ? /2 to /4096 oscillator duty adjustment circuit frequency divider division control re g ister prescalers data bus figure 17.1 block diagram of clock pulse generator 17. clock pulse generator rev.4.00 aug. 20, 2007 page 449 of 638 rej09b0395-0400 17.2 oscillator circuit clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock signal. 17.2.1 connecting a crystal resonator circuit configuration: a crystal resonator can be connected as in the example in figure 17.2. damping resistance rd should be selected according to table 17.1 (1), and external capacitances c l1 and c l2 according to table 17.1 (2). an at-cut parallel-resonance crystal should be used. extal xtal c l1 c l2 rd figure 17.2 connection of crystal resonator (example) if a crystal resonator with a frequency higher than 20 mhz is connected, the external load capacitance values in table 17.1 (2) should not exceed 10 [pf]. also, in order to improve the accuracy of the oscillation frequency, a thorough study of oscillation matching evaluation, etc., should be carried out when deciding the circuit constants. table 17.1 (1) damping resistance value frequency f (mhz) damping resistance value 2 2 < f 4 4 < f 8 8 < f 10 10 < f 13 13 < f 16 16 < f 18 18 < f 25 rd ( ) 1 k 500 200 0 0 0 0 0 note: a crystal resonator between 2 mhz and 25 mhz can be used. if the chip is to be operated at less than 2 mhz, the on-chip frequency divider should be used. (a crystal resonator of less than 2 mhz cannot be used.) 17. clock pulse generator rev.4.00 aug. 20, 2007 page 450 of 638 rej09b0395-0400 table 17.1 (2) external capacitance values external capacitance value 5 v version 3 v version frequency f (mhz) 20 < f 25 2 f 20 2 f 16 16 f 25 c l1 = c l2 (pf) 10 10 to 22 22 10 crystal resonator: figure 17.3 shows an equivalent circuit of the crystal resonator. the crystal resonator should have the characteristics listed in table 17.2. xtal lrs c l c 0 extal at-cut parallel-resonance type figure 17.3 crystal resonator equivalent circuit table 17.2 crystal resonator parameters frequency (mhz) 2 4 8 10 12 16 18 20 25 rs max ( ) 500 120 80 70 60 50 40 40 40 co (pf) 7 pf max use a crystal resonator with a frequency equal to the system clock frequency ( ). notes on board design: when a crystal resonator is connected, the following points should be noted: other signal lines should be routed away from th e oscillator circuit to prevent induction from interfering with correct oscillation. see figure 17.4. when the board is designed, the crystal resonator and its load capacitors should be placed as close as possible to the xtal and extal pins. 17. clock pulse generator rev.4.00 aug. 20, 2007 page 451 of 638 rej09b0395-0400 xtal extal c l2 c l1 h8/3008 avoid si g nal a si g nal b figure 17.4 oscillator circuit block board design precautions 17.2.2 external clock input circuit configuration: an external clock signal can be input as shown in the examples in figure 17.5. if the xtal pin is left open, the stray ca pacitance should not exceed 10 pf. if the stray capacitance at the xtal pin exceeds 10 pf in co nfiguration a, use the connection shown in configuration b instead, and hold the external clock high in standby mode. extal xtal extal xtal external clock input open external clock input a. xtal pin left open b. complementary clock input at xtal pin figure 17.5 external clock input (examples) 17. clock pulse generator rev.4.00 aug. 20, 2007 page 452 of 638 rej09b0395-0400 external clock: the external clock frequency should be equal to the system clock frequency when not divided by the on-chip frequency divider. table 17.3 shows the clock timing, figure 17.6 shows the external clock input tim ing, and figure 17.7 shows th e external clock output settling delay timing. when the appropriate external clock is input via the extal pin, its waveform is corrected by the on-chip oscillator and duty adjustment circuit. when the appropriate external clock is input via the extal pin, its waveform is corrected by the on-chip oscillator and duty adjustment circuit. the resulting stable clock is output to external devices after the external clock settling time (t dext ) has passed after the clock input. the system must remain reset with the reset signal low during t dext , while the clock output is unstable. table 17.3 clock timing (preliminary) v cc = 3.0 v to 3.6 v v cc = 5.0 v 10 % item symbol min max min max unit test conditions external clock input low pulse width t exl 15 ? 15 ? ns figure 17.6 external clock input high pulse width t exh 15 ? 15 ? ns external clock rise time t exr ? 5 ? 5 ns external clock fall time t exf ? 5 ? 5 ns clock low pulse width t cl 0.4 0.6 0.4 0.6 t cyc 5 mhz 80 ? 80 ? ns < 5 mhz figure 19.7 clock high pulse width t ch 0.4 0.6 0.4 0.6 t cyc 5 mhz 80 ? 80 ? ns < 5 mhz external clock output settling delay time t dext * 500 ? 500 ? s figure 17.7 note: * t dext includes a res pulse width (t resw ). t resw = 20 t cyc 17. clock pulse generator rev.4.00 aug. 20, 2007 page 453 of 638 rej09b0395-0400 extal t exr t exf v cc 0.7 0.3 v t exh t exl v cc 0.5 figure 17.6 external clock input timing v cc stby extal (internal or external) res t dext v ih figure 17.7 external clock output settling delay timing 17. clock pulse generator rev.4.00 aug. 20, 2007 page 454 of 638 rej09b0395-0400 17.3 duty adjustment circuit when the oscillator frequency is 5 mhz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate . 17.4 prescalers the prescalers divide the system clock ( ) to generate internal clocks ( /2 to /4096). 17.5 frequency divider the frequency divider divides the duty-adjusted clock signal to generate the system clock ( ). the frequency division ratio can be changed dynamically by modifying the value in divcr, as described below. power consumption in the chip is reduced in almost direct proportion to the frequency division ratio. the system clock generate d by the frequency divider can be output at the pin. 17.5.1 register configuration table 17.4 summarizes the frequency division register. table 17.4 frequency division register address * name abbreviation r/w initial value h'ee01b division control register divcr r/w h'fc note: * lower 20 bits of the address in advanced mode. 17. clock pulse generator rev.4.00 aug. 20, 2007 page 455 of 638 rej09b0395-0400 17.5.2 division control register (divcr) divcr is an 8-bit readable/writable register that selects the division ratio of the frequency divider. bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 0 div0 0 r/w 2 ? 1 ? 1 div1 0 r/w reserved bits divide bits 1 and 0 these bits select the frequency division ratio divcr is initialized to h'fc by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 2?reserved: these bits cannot be modified and are always read as 1. bits 1 and 0?divide (div1, div0): these bits select the frequency division ratio, as follows. bit 1 div1 bit 0 div0 frequency division ratio 0 0 1/1 (initial value) 0 1 1/2 1 0 1/4 1 1 1/8 17. clock pulse generator rev.4.00 aug. 20, 2007 page 456 of 638 rej09b0395-0400 17.5.3 usage notes the divcr setting changes the frequency, so note the following points. ? select a frequency division ratio that stays within the assured operation range specified for the clock cycle time t cyc in the ac electrical ch aracteristics. note that min = lower limit of the operating frequency range. ensure that is not below this lower limit. ? all on-chip module operations are based on . note that the timing of timer operations, serial communication, and other time-dependent processing differs before and after any change in the division ratio. the waiting tim e for exit from software standby mode also changes when the division ratio is changed. for details, see section 18.4.3, selection of waiting time for exit from software standby mode. 18. power-down state rev.4.00 aug. 20, 2007 page 457 of 638 rej09b0395-0400 section 18 power-down state 18.1 overview the h8/3008 has a power-down state that greatly reduces power consumption by halting the cpu, and a module standby function that reduces power consumption by selectively halting on-chip modules. the power-down state includes the following three modes: ? sleep mode ? software standby mode ? hardware standby mode the module standby function can halt on-chip supporting modules independently of the power- down state. the modules that can be halted are the 16-bit timer, 8-bit timer, sci0, sci1, and a/d converter. table 18.1 indicates the methods of entering and exiting the power-down modes and module standby mode, and gives the status of the cpu and on-chip supporting modules in each mode. 18. power-down state rev.4.00 aug. 20, 2007 page 458 of 638 rej09b0395-0400 table 18.1 power-down state and module standby function notes: 1. state in which the correspondin g mstcr bit was set to 1. for details see section 18.2.2, module standby control re g ister h (mstcrh) and section 18.2.3, module standby control re g ister l (mstcrl). 2. the rame bit must be cleared to 0 in syscr before the transition from the pro g ram execution state to hardware standby mode. 3. when p6 7 is used as the output pin. 4. when a mstcr bit is set to 1, the re g isters of the correspondin g on-chip supportin g module are initialized. to restart the module, first clear the mstcr bit to 0, then set up the module re g isters a g ain. le g end: syscr: system control re g ister ssby: software standby bit mstcrh: module standby control re g ister h mstcrl: module standby control re g ister l mode sleep mode software standby mode hardware standby mode module standby state entering conditions sleep instruc- tion executed while ssby = 0 in syscr sleep instruc- tion executed while ssby = 1 in syscr low input at stby pin correspondin g bit set to 1 in mstcrh and mstcrl clock active halted halted active cpu halted halted halted active cpu registers held held undeter- mined ? 16-bit timer active halted and reset halted and reset halted * 1 and reset 8-bit timer active halted and reset halted and reset halted * 1 and reset sci0 active halted and reset halted and reset halted * 1 and reset sci1 active halted and reset halted and reset halted * 1 and reset a/d active halted and reset halted and reset halted * 1 and reset other modules active halted and reset halted and reset active ram held held held * 2 ? clock output * 3 output hi g h output hi g h impedance hi g h impedance * 1 i/o ports held held hi g h impedance ? exiting conditions ? interrupt ? res ? stby ? nmi ? irq 0 to irq 2 ? res ? stby ? stby ? res ? stby ? res ? clear mstcr bit to 0 * 4 18. power-down state rev.4.00 aug. 20, 2007 page 459 of 638 rej09b0395-0400 18.2 register configuration the h8/3008 has a system control register (sys cr) that controls the power-down state, and module standby control registers h (mstcrh) and l (mstcrl) that control the module standby function. table 18.2 summarizes these registers. table 18.2 control register address * name abbreviation r/w initial value h'ee012 system control register syscr r/w h'09 h'ee01c module standby control register h mstcrh r/w h'78 h'ee01d module standby control register l mstcrl r/w h'00 note: * lower 20 bits of the address in advanced mode. 18.2.1 system control register (syscr) bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ue 1 r/w 0 rame 1 r/w 2 nmieg 0 r/w 1 ssoe 0 r/w software standby enables transition to software standby mode ram enable standby timer select 2 to 0 these bits select the waitin g time of the cpu and peripheral functions user bit enable nmi edge select software standby output port enable syscr is an 8-bit readable/writable register. bit 7 (ssby), bits 6 to 4 (sts2 to sts0), and bit 1 (ssoe) control the power-down state. for information on the other syscr bits, see section 3.3, system control register (syscr). 18. power-down state rev.4.00 aug. 20, 2007 page 460 of 638 rej09b0395-0400 bit 7?software standby (ssby): enables transition to software standby mode. when software standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal operation. to clear this bit, write 0. bit 7 ssby des c ription 0 sleep instruction causes transition to sleep mode (initial value) 1 sleep instruction causes transition to software standby mode bits 6 to 4?standby timer select (sts2 to sts0): these bits select the length of time the cpu and on-chip supporting modules wait for the clock to settle when software standby mode is exited by an external interrupt. if the cl ock is generated by a crystal resonator, set these bits according to the clock frequency so that the waiting time will be at least 7 ms. see table 18.3. set these bits according to the operating frequency so th at the waiting time will be at least 100 s. bit 6 sts2 bit 5 sts1 bit 4 sts0 des c ription 0 0 0 waiting time = 8,192 states (initial value) 1 waiting time = 16,384 states 1 0 waiting time = 32,768 states 1 waiting time = 65,536 states 1 0 0 waiting time = 131,072 states 1 0 1 waiting time = 262,144 states 1 1 0 waiting time = 1,024 states 1 1 1 illegal setting bit 1?software standby output port enable (ssoe): specifies whether the address bus and bus control signals ( cs 0 to cs 7 , as , rd , hwr , and lwr ) are kept as outputs or fixed high, or placed in the high-impedance st ate in software standby mode. bit 1 ssoe des c ription 0 in software standby mode, the address bus and bus control signals (initial value) are all high-impedance 1 in software standby mode, the address bus retains its output state and bus control signals are fixed high 18. power-down state rev.4.00 aug. 20, 2007 page 461 of 638 rej09b0395-0400 18.2.2 module standby control register h (mstcrh) mstcrh is an 8-bit readable/w ritable register that controls output of the system clock ( ). it also controls the module standby function, which places individual on-chip s upporting modules in the standby state. module standby can be designated for the sci0, sci1. bit initial value read/write 7 pstop 0 r/w 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 0 mstph0 0 r/w 2 ? 0 r/w 1 mstph1 0 r/w clock stop enables or disables output of the system clock module standby h1 to h0 these bits select modules to be placed in standby reserved bits mstcrh is initialized to h'78 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7? clock stop (pstop): enables or disables output of the system clock ( ). bit 7 pstop des c ription 0 system clock output is enabled (initial value) 1 system clock output is disabled bits 6 to 3?reserved: these bits cannot be modified and are always read as 1. bit 2?reserved: this bit can be written and read. bit 1?module standby h1 (mstph1): selects whether to place the sci1 in standby. bit 1 mstph1 des c ription 0 sci1 operates normally (initial value) 1 sci1 is in standby state 18. power-down state rev.4.00 aug. 20, 2007 page 462 of 638 rej09b0395-0400 bit 0?module standby h0 (mstph0): selects whether to place the sci0 in standby. bit 0 mstph0 des c ription 0 sci0 operates normally (initial value) 1 sci0 is in standby state 18.2.3 module standby control register l (mstcrl) mstcrl is an 8-bit readable/writable register that controls the module standby function, which places individual on-chi p supporting modules in the stan dby state. module standby can be designated for 16-bit timer, 8-bit timer, and a/d converter modules. 2 mstpl2 0 r/w 1 ? 0 r/w 0 mstpl0 0 r/w reserved bits module standby l4 to l2, l0 these bits select modules to be placed in standby bit initial value read/write 7 ? 0 r/w 6 ? 0 r/w 5 ? 0 r/w 4 mstpl4 0 r/w 3 mstpl3 0 r/w mstcrl is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 5?reserved: this bit can be written and read. bit 4?module standby l4 (mstpl4): selects whether to place th e 16-bit timer in standby. bit 4 mstpl4 des c ription 0 16-bit timer operates normally (initial value) 1 16-bit timer is in standby state 18. power-down state rev.4.00 aug. 20, 2007 page 463 of 638 rej09b0395-0400 bit 3?module standby l3 (mstpl3): selects whether to place 8-bit timer channels 0 and 1 in standby. bit 3 mstpl3 des c ription 0 8-bit timer channels 0 and 1 operate normally (initial value) 1 8-bit timer channels 0 and 1 are in standby state bit 2?module standby l2 (mstpl2): selects whether to place 8-bit timer channels 2 and 3 in standby. bit 2 mstpl2 des c ription 0 8-bit timer channels 2 and 3 operate normally (initial value) 1 8-bit timer channels 2 and 3 are in standby state bit 1?reserved: this bit can be written and read. bit 0?module standby l0 (mstpl0): selects whether to place th e a/d converter in standby. bit 0 mstpl0 des c ription 0 a/d converter operates normally (initial value) 1 a/d converter is in standby state 18. power-down state rev.4.00 aug. 20, 2007 page 464 of 638 rej09b0395-0400 18.3 sleep mode 18.3.1 transition to sleep mode when the ssby bit is cleared to 0 in syscr, execution of the sleep instruction causes a transition from the program execution state to sleep mode. immediately after executing the sleep instruction the cpu halts, but the contents of its internal registers are retained. on-chip supporting modules do not halt in sleep mode. modules wh ich have been placed in standby by the module standby function, however, remain halted. 18.3.2 exit from sleep mode sleep mode is exited by an interrupt, or by input at the res or stby pin. exit by interrupt: an interrupt terminates sleep mode and causes a transition to the interrupt exception handling state. sleep mode is not exited by an interrupt source in an on-chip supporting module if the interrupt is disabled in the on-chip supporting module. sleep mode is not exited by an interrupt other than nmi if the interrupt is masked by interrupt priority settings and the settings of the i and ui bits in ccr, ipr. exit by res input: low input at the res pin exits from sleep mode to the reset state. exit by stby input: low input at the stby pin exits from sleep mode to hardware standby mode. 18.4 software standby mode 18.4.1 transition to software standby mode to enter software standby mode, execute the sleep instruction while the ssb y bit is set to 1 in syscr. in software standby mode, current dissipation is reduced to an extremel y low level because the cpu, clock, and on-chip supporting modules a ll halt. on-chip supporting modules are reset and halted. as long as the specified voltage is supplied, however, cpu register contents and on-chip ram data are retained. the settings of the i/o ports also held. when the wdt is used as a watchdog timer (wt/ it = 1), the tme bit must be cleared to 0 before setting ssby. also, when setting tme to 1, ssby should be cleared to 0. clear the brle bit in brcr (inhibiting bus release) before making a transition to software standby mode. 18. power-down state rev.4.00 aug. 20, 2007 page 465 of 638 rej09b0395-0400 18.4.2 exit from software standby mode software standby mode can be exited by input of an external interrupt at the nmi, irq 0 , irq 1 , or irq 2 pin, or by input at the res or stby pin. exit by interrupt: when an nmi, irq 0 , irq 1 , or irq 2 interrupt request signal is received, the clock oscillator begins operating. after the oscillator settling time selected by bits sts2 to sts0 in syscr, stable clock signals are supplied to the entire chip, software standby mode ends, and interrupt exception handling begins. software standby mode is not exited if the interrupt enable bits of interrupts irq 0 , irq 1 , and irq 2 are cleared to 0, or if thes e interrupts are masked in the cpu. exit by res input: when the res input goes low, the clock oscillator starts and clock pulses are supplied immediately to the entire chip. the res signal must be held low long enough for the clock oscillator to stabilize. when res goes high, the cpu starts reset exception handling. exit by stby input: low input at the stby pin causes a transition to hardware standby mode. 18.4.3 selection of waiting time for exit from software standby mode bits sts2 to sts0 in syscr and bits div1 and div0 in divcr should be set as follows. crystal resonator: set sts2 to sts0, div1, and div0 so that the waiting time (for the clock to stabilize) is at least 7 ms. tabl e 18.3 indicates the waiting times that are selected by sts2 to sts0, div1, and div0 settings at various system clock frequencies. when using an external clock: set the sts2 to sts0, div0, and div1 bits so that the waiting time is at least 100 s. 18. power-down state rev.4.00 aug. 20, 2007 page 466 of 638 rej09b0395-0400 table 18.3 clock frequency and waiting time for clock to settle div1 div0 sts2 sts1 sts0 waiting time 25 mhz 20 mhz 18 mhz 16 mhz 12 mhz 10 mhz 8 mhz 6 mhz 4 mhz 2 mhz 1mhz 0 0 0 0 0 8192 states 0.3 0.4 0.46 0.51 0.65 0.8 1.0 1.3 2.0 4.1 0 0 1 16384 states 0.7 0.8 0.91 1.0 1.3 1.6 2.0 2.7 4.1 8.2 * 0 1 0 32768 states 1.3 1.6 1.8 2.0 2.7 3.3 4.1 5.5 8.2 * 16.4 0 1 1 65536 states 2.6 3.3 3.6 4.1 5.5 6.6 8.2 * 10.9 * 16.4 32.8 1 0 0 131072 states 5.2 6.6 7.3 * 8.2 * 10.9 * 13.1 * 16.4 21.8 32.8 65.5 1 0 1 262144 states 10.5 * 13.1 * 14.6 16.4 21.8 26.2 32.8 43.7 65.5 131.1 1 1 0 1024 states 0.04 0.05 0.057 0.064 0.085 0.10 0.13 0.17 0.26 0.51 1 1 1 ille g al settin g 0 1 0 0 0 8192 states 0.7 0.8 0.91 1.02 1.4 1.6 2.0 2.7 4.1 8.2 * 0 0 1 16384 states 1.3 1.6 1.8 2.0 2.7 3.3 4.1 5.5 8.2 * 16.4 0 1 0 32768 states 2.6 3.3 3.6 4.1 5.5 6.6 8.2 * 10.9 * 16.4 32.8 0 1 1 65536 states 5.2 6.6 7.3 * 8.2 * 10.9 * 13.1 * 16.4 21.8 32.8 65.5 1 0 0 131072 states 10.5 * 13.1 * 14.6 16.4 21.8 26.2 32.8 43.7 65.5 131.1 1 0 1 262144 states 21.0 26.2 29.1 32.8 43.7 52.4 65.5 87.4 131.1 262.1 1 1 0 1024 states 0.08 0.10 0.11 0.13 0.17 0.20 0.26 0.34 0.51 1.0 1 1 1 ille g al settin g 1 0 0 0 0 8192 states 1.3 1.6 1.8 2.0 2.7 3.3 4.1 5.5 8.2 * 16.4 * 0 0 1 16384 states 2.6 3.3 3.6 4.1 5.5 6.6 8.2 * 10.9 * 16.4 32.8 0 1 0 32768 states 5.2 6.6 7.3 * 8.2 * 10.9 * 13.1 * 16.4 21.8 32.8 65.5 0 1 1 65536 states 10.5 * 13.1 * 14.6 16.4 21.8 26.2 32.8 43.7 65.5 131.1 1 0 0 131072 states 21.0 26.2 29.1 32.8 43.7 52.4 65.5 87.4 131.1 262.1 1 0 1 262144 states 41.9 52.4 58.3 65.5 87.4 104.9 131.1 174.8 262.1 524.3 1 1 0 1024 states 0.16 0.20 0.23 0.26 0.34 0.41 0.51 0.68 1.02 2.0 1 1 1 ille g al settin g 1 1 0 0 0 8192 states 2.6 3.3 3.6 4.1 5.5 6.6 8.2 * 10.9 * 16.4 * 32.8 * 0 0 1 16384 states 5.2 6.6 7.3 * 8.2 * 10.9 * 13.1 * 16.4 21.8 32.8 65.5 0 1 0 32768 states 10.5 * 13.1 14.6 16.4 21.8 26.2 32.8 43.7 65.5 131.1 0 1 1 65536 states 21.0 26.2 29.1 32.8 43.7 52.4 65.5 87.4 131.1 262.1 1 0 0 131072 states 41.9 52.4 58.3 65.5 87.4 104.9 131.1 174.8 262.1 524.3 1 0 1 262144 states 83.9 104.9 116.5 131.1 174.8 209.7 262.1 349.5 524.3 1048.6 1 1 0 1024 states 0.33 0.41 0.46 0.51 0.68 0.82 1.0 1.4 2.0 4.1 1 1 1 ille g al settin g note: * recommended settin g unit ms ms ms ms 8.2 * 16.4 32.8 65.5 131.1 262.1 1.0 16.4 * 32.8 65.5 131.1 262.1 524.3 2.0 32.8 * 65.5 131.1 262.1 524.3 1048.6 4.1 65.5 131.1 262.1 524.3 1048.6 2097.1 8.2 * 18. power-down state rev.4.00 aug. 20, 2007 page 467 of 638 rej09b0395-0400 18.4.4 sample application of software standby mode figure 18.1 shows an example in which software standby mode is entered at the fall of nmi and exited at the rise of nmi. with the nmi edge select bit (nmieg) cleared to 0 in syscr (selecting the falling edge), an nmi interrupt occurs. next the nmieg bit is set to 1 (selecting the rising edge) and the ssby bit is set to 1; then the sleep instruction is executed to enter software standby mode. software standby mode is exited at the next rising edge of the nmi signal. nmi nmieg ssby nmi interrupt handler nmieg = 1 ssby = 1 software standby mode (power- down state) oscillator settlin g time (t osc2 ) sleep instruction nmi exception handlin g clock oscillator figure 18.1 nmi timing for software standby mode (example) 18.4.5 note the i/o ports retain their existing states in software standby mode. if a port is in the high output state, its output current is not reduced. 18. power-down state rev.4.00 aug. 20, 2007 page 468 of 638 rej09b0395-0400 18.5 hardware standby mode 18.5.1 transition to hardware standby mode regardless of its current state, the chip enters hardware standby mode whenever the stby pin goes low. hardware standby mode reduces power consumption drastically by halting all functions of the cpu, and on-chip supporting modules. all modules are reset except the on-chip ram. as long as the specified voltage is supplied, on-chip ram data is retained. i/o ports are placed in the high-impedance state. clear the rame bit to 0 in syscr before stby goes low to retain on-chip ram data. the inputs at the mode pins (md2 to md0) should not be changed during hardware standby mode. 18.5.2 exit from hardware standby mode hardware standby mode is exited by inputs at the stby and res pins. while res is low, when stby goes high, the clock oscillator starts running. res should be held low long enough for the clock oscillator to settle. when res goes high, reset exception handling begins, followed by a transition to the program execution state. 18.5.3 timing for hardware standby mode figure 18.2 shows the timing relationships for hardware standby mode. to enter hardware standby mode, first drive res low, then drive stby low. to exit hardware standby mode, first drive stby high, wait for the clock to settle, then bring res from low to high. 18. power-down state rev.4.00 aug. 20, 2007 page 469 of 638 rej09b0395-0400 res stby clock oscillator oscillator settlin g time reset exception handlin g figure 18.2 hardware standby mode timing 18.6 module standby function 18.6.1 module standby timing the module standby function can halt several of the on-chip supporting modules (sci1, sci0, 16- bit timer, 8-bit timer, and a/d converter) independently in the power-down state. this standby function is controlled by bits mstph2 to mstph0 in mstcrh and bits mstpl7 to mstpl0 in mstcrl. when one of these bits is set to 1, the corresponding on-chip supporting module is placed in standby and halts at the beginning of th e next bus cycle after the mstcr write cycle. 18.6.2 read/write in module standby when an on-chip supporting module is in module standby, read/write access to its registers is disabled. read access always results in h'ff data. write access is ignored. 18.6.3 usage notes when using the module standby function, note the following points. on-chip supporting module interrupts: before setting a module standby bit, first disable interrupts by that module. when an on-chip supporting module is placed in standby by the module standby function, its registers are initialized, incl uding registers with in terrupt request flags. pin states: pins used by an on-chip supporting module lose their module functions when the module is placed in module standby. what happens after that depends on the particular pin. for details, see section 7, i/o ports. pins that change from the input to the out put state require special care. for example, if sci1 is pl aced in module standby, the receive data pin loses its receive data 18. power-down state rev.4.00 aug. 20, 2007 page 470 of 638 rej09b0395-0400 function and becomes a port pin. if its port ddr bit is set to 1, the pin becomes a data output pin, and its output may collide with external sci tran smit data. data collision should be prevented by clearing the port ddr bit to 0 or taking other appropriate action. register resetting: when an on-chip supporting module is halted by the module standby function, all its registers are initialized. to restart the module, after its mstcr bit is cleared to 0, its registers must be set up again. it is not possible to write to the registers while the mstcr bit is set to 1. 18.7 system clock output disabling function output of the system clock ( ) can be controlled by the pstop bit in mstcrh. when the pstop bit is set to 1, output of the system clock halts and the pin is placed in the high- impedance state. figure 18.3 shows the timing of the stopping and starting of system clock output. when the pstop bit is cleared to 0, output of th e system clock is enabled. table 18.4 indicates the state of the pin in various operating states. t1 t2 (pstop = 1) t3 t1 t2 (pstop = 0) mstcrh write cycle mstcrh write cycle hi g h impedance pin t3 figure 18.3 starting and stopping of system clock output table 18.4 pin state in variou s operating states operating state pstop = 0 pstop = 1 hardware standby high impedance high impedance software standby always high high impedance sleep mode system clock output high impedance normal operation system clock output high impedance 19. electrical characteristics rev.4.00 aug. 20, 2007 page 471 of 638 rej09b0395-0400 section 19 electrical characteristics 19.1 absolute maximum ratings table 19.1 lists the absolute maximum ratings. table 19.1 absolute maximum ratings item symbol value unit power supply voltage v cc 5 v version: ? 0.3 to +7.0 v 3 v version: ? 0.3 to +4.6 v input voltage (except for port 7) v in ? 0.3 to v cc +0.3 v input voltage (port 7) v in ? 0.3 to av cc +0.3 v reference voltage v ref ? 0.3 to av cc +0.3 v analog power supply voltage av cc 5 v version: ? 0.3 to +7.0 v 3 v version: ? 0.3 to +4.6 v analog input voltage v an ? 0.3 to av cc +0.3 v operating temperature t opr regular specifications: ? 20 to +75 c wide-range specifications: ? 40 to +85 c storage temperature t stg ? 55 to +125 c caution: permanent damage to the chip may result if absolute maximum ratings are exceeded. 19. electrical characteristics rev.4.00 aug. 20, 2007 page 472 of 638 rej09b0395-0400 19.2 dc characteristics table 19.2 lists the dc characteristics. table 19.3 lists the permissible output currents. table 19.2 dc characteristics (1) conditions: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , v ref = 4.5 v to av cc * 1 , v ss = av ss = 0 v* 1 , t a = ? 20c to +75c (regular specifications), t a = ? 40c to +85c (wide-range specifications) item symbol min typ max unit test conditions v t ? 1.0 ? ? v v t + ? ? v cc 0.7 v schmitt trigger input voltages port a, p8 0 to p8 2 v t + ? v t ? 0.4 ? ? v input high voltage res , stby , nmi, md 2 to md 0 v ih v cc ? 0.7 ? v cc +0.3 v extal v cc 0.7 ? v cc +0.3 v port 7 2.0 ? av cc +0.3 v ports 4 to 6, p8 3 , p8 4 , p9 0 to p9 5 , port b 2.0 ? v cc +0.3 v input low voltage res , stby , md 2 to md 0 v il ? 0.3 ? 0.5 v nmi, extal, ports 4 to 7, p8 3 , p8 4 , p9 0 to p9 5 , port b ? 0.3 ? 0.8 v v oh v cc ? 0.5 ? ? v i oh = ? 200 a output high voltage all output pins (except reso ) 3.5 ? ? v i oh = ? 1 ma output low voltage all output pins (except reso ) v ol ? ? 0.4 v i ol = 1.6 ma a 0 to a 19 ? ? 1.0 v i ol = 10 ma reso ? ? 0.4 v i ol = 1.6 ma input leakage current stby , nmi, res , md 2 to md 0 |i in | ? ? 1.0 a v in = 0.5 v to v cc ? 0.5 v port 7 ? ? 1.0 a v in = 0.5 v to av cc ? 0.5 v 19. electrical characteristics rev.4.00 aug. 20, 2007 page 473 of 638 rej09b0395-0400 item symbol min typ max unit test conditions ports 4 to 6, a 0 to a 19 , ports 8 to b |i tsi | ? ? 1.0 a v in = 0.5 v to v cc ? 0.5 v three-state leakage current reso ? ? 10.0 a v in = 0 v input pull-up mos current ports 4 and 5 ? i p 50 ? 300 a v in = 0 v nmi c in ? ? 50 pf input capacitance all input pins except nmi ? ? 15 pf vin = 0 v f = fmin ta = 25c current dissipation * 2 normal operation i cc * 3 ? 32 (5.0 v) 47 ma f = 20 mhz ? 37 (5.0 v) 58 ma f = 25 mhz sleep mode ? 24 (5.0 v) 38 ma f = 20 mhz ? 29 (5.0 v) 47 ma f = 25 mhz module standby mode ? 19 (5.0 v) 31 ma f = 20 mhz ? 21 (5.0 v) 37 ma f = 25 mhz standby mode ? 1.0 10 a t a 50c ? ? 80 a 50c < t a analog power supply current during a/d conversion ai cc ? 0.6 1.5 ma during a/d and d/a conversion ? 0.6 1.5 ma idle ? 0.01 5.0 a daste = 0 reference current during a/d conversion ai cc ? 0.45 0.8 ma during a/d and d/a conversion ? 2.0 3.0 ma idle ? 0.01 5.0 a daste = 0 ram standby voltage v ram 2.0 ? ? v 19. electrical characteristics rev.4.00 aug. 20, 2007 page 474 of 638 rej09b0395-0400 notes: 1. do not open the pin connections of the av cc , v ref and av ss pins while the a/d converter is not in use. connect the av cc and v ref pins to the v cc and connect the av ss pin to the v ss , respectively. 2. given current consumption values are when all the output pins are made to unloaded state and, furthermore, when the on-chip pull-up mos is turned off under conditions that v ih min = v cc ? 0.5 v and v il max = 0.5 v. also, the aforesaid current consumption values are when v ih min = v cc 0.9 and v il max = 0.3 v under the condition of v ram v cc < 4.5 v. 3. i cc max. (under normal operations) = 3.0 (ma) + 0.40 (ma/(mhz v)) v cc f i cc max. (when using the sleeve) = 3.0 (ma) + 0.32 (ma/(mhz v)) v cc f i cc max. (when the sleeve + module are standing by) = 3.0 (ma) + 0.25 (ma/(mhz v)) v cc f also, the typ. values for current dissipation are reference values. 19. electrical characteristics rev.4.00 aug. 20, 2007 page 475 of 638 rej09b0395-0400 table 19.2 dc characteristics (2) conditions: v cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, v ref = 3.0 v to av cc * 1 , v ss = av ss = 0 v* 1 , t a = ? 20c to +75c (regular specifications), t a = ? 40c to +85c (wide-range specifications) item symbol min typ max unit test conditions v t ? v cc 0.2 ? ? v v t + ? ? v cc 0.7 v schmitt trigger input voltages port a, p8 0 to p8 2 v t + ? v t ? v cc 0.05 ? ? v input high voltage res , stby , nmi, md 2 to md 0 v ih v cc 0.9 ? v cc +0.3 v extal v cc 0.7 ? v cc +0.3 v port 7 v cc 0.7 ? av cc +0.3 v ports 4 to 6 p8 3 , p8 4 , p9 0 to p9 5 , port b v cc 0.7 ? v cc +0.3 v input low voltage res , stby , md 2 to md 0 v il ? 0.3 ? v cc 0.1 v nmi, extal, ports 4 to 7 p8 3 , p8 4 , p9 0 to p9 5 , port b ? 0.3 ? v cc 0.2 v v oh v cc ? 0.5 ? ? v i oh = ? 200 a output high voltage all output pins (except reso ) v cc ? 1.0 ? ? v i oh = ? 1 ma output low voltage all output pins (except reso ) v ol ? ? 0.4 v i ol = 1.6 ma a 0 to a 19 ? ? 1.0 v i ol = 5 ma reso ? ? 0.4 v i ol = 1.6 ma input leakage current stby , nmi, res , md 2 to md 0 |i in | ? ? 1.0 a v in = 0.5 v to v cc ? 0.5 v port 7 ? ? 1.0 a v in = 0.5 v to av cc ? 0.5 v 19. electrical characteristics rev.4.00 aug. 20, 2007 page 476 of 638 rej09b0395-0400 item symbol min typ max unit test conditions three-state leakage current ports 4 to 6, a 0 to a 19 , ports 8 to b |i tsi | ? ? 1.0 a v in = 0.5 v to v cc ? 0.5 v reso ? ? 10.0 a v in = 0 v input pull-up mos current ports 4 and 5 ? i p 10 ? 300 a v in = 0 v nmi c in ? ? 50 pf input capacitance all input pins except nmi ? ? 15 pf v in = 0 v f = f min t a = 25c current dissipation * 2 normal operation i cc * 3 ? 37 (3.3 v) 58 ma f = 25 mhz sleep mode ? 29 (3.3 v) 47 ma f = 25 mhz module standby mode ? 21 (3.3 v) 37 ma f = 25 mhz standby mode ? 1.0 10 a t a 50c ? ? 80 a 50c < t a analog power supply current during a/d conversion ai cc ? 0.6 1.5 ma av cc = 3.0 v during a/d and d/a conversion ? 0.6 1.5 ma av cc = 3.0 v idle ? 0.01 5.0 a daste = 0 reference current during a/d conversion ai cc ? 0.45 0.8 ma v ref = 3.0 v during a/d and d/a conversion ? 2.0 3.0 ma v ref = 3.0 v idle ? 0.01 5.0 a daste = 0 ram standby voltage v ram 2.0 ? ? v notes: 1. do not open the pin connections of the av cc , v ref and av ss pins while the a/d converter is not in use. connect the av cc and v ref pins to the v cc and connect the av ss pin to the v ss , respectively. 2. given current consumption values are when all the output pins are made to unloaded state and, furthermore, when the on-chip pull-up mos is turned off under conditions that v ih min = v cc ? 0.5 v and v il max = 0.5 v. 19. electrical characteristics rev.4.00 aug. 20, 2007 page 477 of 638 rej09b0395-0400 also, the aforesaid current consumption values are when v ih min = v cc 0.9 and v il max = 0.3 v under the condition of v ram v cc < 3.0 v. 3. i cc max. (under normal operations) = 3.0 (ma) + 0.61 (ma/(mhz v)) v cc f i cc max. (when using the sleeve) = 3.0 (ma) + 0.49 (ma/(mhz v)) v cc f i cc max. (when the sleeve + module are standing by) = 3.0 (ma) + 0.38 (ma/(mhz v)) v cc f also, the typ. values for current dissipation are reference values. table 19.3 permissible output currents condition: t a = ? 20c to +75c (regular specifications), t a = ? 40c to +85c (wide-range specifications) condition a: v cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, v ref = 3.0 to av cc , v ss = av ss = 0 v condition b: v cc = 4.5 to 5.5 v, av cc = 4.5 to 5.5 v, v ref = 4.5 to av cc , v ss = av ss = 0 v condition a, b item symbol min typ max unit a 19 to a 0 i ol ? ? 10 ma permissible output low current (per pin) other output pins ? ? 2.0 ma permissible output low current (total) total of 20 pins in a 19 to a 0 i ol ? ? 80 ma total of all output pins, including the above ? ? 120 ma permissible output high current (per pin) all output pins | ? i oh | ? ? 2.0 ma permissible output high current (total) total of all output pins |? i oh | ? ? 40 ma notes: 1. to protect chip reliability, do not exceed the output current values in table 19.3. 2. when directly driving a darlington pair or led, always insert a current-limiting resistor in the output line, as shown in figure 19.1. 19. electrical characteristics rev.4.00 aug. 20, 2007 page 478 of 638 rej09b0395-0400 h8/3008 port 2 k darlin g ton pair figure 19.1 darlington pair drive circuit (example) 19. electrical characteristics rev.4.00 aug. 20, 2007 page 479 of 638 rej09b0395-0400 19.3 ac characteristics clock timing parameters are listed in table 19.4, control signal timing parameters in table 19.5, and bus timing parameters in table 19.6. timing parameters of the on-chip supporting modules are listed in table 19.7. table 19.4 clock timing condition: t a = ? 20c to +75c (regular specifications), t a = ? 40c to +85c (wide-range specifications) condition a: v cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, v ref = 3.0 to av cc , v ss = av ss = 0 v, fmax = 25 mhz condition b: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , v ref = 4.5 to av cc , v ss = av ss = 0 v, fmax = 20 mhz condition c: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , v ref = 4.5 to av cc , v ss = av ss = 0 v, fmax = 25 mhz condition a b c item symbol min max min max min max unit test conditions clock cycle time t cyc 40 500 50 500 40 500 ns clock pulse low width t cl 10 ? 15 ? 10 ? ns figure 19.3 to figure 19.15 clock pulse high width t ch 10 ? 15 ? 10 ? ns clock rise time t cr ? 10 ? 10 ? 10 ns clock fall time t cf ? 10 ? 10 ? 10 ns clock oscillator settling time at reset t osc1 20 ? 20 ? 20 ? ms figure 19.3 clock oscillator settling time in software standby t osc2 7 ? 7 ? 7 ? ms figure 18.1 19. electrical characteristics rev.4.00 aug. 20, 2007 page 480 of 638 rej09b0395-0400 table 19.5 control signal timing condition: t a = ? 20c to +75c (regular specifications), t a = ? 40c to +85c (wide-range specifications) condition a: v cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, v ref = 3.0 to av cc , v ss = av ss = 0 v, fmax = 25 mhz condition b: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , v ref = 4.5 to av cc , v ss = av ss = 0 v, fmax = 20 mhz condition c: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , v ref = 4.5 to av cc , v ss = av ss = 0 v, fmax = 25 mhz condition a b and c item symbol min max min max unit test conditions res setup time t ress 150 ? 150 ? ns figure 19.4 res pulse width t resw 10 ? 10 ? t cyc mode programming setup time t mds 200 ? 200 ? ns reso output delay time t resd ? 50 ? 50 ns figure 19.5 reso output pulse width t resow 132 ? 132 ? t cyc nmi, irq setup time t nmis 150 ? 150 ? ns figure 19.6 nmi, irq hold time t nmih 10 ? 10 ? ns nmi, irq pulse width (in recovery from software standby mode) t nmiw 200 ? 200 ? ns 19. electrical characteristics rev.4.00 aug. 20, 2007 page 481 of 638 rej09b0395-0400 table 19.6 bus timing condition: t a = ? 20c to +75c (regular specifications), t a = ? 40c to +85c (wide-range specifications) condition a: v cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, v ref = 3.0 to av cc , v ss = av ss = 0 v, fmax = 25 mhz condition b: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , v ref = 4.5 to av cc , v ss = av ss = 0 v, fmax = 20 mhz condition c: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , v ref = 4.5 to av cc , v ss = av ss = 0 v, fmax = 25 mhz condition a b and c item symbol min max min max unit test conditions address delay time t ad ? 25 ? 25 ns address hold time t ah 0.5 t cyc ? 20 ? 0.5 t cyc ? 20 ? ns figure 19.7, figure 19.8 read strobe delay time t rsd ? 25 ? 25 ns address strobe delay time t asd ? 25 ? 25 ns write strobe delay time t wsd ? 25 ? 25 ns strobe delay time t sd ? 25 ? 25 ns write strobe pulse width 1 t wsw1 1.0 t cyc ? 25 ? 1.0 t cyc ? 25 ? ns write strobe pulse width 2 t wsw2 1.5 t cyc ? 25 ? 1.5 t cyc ? 25 ? ns address setup time 1 t as1 0.5 t cyc ? 20 ? 0.5 t cyc ? 20 ? ns address setup time 2 t as2 1.0 t cyc ? 20 ? 1.0 t cyc ? 20 ? ns read data setup time t rds 25 ? 25 ? ns read data hold time t rdh 0 ? 0 ? ns write data delay time t wdd ? 35 ? 35 ns write data setup time 1 t wds1 1.0 t cyc ? 30 ? 1.0 t cyc ? 30 ? ns write data setup time 2 t wds2 2.0 t cyc ? 30 ? 2.0 t cyc ? 30 ? ns 19. electrical characteristics rev.4.00 aug. 20, 2007 page 482 of 638 rej09b0395-0400 condition a b and c item symbol min max min max unit test conditions write data hold time t wdh 0.5 t cyc ? 15 ? 0.5 t cyc ? 15 ? ns read data access time 1 t acc1 ? 2.0 t cyc ? 45 ? 2.0 t cyc ? 45 ns figure 19.7, figure 19.8 read data access time 2 t acc2 ? 3.0 t cyc ? 45 ? 3.0 t cyc ? 45 ns read data access time 3 t acc3 ? 1.5 t cyc ? 45 ? 1.5 t cyc ? 45 ns read data access time 4 t acc4 ? 2.5 t cyc ? 45 ? 2.5 t cyc ? 45 ns precharge time 1 t pch1 1.0 t cyc ? 20 ? 1.0 t cyc ? 20 ? ns precharge time 2 t pch2 0.5 t cyc ? 20 ? 0.5 t cyc ? 20 ? ns wait setup time t wts 25 ? 25 ? ns figure 19.9 wait hold time t wth 5 ? 5 ? ns bus request setup time t brqs 25 ? 25 ? ns figure 19.10 bus acknowledge delay time 1 t bacd1 ? 30 ? 30 ns bus acknowledge delay time 2 t bacd2 ? 30 ? 30 ns bus-floating time t bzd ? 30 ? 30 ns note: in order to secure the address hold time relative to the rise of the rd strobe, address update mode 2 should be used. for details see section 6.3.5, address output method. 19. electrical characteristics rev.4.00 aug. 20, 2007 page 483 of 638 rej09b0395-0400 table 19.7 timing of on-chip supporting modules condition: t a = ? 20c to +75c (regular specifications), t a = ? 40c to +85c (wide-range specifications) condition a: v cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, v ref = 3.0 to av cc , v ss = av ss = 0 v, fmax = 25 mhz condition b: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , v ref = 4.5 to av cc , v ss = av ss = 0 v, fmax = 20 mhz condition c: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , v ref = 4.5 to av cc , v ss = av ss = 0 v, fmax = 25 mhz condition a b and c module item symbol min max min max unit test conditions output data delay time t pwd ? 50 ? 50 ns figure 19.11 input data setup time t prs 50 ? 50 ? ns ports and tpc input data hold time t prh 50 ? 50 ? ns timer output delay time t tocd ? 50 ? 50 ns figure 19.12 16-bit timer timer input setup time t tics 50 ? 50 ? ns timer clock input setup time t tcks 50 ? 50 ? ns figure 19.13 single edge t tckwh 1.5 ? 1.5 ? t cyc timer clock pulse width both edges t tckwl 2.5 ? 2.5 ? t cyc timer output delay time t tocd ? 50 ? 50 ns figure 19.12 8-bit timer timer input setup time t tics 50 ? 50 ? ns timer clock input setup time t tcks 50 ? 50 ? ns figure 19.13 single edge t tckwh 1.5 ? 1.5 ? t cyc timer clock pulse width both edges t tckwl 2.5 ? 2.5 ? t cyc 19. electrical characteristics rev.4.00 aug. 20, 2007 page 484 of 638 rej09b0395-0400 condition a b and c module item symbol min max min max unit test conditions sci asynchronous t scyc 4 ? 4 ? t cyc figure 19.14 input clock cycle synchronous 6 ? 6 ? t cyc input clock rise time t sckr ? 1.5 ? 1.5 t cyc input clock fall time t sckf ? 1.5 ? 1.5 t cyc input clock pulse width t sckw 0.4 0.6 0.4 0.6 t scyc transmit data delay time t txd ? 100 ? 100 ns figure 19.15 receive data setup time (synchronous) t rxs 100 ? 100 ? ns clock input t rxh 100 ? 100 ? ns receive data hold time (synchronous) clock output 0 ? 0 ? ns cr h r l chip output pin c = 90 pf: ports 4, 6, 8, a 19 to a 0 , d 15 to d 8 c = 30 pf: ports 9, a, b, reso input/output timin g measurement levels ? low: 0.8 v ? hi g h: 2.0 v r = 2.4 k r = 12 k l h figure 19.2 output load circuit 19. electrical characteristics rev.4.00 aug. 20, 2007 page 485 of 638 rej09b0395-0400 19.4 a/d conversion characteristics table 19.8 lists the a/d conversion characteristics. table 19.8 a/d conversion characteristics condition: t a = ? 20c to +75c (regular specifications), t a = ? 40c to +85c (wide-range specifications) condition a: v cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, v ref = 3.0 to av cc , v ss = av ss = 0 v, fmax = 25 mhz condition b: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , v ref = 4.5 to av cc , v ss = av ss = 0 v, fmax = 25 mhz condition c: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , v ref = 4.5 to av cc , v ss = av ss = 0 v, fmax = 25 mhz condition a b and c item min typ max min typ max unit resolution 10 10 10 10 10 10 bits conversion time (single mode) 5.36 ? ? 5.36 ? ? s conversion time: 134 states analog input capacitance ? ? 20 ? ? 20 pf 13 mhz ? ? 10 ? ? 10 k permissible signal-source impedance > 13 mhz ? ? 5 ? ? 5 k nonlinearity error ? ? 3.5 ? ? 3.5 lsb offset error ? ? 3.5 ? ? 3.5 lsb full-scale error ? ? 3.5 ? ? 3.5 lsb quantization error ? ? 0.5 ? ? 0.5 lsb absolute accuracy ? ? 4.0 ? ? 4.0 lsb 19. electrical characteristics rev.4.00 aug. 20, 2007 page 486 of 638 rej09b0395-0400 condition a b and c item min typ max min typ max unit resolution 10 10 10 10 10 10 bits conversion time (single mode) 5.36 ? ? 5.36 ? ? s conversion time: 70 states analog input capacitance ? ? 20 ? ? 20 pf 13 mhz ? ? 5 ? ? 5 k permissible signal-source impedance > 13 mhz ? ? 3 ? ? 3 k nonlinearity error ? ? 7.5 ? ? 7.5 lsb offset error ? ? 7.5 ? ? 7.5 lsb full-scale error ? ? 7.5 ? ? 7.5 lsb quantization error ? ? 0.5 ? ? 0.5 lsb absolute accuracy ? ? 8.0 ? ? 8.0 lsb note: * do not select 70 states as the conversion time when using an operating frequency that exceeds f = 70 (states)/5.36 ( s) 13.0 (mhz). 19. electrical characteristics rev.4.00 aug. 20, 2007 page 487 of 638 rej09b0395-0400 19.5 d/a conversion characteristics table 19.9 lists the d/a conversion characteristics. table 19.9 d/a conversion characteristics condition: t a = ? 20c to +75c (regular specifications), t a = ? 40c to +85c (wide-range specifications) condition a: v cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, v ref = 3.0 to av cc , v ss = av ss = 0 v, fmax = 25 mhz condition b: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , v ref = 4.5 to av cc , v ss = av ss = 0 v, fmax = 20 mhz condition c: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , v ref = 4.5 to av cc , v ss = av ss = 0 v, fmax = 25 mhz condition a b and c item min typ max min typ max unit conditions resolution 8 8 8 8 8 8 bits conversion time (setting time) ? ? 10 ? ? 10 s 20 pf capacitive load absolute accuracy ? 2.0 3.0 ? 1.5 2.0 lsb 2 m resistive load ? ? 2.0 ? ? 1.5 lsb 4 m resistive load 19. electrical characteristics rev.4.00 aug. 20, 2007 page 488 of 638 rej09b0395-0400 19.6 operational timing this section shows timing diagrams. 19.6.1 clock timing clock timing is shown as follows: ? oscillator settling timing figure 19.3 shows the oscillator settling timing. v cc stby res t osc1 t osc1 figure 19.3 oscillator settling timing 19. electrical characteristics rev.4.00 aug. 20, 2007 page 489 of 638 rej09b0395-0400 19.6.2 control signal timing control signal timing is shown as follows: ? reset input timing figure 19.4 shows the reset input timing. ? reset output timing figure 19.5 shows the reset output timing. ? interrupt input timing figure 19.6 shows the interrupt input timing for nmi and irq 5 to irq 0 . t ress t ress t resw t mds res md 2 to md 0 figure 19.4 reset input timing reso t resd t resow t resd figure 19.5 reset output timing 19. electrical characteristics rev.4.00 aug. 20, 2007 page 490 of 638 rej09b0395-0400 nmi irq irq e l t nmis t nmih t nmis t nmih t nmis t nmiw nmi irq j irq : ed g e-sensitive irq : level-sensitive irq (i = 0 to 5) e l i i irq (j = 0 to 5) figure 19.6 interrupt input timing 19. electrical characteristics rev.4.00 aug. 20, 2007 page 491 of 638 rej09b0395-0400 19.6.3 bus timing bus timing is shown as follows: ? basic bus cycle: two-state access figure 19.7 shows the timing of the external two-state access cycle. ? basic bus cycle: three-state access figure 19.8 shows the timing of the external three-state access cycle. ? basic bus cycle: three-state access with one wait state figure 19.9 shows the timing of the external three-state access cycle with one wait state inserted. ? bus-release mode timing figure 19.10 shows the bus-release mode timing. 19. electrical characteristics rev.4.00 aug. 20, 2007 page 492 of 638 rej09b0395-0400 t 1 t 2 t ch t ad t cl t cr t cf t asd t acc3 t as1 t cyc t cyc t sd t rds t ah t pch1 t pch2 t rdh * t pch1 t sd t ah t asd t acc3 t as1 t acc1 t asd t as1 t wsw1 t wds1 t wdh t wdd a 23 to a 0 , cs n as rd (read) d 15 to d 0 (read) hwr , lwr (write) d 15 to d 0 (write) note: * specification from the earliest ne g ation timin g of a 23 to a 0 , cs n , and rd . t rsd figure 19.7 basic bus cycle: two-state access 19. electrical characteristics rev.4.00 aug. 20, 2007 page 493 of 638 rej09b0395-0400 t 1 t 2 t 3 t acc4 t acc4 t as2 t wds2 t wsw2 t wsd t wdd t acc2 t rds a 23 to a 0 , cs n as rd (read) d 15 to d 0 (read) hwr , lwr (write) d 15 to d 0 (write) figure 19.8 basic bus cycle: three-state access 19. electrical characteristics rev.4.00 aug. 20, 2007 page 494 of 638 rej09b0395-0400 t 1 t 2 t w t 3 t wts t wts t wth as rd (read) d 15 to d 0 (read) hwr , lwr (write) d 15 to d 0 (write) wait t wth a 23 to a 0 , cs n figure 19.9 basic bus cycle: three- state access with one wait state breq back a 23 to a 0 , as , rd , hwr , lwr t brqs t brqs t bacd1 t bzd t bacd2 t bzd figure 19.10 bus-release mode timing 19. electrical characteristics rev.4.00 aug. 20, 2007 page 495 of 638 rej09b0395-0400 19.6.4 tpc and i/o port timing figure 19.11 shows the tpc and i/o port input/output timing. t 1 t 2 t 3 port 4 to b (read) port 4, 6, 8 to b (write) t prs t prh t pwd figure 19.11 tpc and i/o port input/output timing 19.6.5 timer input/output timing 16-bit timer and 8-bit timer timing are shown below. ? timer input/output timing figure 19.12 shows the timer input/output timing. ? timer external clock input timing figure 19.13 shows the timer external clock input timing. output compare * 1 input capture * 2 t tocd t tics notes: 1. tioca0 to tioca2, tiocb0 to tiocb2, tmo0, tmo2, tmio1, tmio3 2. tioca0 to tioca2, tiocb0 to tiocb2, tmio1, tmio3 figure 19.12 timer input/output timing 19. electrical characteristics rev.4.00 aug. 20, 2007 page 496 of 638 rej09b0395-0400 t tcks t tcks t tckwh t tckwl tclka to tclkd figure 19.13 timer external clock input timing 19.6.6 sci input/output timing sci timing is shown as follows: ? sci input clock timing figure 19.14 shows the sci input clock timing. ? sci input/output timing (synchronous mode) figure 19.15 shows the sci input/output timing in synchronous mode. sck 0 , sck 1 t sckw t scyc t sckr t sckf figure 19.14 sci input clock timing t scyc t txd t rxs t rxh sck 0 , sck 1 txd 0 , txd 1 (transmit data) rxd 0 , rxd 1 (receive data) figure 19.15 sci input/output timing in synchronous mode appendix a instruction set rev.4.00 aug. 20, 2007 page 497 of 638 rej09b0395-0400 appendix a instruction set a.1 instruction list operand notation symbol description rd general destination register rs general source register rn general register erd general destination register (address register or 32-bit register) ers general source register (address register or 32-bit register) ern general register (32-bit register) (ead) destination operand (eas) source operand pc program counter sp stack pointer ccr condition code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr disp displacement transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right + addition of the operands on both sides ? subtraction of the operand on the right from the operand on the left multiplication of the operands on both sides division of the operand on the left by the operand on the right logical and of the operands on both sides logical or of the operands on both sides exclusive logical or of the operands on both sides ? not (logical complement) ( ), < > contents of operand note: general registers include 8-bit registers (r0h to r7h and r0l to r7l) and 16-bit registers (r0 to r7 and e0 to e7). appendix a instruction set rev.4.00 aug. 20, 2007 page 498 of 638 rej09b0395-0400 condition code notation symbol description changed according to execution result * undetermined (no guaranteed value) 0 cleared to 0 1 set to 1 ? not affected by execution of the instruction varies depending on conditions, described in notes appendix a instruction set rev.4.00 aug. 20, 2007 page 499 of 638 rej09b0395-0400 table a.1 instruction set 1. data transfer instructions mnemoni c operation condition code operand size #xx rn @ern @(d, ern) @ ? ern/@ern+ @aa @(d, pc) @@aa ? addressing mode and instru c tion length (bytes) normal advan c ed no. of states * 1 i h n z v c mov.b #xx:8, rd mov.b rs, rd mov.b @ers, rd mov.b @(d:16, ers), rd mov.b @(d:24, ers), rd mov.b @ers+, rd mov.b @aa:8, rd mov.b @aa:16, rd mov.b @aa:24, rd mov.b rs, @erd mov.b rs, @(d:16, erd) mov.b rs, @(d:24, erd) mov.b rs, @?erd mov.b rs, @aa:8 mov.b rs, @aa:16 mov.b rs, @aa:24 mov.w #xx:16, rd mov.w rs, rd mov.w @ers, rd mov.w @(d:16, ers), rd mov.w @(d:24, ers), rd mov.w @ers+, rd mov.w @aa:16, rd b b b b b b b b b b b b b b b b w w w w w w w 2 2 2 4 8 2 2 4 6 2 4 8 2 2 4 6 4 2 2 4 8 2 4 #xx:8 rd8 rs8 rd8 @ers rd8 @(d:16, ers) rd8 @(d:24, ers) rd8 @ers rd8 ers32+1 ers32 @aa:8 rd8 @aa:16 rd8 @aa:24 rd8 rs8 @erd rs8 @(d:16, erd) rs8 @(d:24, erd) erd32 ? 1 erd32 rs8 @erd rs8 @aa:8 rs8 @aa:16 rs8 @aa:24 #xx:16 rd16 rs16 rd16 @ers rd16 @(d:16, ers) rd16 @(d:24, ers) rd16 @ers rd16 ers32+2 @erd32 @aa:16 rd16 2 2 4 6 10 6 4 6 8 4 6 10 6 4 6 8 4 2 4 6 10 6 6 ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? appendix a instruction set rev.4.00 aug. 20, 2007 page 500 of 638 rej09b0395-0400 mnemoni c operation condition code operand size #xx rn @ern @(d, ern) @ ? ern/@ern+ @aa @(d, pc) @@aa ? addressing mode and instru c tion length (bytes) normal advan c ed no. of states * 1 i h n z v c mov.w @aa:24, rd mov.w rs, @erd mov.w rs, @(d:16, erd) mov.w rs, @(d:24, erd) mov.w rs, @?erd mov.w rs, @aa:16 mov.w rs, @aa:24 mov.l #xx:32, rd mov.l ers, erd mov.l @ers, erd mov.l @(d:16, ers), erd mov.l @(d:24, ers), erd mov.l @ers+, erd mov.l @aa:16, erd mov.l @aa:24, erd mov.l ers, @erd mov.l ers, @(d:16, erd) mov.l ers, @(d:24, erd) mov.l ers, @?erd mov.l ers, @aa:16 mov.l ers, @aa:24 pop.w rn pop.l ern w w w w w w w l l l l l l l l l l l l l l w l 6 2 4 8 2 4 6 6 2 4 6 10 4 6 8 4 6 10 4 6 8 2 4 @aa:24 rd16 rs16 @erd rs16 @(d:16, erd) rs16 @(d:24, erd) erd32?2 erd32 rs16 @erd rs16 @aa:16 rs16 @aa:24 #xx:32 rd32 ers32 erd32 @ers erd32 @(d:16, ers) erd32 @(d:24, ers) erd32 @ers erd32 ers32+4 ers32 @aa:16 erd32 @aa:24 erd32 ers32 @erd ers32 @(d:16, erd) ers32 @(d:24, erd) erd32?4 erd32 ers32 @erd ers32 @aa:16 ers32 @aa:24 @sp rn16 sp+2 sp @sp ern32 sp+4 sp 8 4 6 10 6 6 8 6 2 8 10 14 10 10 12 8 10 14 10 10 12 6 10 ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? appendix a instruction set rev.4.00 aug. 20, 2007 page 501 of 638 rej09b0395-0400 mnemoni c operation condition code operand size #xx rn @ern @(d, ern) @ ? ern/@ern+ @aa @(d, pc) @@aa ? addressing mode and instru c tion length (bytes) normal advan c ed no. of states * 1 i h n z v c push.w rn push.l ern movfpe @aa:16, rd movtpe rs, @aa:16 w l b b 2 4 4 4 sp ? 2 sp rn16 @sp sp ? 4 sp ern32 @sp cannot be used in the h8/3008 cannot be used in the h8/3008 6 10 ? ? 0 ? ? ? 0 ? cannot be used in the h8/3008 cannot be used in the h8/3008 ? ? ? ? 2. arithmetic instructions mnemoni c operation condition code operand size #xx rn @ern @(d, ern) @ ? ern/@ern+ @aa @(d, pc) @@aa ? addressing mode and instru c tion length (bytes) normal advan c ed no. of states * 1 i h n z v c add.b #xx:8, rd add.b rs, rd add.w #xx:16, rd add.w rs, rd add.l #xx:32, erd add.l ers, erd addx.b #xx:8, rd addx.b rs, rd adds.l #1, erd adds.l #2, erd adds.l #4, erd inc.b rd inc.w #1, rd inc.w #2, rd b b w w l l b b l l l b w w 2 2 4 2 6 2 2 2 2 2 2 2 2 2 rd8+#xx:8 rd8 rd8+rs8 rd8 rd16+#xx:16 rd16 rd16+rs16 rd16 erd32+#xx:32 erd32 erd32+ers32 erd32 rd8+#xx:8 +c rd8 rd8+rs8 +c rd8 erd32+1 erd32 erd32+2 erd32 erd32+4 erd32 rd8+1 rd8 rd16+1 rd16 rd16+2 rd16 2 2 4 2 6 2 2 2 2 2 2 2 2 2 ? ? ? (1) ? (1) ? (2) ? (2) ? (3) ? (3) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? appendix a instruction set rev.4.00 aug. 20, 2007 page 502 of 638 rej09b0395-0400 mnemoni c operation condition code operand size #xx rn @ern @(d, ern) @ ? ern/@ern+ @aa @(d, pc) @@aa ? addressing mode and instru c tion length (bytes) normal advan c ed no. of states * 1 i h n z v c inc.l #1, erd inc.l #2, erd daa rd sub.b rs, rd sub.w #xx:16, rd sub.w rs, rd sub.l #xx:32, erd sub.l ers, erd subx.b #xx:8, rd subx.b rs, rd subs.l #1, erd subs.l #2, erd subs.l #4, erd dec.b rd dec.w #1, rd dec.w #2, rd dec.l #1, erd dec.l #2, erd das.rd mulxu. b rs, rd mulxu. w rs, erd mulxs. b rs, rd mulxs. w rs, erd divxu. b rs, rd l l b b w w l l b b l l l b w w l l b b w b w b 2 2 2 2 4 2 6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 2 erd32+1 erd32 erd32+2 erd32 rd8 decimal adjust rd8 rd8 ? rs8 rd8 rd16 ? #xx:16 rd16 rd16 ? rs16 rd16 erd32?#xx:32 erd32 erd32?ers32 erd32 rd8 ? #xx:8 ? c rd8 rd8 ? rs8 ? c rd8 erd32 ? 1 erd32 erd32 ? 2 erd32 erd32 ? 4 erd32 rd8 ? 1 rd8 rd16 ? 1 rd16 rd16 ? 2 rd16 erd32 ? 1 erd32 erd32 ? 2 erd32 rd8 decimal adjust rd8 rd8 rs8 rd16 (unsi g ned multiplication) rd16 rs16 erd32 (unsi g ned multiplication) rd8 rs8 rd16 (si g ned multiplication) rd16 rs16 erd32 (si g ned multiplication) rd16 rs8 rd16 (rdh: remainder, rdl: quotient) (unsi g ned division) 2 2 2 2 4 2 6 2 2 2 2 2 2 2 2 2 2 2 2 14 22 16 24 14 ? ? ? ? ? ? ? * * ? ? ? (1) ? (1) ? (2) ? (2) ? (3) ? (3) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? * * ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (6) (7) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? appendix a instruction set rev.4.00 aug. 20, 2007 page 503 of 638 rej09b0395-0400 mnemoni c operation condition code operand size #xx rn @ern @(d, ern) @ ? ern/@ern+ @aa @(d, pc) @@aa ? addressing mode and instru c tion length (bytes) normal advan c ed no. of states * 1 i h n z v c divxu. w rs, erd divxs. b rs, rd divxs. w rs, erd cmp.b #xx:8, rd cmp.b rs, rd cmp.w #xx:16, rd cmp.w rs, rd cmp.l #xx:32, erd cmp.l ers, erd neg.b rd neg.w rd neg.l erd extu.w rd extu.l erd exts.w rd exts.l erd w b w b b w w l l b w l w l w l 2 4 4 2 2 4 2 6 2 2 2 2 2 2 2 2 erd32 rs16 erd32 (ed: remainder, rd: quotient) (unsi g ned division) rd16 rs8 rd16 (rdh: remainder, rdl: quotient) (si g ned division) erd32 rs16 erd32 (ed: remainder, rd: quotient) (si g ned division) rd8 ? #xx:8 rd8 ? rs8 rd16 ? #xx:16 rd16 ? rs16 erd32 ? #xx:32 erd32 ? ers32 0 ? rd8 rd8 0 ? rd16 rd16 0 ? erd32 erd32 0 ( appendix a instruction set rev.4.00 aug. 20, 2007 page 504 of 638 rej09b0395-0400 3. logic instructions mnemoni c operation condition code operand size #xx rn @ern @(d, ern) @ ? ern/@ern+ @aa @(d, pc) @@aa ? addressing mode and instru c tion length (bytes) normal advan c ed no. of states * 1 i h n z v c and.b #xx:8, rd and.b rs, rd and.w #xx:16, rd and.w rs, rd and.l #xx:32, erd and.l ers, erd or.b #xx:8, rd or.b rs, rd or.w #xx:16, rd or.w rs, rd or.l #xx:32, erd or.l ers, erd xor.b #xx:8, rd xor.b rs, rd xor.w #xx:16, rd xor.w rs, rd xor.l #xx:32, erd xor.l ers, erd not.b rd not.w rd not.l erd b b w w l l b b w w l l b b w w l l b w l 2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2 rd8 #xx:8 rd8 rd8 rs8 rd8 rd16 #xx:16 rd16 rd16 rs16 rd16 erd32 #xx:32 erd32 erd32 ers32 erd32 rd8 #xx:8 rd8 rd8 rs8 rd8 rd16 #xx:16 rd16 rd16 rs16 rd16 erd32 #xx:32 erd32 erd32 ers32 erd32 rd8 #xx:8 rd8 rd8 rs8 rd8 rd16 #xx:16 rd16 rd16 rs16 rd16 erd32 #xx:32 erd32 erd32 ers32 erd32 ? rd8 rd8 ? rd16 rd16 ? rd32 rd32 2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2 ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? appendix a instruction set rev.4.00 aug. 20, 2007 page 505 of 638 rej09b0395-0400 4. shift instructions mnemoni c operation condition code operand size #xx rn @ern @(d, ern) @ ? ern/@ern+ @aa @(d, pc) @@aa ? addressing mode and instru c tion length (bytes) normal advan c ed no. of states * 1 i h n z v c shal.b rd shal.w rd shal.l erd shar.b rd shar.w rd shar.l erd shll.b rd shll.w rd shll.l erd shlr.b rd shlr.w rd shlr.l erd rotxl.b rd rotxl.w rd rotxl.l erd rotxr.b rd rotxr.w rd rotxr.l erd rotl.b rd rotl.w rd rotl.l erd rotr.b rd rotr.w rd rotr.l erd b w l b w l b w l b w l b w l b w l b w l b w l 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ? ? ? ? ? ? ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 c msb lsb c msb lsb c msb lsb c msb lsb msb lsb 0 c msb lsb 0 c c msb lsb 0c msb lsb ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? appendix a instruction set rev.4.00 aug. 20, 2007 page 506 of 638 rej09b0395-0400 5. bit manipulation instructions mnemoni c operation condition code operand size #xx rn @ern @(d, ern) @ ? ern/@ern+ @aa @(d, pc) @@aa ? addressing mode and instru c tion length (bytes) normal advan c ed no. of states * 1 i h n z v c bset #xx:3, rd bset #xx:3, @erd bset #xx:3, @aa:8 bset rn, rd bset rn, @erd bset rn, @aa:8 bclr #xx:3, rd bclr #xx:3, @erd bclr #xx:3, @aa:8 bclr rn, rd bclr rn, @erd bclr rn, @aa:8 bnot #xx:3, rd bnot #xx:3, @erd bnot #xx:3, @aa:8 bnot rn, rd bnot rn, @erd bnot rn, @aa:8 btst #xx:3, rd btst #xx:3, @erd btst #xx:3, @aa:8 btst rn, rd btst rn, @erd btst rn, @aa:8 bld #xx:3, rd b b b b b b b b b b b b b b b b b b b b b b b b b 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 (#xx:3 of rd8) 1 (#xx:3 of @erd) 1 (#xx:3 of @aa:8) 1 (rn8 of rd8) 1 (rn8 of @erd) 1 (rn8 of @aa:8) 1 (#xx:3 of rd8) 0 (#xx:3 of @erd) 0 (#xx:3 of @aa:8) 0 (rn8 of rd8) 0 (rn8 of @erd) 0 (rn8 of @aa:8) 0 (#xx:3 of rd8) ? (#xx:3 of rd8) (#xx:3 of @erd) ? (#xx:3 of @erd) (#xx:3 of @aa:8) ? (#xx:3 of @aa:8) (rn8 of rd8) ? (rn8 of rd8) (rn8 of @erd) ? (rn8 of @erd) (rn8 of @aa:8) ? (rn8 of @aa:8) ? (#xx:3 of rd8) z ? (#xx:3 of @erd) z ? (#xx:3 of @aa:8) z ? (rn8 of @rd8) z ? (rn8 of @erd) z ? (rn8 of @aa:8) z (#xx:3 of rd8) c 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 6 6 2 6 6 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? appendix a instruction set rev.4.00 aug. 20, 2007 page 507 of 638 rej09b0395-0400 mnemoni c operation condition code operand size #xx rn @ern @(d, ern) @ ? ern/@ern+ @aa @(d, pc) @@aa ? addressing mode and instru c tion length (bytes) normal advan c ed no. of states * 1 i h n z v c bld #xx:3, @erd bld #xx:3, @aa:8 bild #xx:3, rd bild #xx:3, @erd bild #xx:3, @aa:8 bst #xx:3, rd bst #xx:3, @erd bst #xx:3, @aa:8 bist #xx:3, rd bist #xx:3, @erd bist #xx:3, @aa:8 band #xx:3, rd band #xx:3, @erd band #xx:3, @aa:8 biand #xx:3, rd biand #xx:3, @erd biand #xx:3, @aa:8 bor #xx:3, rd bor #xx:3, @erd bor #xx:3, @aa:8 bior #xx:3, rd bior #xx:3, @erd bior #xx:3, @aa:8 bxor #xx:3, rd bxor #xx:3, @erd bxor #xx:3, @aa:8 bixor #xx:3, rd bixor #xx:3, @erd bixor #xx:3, @aa:8 b b b b b b b b b b b b b b b b b b b b b b b b b b b b b 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 (#xx:3 of @erd) c (#xx:3 of @aa:8) c ? (#xx:3 of rd8) c ? (#xx:3 of @erd) c ? (#xx:3 of @aa:8) c c (#xx:3 of rd8) c (#xx:3 of @erd24) c (#xx:3 of @aa:8) ? c (#xx:3 of rd8) ? c (#xx:3 of @erd24) ? c (#xx:3 of @aa:8) c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c c ? (#xx:3 of rd8) c c ? (#xx:3 of @erd24) c c ? (#xx:3 of @aa:8) c c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c c ? (#xx:3 of rd8) c c ? (#xx:3 of @erd24) c c ? (#xx:3 of @aa:8) c c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c c ? (#xx:3 of rd8) c c ? (#xx:3 of @erd24) c c ? (#xx:3 of @aa:8) c 6 6 2 6 6 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? appendix a instruction set rev.4.00 aug. 20, 2007 page 508 of 638 rej09b0395-0400 6. branching instructions mnemoni c operation bran c h condition condition code operand size #xx rn @ern @(d, ern) @ ? ern/@ern+ @aa @(d, pc) @@aa ? addressing mode and instru c tion length (bytes) normal advan c ed no. of states * 1 i h n z v c bra d:8 (bt d:8) bra d:16 (bt d:16) brn d:8 (bf d:8) brn d:16 (bf d:16) bhi d:8 bhi d:16 bls d:8 bls d:16 bcc d:8 (bhs d:8) bcc d:16 (bhs d:16) bcs d:8 (blo d:8) bcs d:16 (blo d:16) bne d:8 bne d:16 beq d:8 beq d:16 bvc d:8 bvc d:16 bvs d:8 bvs d:16 bpl d:8 bpl d:16 bmi d:8 bmi d:16 bge d:8 bge d:16 blt d:8 blt d:16 bgt d:8 bgt d:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 if condition is true then pc pc+d else next; 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? always never c z = 0 c z = 1 c = 0 c = 1 z = 0 z = 1 v = 0 v = 1 n = 0 n = 1 n v = 0 n v = 1 z (n v) = 0 appendix a instruction set rev.4.00 aug. 20, 2007 page 509 of 638 rej09b0395-0400 mnemoni c operation operation condition code operand size #xx rn @ern @(d, ern) @ ? ern/@ern+ @aa @(d, pc) @@aa ? addressing mode and instru c tion length (bytes) normal advan c ed no. of states * 1 i h n z v c ble d:8 ble d:16 jmp @ern jmp @aa:24 jmp @@aa:8 bsr d:8 bsr d:16 jsr @ern jsr @aa:24 jsr @@aa:8 rts ? ? ? ? ? ? ? ? ? ? ? 2 4 2 4 2 2 4 2 4 2 2 pc ern pc aa:24 pc @aa:8 pc @ ? sp pc pc+d:8 pc @ ? sp pc pc+d:16 pc @ ? sp pc @ern pc @ ? sp pc @aa:24 pc @ ? sp pc @aa:8 pc @sp+ 4 6 4 6 8 6 8 6 8 8 8 10 8 10 8 10 12 10 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bran c h condition if condition is true then pc pc+d else next; z (n v) = 1 appendix a instruction set rev.4.00 aug. 20, 2007 page 510 of 638 rej09b0395-0400 7. system control instructions mnemoni c operation condition code operand size #xx rn @ern @(d, ern) @ ? ern/@ern+ @aa @(d, pc) @@aa ? addressing mode and instru c tion length (bytes) normal advan c ed no. of states * 1 i h n z v c trapa #x:2 rte sleep ldc #xx:8, ccr ldc rs, ccr ldc @ers, ccr ldc @(d:16, ers), ccr ldc @(d:24, ers), ccr ldc @ers+, ccr ldc @aa:16, ccr ldc @aa:24, ccr stc ccr, rd stc ccr, @erd stc ccr, @(d:16, erd) stc ccr, @(d:24, erd) stc ccr, @?erd stc ccr, @aa:16 stc ccr, @aa:24 andc #xx:8, ccr orc #xx:8, ccr xorc #xx:8, ccr nop ? ? ? b b w w w w w w b w w w w w w b b b ? 2 2 2 4 6 10 4 6 8 2 4 6 10 4 6 8 2 2 2 2 pc @ ? sp ccr @ ? sp appendix a instruction set rev.4.00 aug. 20, 2007 page 511 of 638 rej09b0395-0400 8. block transfer instructions mnemoni c operation condition code operand size #xx rn @ern @(d, ern) @ ? ern/@ern+ @aa @(d, pc) @@aa ? addressing mode and instru c tion length (bytes) normal advan c ed no. of states * 1 i h n z v c eepmov. b eepmov. w ? ? 4 4 if r4l 0 repeat @r5 @r6 r5+1 r5 r6+1 r6 r4l ? 1 r4l until r4l=0 else next; if r4 0 repeat @r5 @r6 r5+1 r5 r6+1 r6 r4 ? 1 r4 until r4l=0 else next; ? ? ? ? ? ? ? ? ? ? ? ? 8+4n * 2 8+4n * 2 notes: 1. the number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. for other cases see section a.3, number of states required for execution. 2. n is the value set in register r4l or r4. (1) set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. (2) set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. (3) retains its previous value when the result is zero; otherwise cleared to 0. (4) set to 1 when the adjustment produces a carry; otherwise retains its previous value. (5) the number of states required for execution of an instruction that transfers data in synchronization with the e clock is variable. (6) set to 1 when the divisor is negative; otherwise cleared to 0. (7) set to 1 when the divisor is zero; otherwise cleared to 0. (8) set to 1 when the quotient is negative; otherwise cleared to 0. appendix a instruction set rev.4.00 aug. 20, 2007 page 512 of 638 rej09b0395-0400 a.2 operation code maps table a.2 operation code map (1) ah al 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f nop bra mulxu bset brn divxu bnot stc bhi mulxu bclr ldc bls divxu btst orc or.b bcc rts or xorc xor.b bcs bsr xor bor bior bxor bixor band biand andc and.b bne rte and ldc bnq trapa bld bild bst bist bvc mov bpl jmp bmi addx subx bgt jsr ble mov add addx cmp subx or xor and mov in s tr uc tion when m o s t s ignifi c ant bit of bh i s 0. in s tr uc tion when m o s t s ignifi c ant bit of bh i s 1. in s tr uc tion c o d e: table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) bvs blt bge bsr table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (3) 1 s t b y te 2n d b y te ah bh al bl add sub mov cmp mov.b eepmov appendix a instruction set rev.4.00 aug. 20, 2007 page 513 of 638 rej09b0395-0400 table a.2 operation code map (2) ah al bh 0123456789abcdef 01 0a 0b 0f 10 11 12 13 17 1a 1b 1f 58 79 7a mov inc adds daa dec subs das bra mov mov bhi cmp cmp ldc/stc bcc or or bpl bgt in s tr uc tion c o d e: bvs sleep bvc bge table a.2 (3) table a.2 (3) table a.2 (3) bne and and inc extu dec beq inc extu dec bcs xor xor shll shlr rotxl rotxr not bls sub sub brn add add inc exts dec blt inc exts dec ble shal shar rotl rotr neg bmi 1 s t b y te 2n d b y te ah bh al bl subs adds add mov sub cmp shll shlr rotxl rotxr not shal shar rotl rotr neg appendix a instruction set rev.4.00 aug. 20, 2007 page 514 of 638 rej09b0395-0400 table a.2 operation code map (3) ah albh blch cl 0123456789abcdef 01406 01c05 01d05 01f06 7cr06 7cr07 7dr06 7dr07 7eaa6 7eaa7 7faa6 7faa7 mulxs bset bset bset bset divixs bnot bnot bnot bnot mulxs bclr bclr bclr bclr divxs btst btst btst btst or xor bor bior bxor bixor band biand and bld bild bst bist in s tr uc tion when m o s t s ignifi c ant bit of dh i s 0. in s tr uc tion when m o s t s ignifi c ant bit of dh i s 1. in s tr uc tion c o d e: * * * * * * * * 1 1 1 1 2 2 2 2 bor bior bxor bixor band biand bld bild bst bist notes: 1. 2. r is the re g ister desi g nation field. aa is the absolute address field. 1 s t b y te 2n d b y te ah bh al bl 3 r d b y te ch dh cl dl 4th b y te ldc stc ldc ldc ldc stc stc stc appendix a instruction set rev.4.00 aug. 20, 2007 page 515 of 638 rej09b0395-0400 a.3 number of states required for execution the tables in this section can be used to calculate the number of states required for instruction execution by the h8/300h cpu. table a.4 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instru ction. table a.3 indicates the number of states required per cycle according to the bus size. the number of states required for execution of an instruction can be calculated from these two tables as follows: number of states = i s i + j s j + k s k + l s l + m s m + n s n examples of calculation of number of states required for execution examples: advanced mode, stack located in external address space, on-chip supporting modules accessed with 8-bit bus width, external devices acce ssed in three states with one wait state and 16-bit bus width. bset #0, @ffffc7:8 from table a.4, i = l = 2 and j = k = m = n = 0 from table a.3, s i = 4 and s l = 3 number of states = 2 4 + 2 3 = 14 jsr @@30 from table a.4, i = j = k = 2 and l = m = n = 0 from table a.3, s i = s j = s k = 4 number of states = 2 4 + 2 4 + 2 4 = 24 appendix a instruction set rev.4.00 aug. 20, 2007 page 516 of 638 rej09b0395-0400 table a.3 number of states per cycle access conditions external device on-chip sup- porting module 8-bit bus 16-bit bus cycle on-chip memory 8-bit bus 16-bit bus 2-state access 3-state access 2-state access 3-state access instruction fetch s i 2 6 3 4 6 + 2m 2 3 + m branch address read s j stack operation s k byte data access s l 3 2 3 + m word data access s m 6 4 6 + 2m internal operation s n 1 legend: m: number of wait states inserted into external device access appendix a instruction set rev.4.00 aug. 20, 2007 page 517 of 638 rej09b0395-0400 table a.4 number of cycles per instruction instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n add add.b #xx:8, rd add.b rs, rd add.w #xx:16, rd add.w rs, rd add.l #xx:32, erd add.l ers, erd 1 1 2 1 3 1 adds adds #1/2/4, erd 1 addx addx #xx:8, rd addx rs, rd 1 1 and and.b #xx:8, rd and.b rs, rd and.w #xx:16, rd and.w rs, rd and.l #xx:32, erd and.l ers, erd 1 1 2 1 3 2 andc andc #xx:8, ccr 1 band band #xx:3, rd band #xx:3, @erd band #xx:3, @aa:8 1 2 2 1 1 bcc bra d:8 (bt d:8) brn d:8 (bf d:8) bhi d:8 bls d:8 bcc d:8 (bhs d:8) bcs d:8 (blo d:8) bne d:8 beq d:8 bvc d:8 bvs d:8 bpl d:8 bmi d:8 bge d:8 blt d:8 bgt d:8 ble d:8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 appendix a instruction set rev.4.00 aug. 20, 2007 page 518 of 638 rej09b0395-0400 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bcc bra d:16 (bt d:16) brn d:16 (bf d:16) bhi d:16 bls d:16 bcc d:16 (bhs d:16) bcs d:16 (blo d:16) bne d:16 beq d:16 bvc d:16 bvs d:16 bpl d:16 bmi d:16 bge d:16 blt d:16 bgt d:16 ble d:16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 bclr bclr #xx:3, rd bclr #xx:3, @erd bclr #xx:3, @aa:8 bclr rn, rd bclr rn, @erd bclr rn, @aa:8 1 2 2 1 2 2 2 2 2 2 biand biand #xx:3, rd biand #xx:3, @erd biand #xx:3, @aa:8 1 2 2 1 1 bild bild #xx:3, rd bild #xx:3, @erd bild #xx:3, @aa:8 1 2 2 1 1 bior bior #xx:8, rd bior #xx:8, @erd bior #xx:8, @aa:8 1 2 2 1 1 bist bist #xx:3, rd bist #xx:3, @erd bist #xx:3, @aa:8 1 2 2 2 2 bixor bixor #xx:3, rd bixor #xx:3, @erd bixor #xx:3, @aa:8 1 2 2 1 1 bld bld #xx:3, rd bld #xx:3, @erd bld #xx:3, @aa:8 1 2 2 1 1 appendix a instruction set rev.4.00 aug. 20, 2007 page 519 of 638 rej09b0395-0400 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bnot bnot #xx:3, rd bnot #xx:3, @erd bnot #xx:3, @aa:8 bnot rn, rd bnot rn, @erd bnot rn, @aa:8 1 2 2 1 2 2 2 2 2 2 bor bor #xx:3, rd bor #xx:3, @erd bor #xx:3, @aa:8 1 2 2 1 1 bset bset #xx:3, rd bset #xx:3, @erd bset #xx:3, @aa:8 bset rn, rd bset rn, @erd bset rn, @aa:8 1 2 2 1 2 2 2 2 2 2 bsr bsr d:8 normal 2 1 advanced 2 2 bsr d:16 normal 2 1 2 advanced 2 2 2 bst bst #xx:3, rd bst #xx:3, @erd bst #xx:3, @aa:8 1 2 2 2 2 btst btst #xx:3, rd btst #xx:3, @erd btst #xx:3, @aa:8 btst rn, rd btst rn, @erd btst rn, @aa:8 1 2 2 1 2 2 1 1 1 1 bxor bxor #xx:3, rd bxor #xx:3, @erd bxor #xx:3, @aa:8 1 2 2 1 1 cmp cmp.b #xx:8, rd cmp.b rs, rd cmp.w #xx:16, rd cmp.w rs, rd cmp.l #xx:32, erd cmp.l ers, erd 1 1 2 1 3 1 daa daa rd 1 das das rd 1 appendix a instruction set rev.4.00 aug. 20, 2007 page 520 of 638 rej09b0395-0400 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n dec dec.b rd dec.w #1/2, rd dec.l #1/2, erd 1 1 1 divxs divxs.b rs, rd divxs.w rs, erd 2 2 12 20 divxu divxu.b rs, rd divxu.w rs, erd 1 1 12 20 eepmov eepmov.b eepmov.w 2 2 2n + 2 * 1 2n + 2 * 1 exts exts.w rd exts.l erd 1 1 extu extu.w rd extu.l erd 1 1 inc inc.b rd inc.w #1/2, rd inc.l #1/2, erd 1 1 1 jmp jmp @ern 2 jmp @aa:24 2 2 jmp @@aa:8 normal 2 1 2 advanced 2 2 2 jsr jsr @ern normal 2 1 advanced 2 2 jsr @aa:24 normal 2 1 2 advanced 2 2 2 jsr @@aa:8 normal 2 1 1 advanced 2 2 2 ldc ldc #xx:8, ccr ldc rs, ccr ldc @ers, ccr ldc @(d:16, ers), ccr ldc @(d:24, ers), ccr ldc @ers+, ccr ldc @aa:16, ccr ldc @aa:24, ccr 1 1 2 3 5 2 3 4 1 1 1 1 1 1 2 appendix a instruction set rev.4.00 aug. 20, 2007 page 521 of 638 rej09b0395-0400 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n mov mov.b #xx:8, rd mov.b rs, rd mov.b @ers, rd mov.b @(d:16, ers), rd mov.b @(d:24, ers), rd mov.b @ers+, rd mov.b @aa:8, rd mov.b @aa:16, rd mov.b @aa:24, rd mov.b rs, @erd mov.b rs, @(d:16, erd) mov.b rs, @(d:24, erd) mov.b rs, @?erd mov.b rs, @aa:8 mov.b rs, @aa:16 mov.b rs, @aa:24 mov.w #xx:16, rd mov.w rs, rd mov.w @ers, rd mov.w @(d:16, ers), rd mov.w @(d:24, ers), rd mov.w @ers+, rd mov.w @aa:16, rd mov.w @aa:24, rd mov.w rs, @erd mov.w rs, @(d:16, erd) mov.w rs, @(d:24, erd) mov.w rs, @?erd mov.w rs, @aa:16 mov.w rs, @aa:24 1 1 1 2 4 1 1 2 3 1 2 4 1 1 2 3 2 1 1 2 4 1 2 3 1 2 4 1 2 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 mov.l #xx:32, erd mov.l ers, erd mov.l @ers, erd mov.l @(d:16, ers), erd mov.l @(d:24, ers), erd mov.l @ers+, erd mov.l @aa:16, erd mov.l @aa:24, erd mov.l ers, @erd mov.l ers, @(d:16, erd) mov.l ers, @(d:24, erd) mov.l ers, @?erd mov.l ers, @aa:16 mov.l ers, @aa:24 3 1 2 3 5 2 3 4 2 3 5 2 3 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 appendix a instruction set rev.4.00 aug. 20, 2007 page 522 of 638 rej09b0395-0400 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n movfpe movfpe @aa:16, rd * 2 2 1 movtpe movtpe rs, @aa:16 * 2 2 1 mulxs mulxs.b rs, rd mulxs.w rs, erd 2 2 12 20 mulxu mulxu.b rs, rd mulxu.w rs, erd 1 1 12 20 neg neg.b rd neg.w rd neg.l erd 1 1 1 nop nop 1 not not.b rd not.w rd not.l erd 1 1 1 or or.b #xx:8, rd or.b rs, rd or.w #xx:16, rd or.w rs, rd or.l #xx:32, erd or.l ers, erd 1 1 2 1 3 2 orc orc #xx:8, ccr 1 pop pop.w rn pop.l ern 1 2 1 2 2 2 push push.w rn push.l ern 1 2 1 2 2 2 rotl rotl.b rd rotl.w rd rotl.l erd 1 1 1 rotr rotr.b rd rotr.w rd rotr.l erd 1 1 1 rotxl rotxl.b rd rotxl.w rd rotxl.l erd 1 1 1 rotxr rotxr.b rd rotxr.w rd rotxr.l erd 1 1 1 rte rte 2 2 2 appendix a instruction set rev.4.00 aug. 20, 2007 page 523 of 638 rej09b0395-0400 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n rts rts normal 2 1 2 advanced 2 2 2 shal shal.b rd shal.w rd shal.l erd 1 1 1 shar shar.b rd shar.w rd shar.l erd 1 1 1 shll shll.b rd shll.w rd shll.l erd 1 1 1 shlr shlr.b rd shlr.w rd shlr.l erd 1 1 1 sleep sleep 1 stc stc ccr, rd stc ccr, @erd stc ccr, @(d:16, erd) stc ccr, @(d:24, erd) stc ccr, @?erd stc ccr, @aa:16 stc ccr, @aa:24 1 2 3 5 2 3 4 1 1 1 1 1 1 2 sub sub.b rs, rd sub.w #xx:16, rd sub.w rs, rd sub.l #xx:32, erd sub.l ers, erd 1 2 1 3 1 subs subs #1/2/4, erd 1 subx subx #xx:8, rd subx rs, rd 1 1 trapa trapa #x:2 normal 2 1 2 4 advanced 2 2 2 4 xor xor.b #xx:8, rd xor.b rs, rd xor.w #xx:16, rd xor.w rs, rd xor.l #xx:32, erd xor.l ers, erd 1 1 2 1 3 2 xorc xorc #xx:8, ccr 1 notes: 1. n is the value set in register r4l or r4. the source and destination are accessed n + 1 times each. 2. not available in the h8/3008. appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 524 of 638 rej09b0395-0400 appendix b internal i/o registers b.1 address list bit names address (low) register name data bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'ee000 ? ? ? ? ? ? ? ? ? h'ee001 ? ? ? ? ? ? ? ? ? h'ee002 ? ? ? ? ? ? ? ? ? h'ee003 p4ddr 8 p4 7 ddr p4 6 ddr p4 5 ddr p4 4 ddr p4 3 ddr p4 2 ddr p4 1 ddr p4 0 ddr port 4 h'ee004 ? ? ? ? ? ? ? ? ? h'ee005 p6ddr 8 ? p6 6 ddr p6 5 ddr p6 4 ddr p6 3 ddr p6 2 ddr p6 1 ddr p6 0 ddr port 6 h'ee006 ? ? ? ? ? ? ? ? ? h'ee007 p8ddr 8 ? ? ? p8 4 ddr p8 3 ddr p8 2 ddr p8 1 ddr p8 0 ddr port 8 h'ee008 p9ddr 8 ? ? p9 5 ddr p9 4 ddr p9 3 ddr p9 2 ddr p9 1 ddr p9 0 ddr port 9 h'ee009 paddr 8 pa 7 ddr pa 6 ddr pa 5 ddr pa 4 ddr pa 3 ddr pa 2 ddr pa 1 ddr pa 0 ddr port a h'ee00a pbddr 8 pb 7 ddr pb 6 ddr pb 5 ddr pb 4 ddr pb 3 ddr pb 2 ddr pb 1 ddr pb 0 ddr port b h'ee00b ? ? ? ? ? ? ? ? ? h'ee00c ? ? ? ? ? ? ? ? ? h'ee00d ? ? ? ? ? ? ? ? ? h'ee00e ? ? ? ? ? ? ? ? ? h'ee00f ? ? ? ? ? ? ? ? ? h'ee010 ? ? ? ? ? ? ? ? ? h'ee011 mdcr 8 ? ? ? ? ? mds2 mds1 mds0 system control h'ee012 syscr 8 ssby sts2 sts1 sts0 ue nmieg ssoe rame h'ee013 brcr 8 a23e a22e a21e a20e ? ? ? brle bus controller h'ee014 iscr 8 ? ? irq5sc irq4sc irq3sc irq2sc irq1sc irq0sc h'ee015 ier 8 ? ? irq5e irq4e irq3e irq2e irq1e irq0e interrupt controller h'ee016 isr 8 ? ? irq5f irq4f irq3f irq2f irq1f irq0f h'ee017 ? ? ? ? ? ? ? ? ? h'ee018 ipra 8 ipra7 ipra6 ipra5 ipra4 ipra3 ipra2 ipra1 ipra0 h'ee019 iprb 8 iprb7 iprb6 ? ? iprb3 iprb2 ? ? h'ee01a dastcr 8 ? ? ? ? ? ? ? daste d/a converter h'ee01b divcr 8 ? ? ? ? ? ? div1 div0 system control h'ee01c mstcrh 8 pstop ? ? ? ? ? mstph1 mstph0 h'ee01d mstcrl 8 ? ? ? mstpl4 mstpl3 mstpl2 ? mstpl0 h'ee01e adrcr 8 ? ? ? ? ? ? ? adrctl bus controller h'ee01f cscr 8 cs7e cs6e cs5e cs4e ? ? ? ? appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 525 of 638 rej09b0395-0400 bit names address (low) register name data bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'ee020 abwcr 8 abw7 abw6 abw5 abw4 abw3 abw2 abw1 abw0 bus controller h'ee021 astcr 8 ast7 ast6 ast5 ast4 ast3 ast2 ast1 ast0 h'ee022 wcrh 8 w71 w70 w61 w60 w51 w50 w41 w40 h'ee023 wcrl 8 w31 w30 w21 w20 w11 w10 w01 w00 h'ee024 bcr 8 icis1 icis0 ? * 1 ? * 1 ? * 1 ? * 1 rdea waite h'ee025 ? ? ? ? ? ? ? ? ? h'ee026 reserved area (access prohibited) h'ee027 h'ee028 h'ee029 h'ee02a h'ee02b h'ee02c h'ee02d h'ee02e h'ee02f h'ee030 reserved area (access prohibited) h'ee031 h'ee032 h'ee033 h'ee034 h'ee035 h'ee036 h'ee037 h'ee038 h'ee039 h'ee03a h'ee03b h'ee03c h'ee03d h'ee03e p4pcr 8 p4 7 pcr p4 6 pcr p4 5 pcr p4 4 pcr p4 3 pcr p4 2 pcr p4 1 pcr p4 0 pcr port 4 h'ee03f reserved area (access prohibited) appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 526 of 638 rej09b0395-0400 bit names address (low) register name data bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'ee040 reserved area (access prohibited) h'ee041 h'ee042 h'ee043 h'ee044 h'ee045 h'ee046 h'ee047 h'ee048 h'ee049 h'ee04a h'ee04b h'ee04c h'ee04d h'ee04e h'ee04f h'ee050 reserved area (access prohibited) h'ee051 h'ee052 h'ee053 h'ee054 h'ee055 h'ee056 h'ee057 h'ee058 h'ee059 h'ee05a h'ee05b h'ee05c h'ee05d h'ee05e h'ee05f appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 527 of 638 rej09b0395-0400 bit names address (low) register name data bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'ee060 reserved area (access prohibited) h'ee061 h'ee062 h'ee063 h'ee064 h'ee065 h'ee066 h'ee067 h'ee068 h'ee069 h'ee06a h'ee06b h'ee06c h'ee06d h'ee06e h'ee06f h'ee070 reserved area (access prohibited) h'ee071 h'ee072 h'ee073 h'ee074 h'ee075 h'ee076 h'ee077 h'ee078 h'ee079 h'ee07a h'ee07b h'ee07c h'ee07d h'ee07e h'ee07f appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 528 of 638 rej09b0395-0400 bit names address (low) register name data bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'ee080 reserved area (access prohibited) h'ee081 h'ee082 h'ee083 h'ee084 h'ee085 h'ee086 h'ee087 h'ee088 h'ee089 h'ee08a h'ee08b h'ee08c h'ee08d h'ee08e h'ee08f h'ee090 reserved area (access prohibited) h'ee091 h'ee092 h'ee093 h'ee094 h'ee095 h'ee096 h'ee097 h'ee098 h'ee099 h'ee09a h'ee09b h'ee09c h'ee09d h'ee09e h'ee09f appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 529 of 638 rej09b0395-0400 bit names address (low) register name data bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'ee0a0 reserved area (access prohibited) h'ee0a1 h'ee0a2 h'ee0a3 h'ee0a4 h'ee0a5 h'ee0a6 h'ee0a7 h'ee0a8 h'ee0a9 h'ee0aa h'ee0ab h'ee0ac h'ee0ad h'ee0ae h'ee0af h'ee0b0 reserved area (access prohibited) h'ee0b1 h'ee0b2 h'ee0b3 h'ee0b4 h'ee0b5 h'ee0b6 h'ee0b7 h'ee0b8 h'ee0b9 h'ee0ba h'ee0bb h'ee0bc h'ee0bd h'ee0be h'ee0bf appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 530 of 638 rej09b0395-0400 bit names address (low) register name data bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'ee0c0 reserved area (access prohibited) h'ee0c1 h'ee0c2 h'ee0c3 h'ee0c4 h'ee0c5 h'ee0c6 h'ee0c7 h'ee0c8 h'ee0c9 h'ee0ca h'ee0cb h'ee0cc h'ee0cd h'ee0ce h'ee0cf h'ee0d0 reserved area (access prohibited) h'ee0d1 h'ee0d2 h'ee0d3 h'ee0d4 h'ee0d5 h'ee0d6 h'ee0d7 h'ee0d8 h'ee0d9 h'ee0da h'ee0db h'ee0dc h'ee0dd h'ee0de h'ee0df appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 531 of 638 rej09b0395-0400 bit names address (low) register name data bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'ee0e0 reserved area (access prohibited) h'ee0e1 h'ee0e2 h'ee0e3 h'ee0e4 h'ee0e5 h'ee0e6 h'ee0e7 h'ee0e8 h'ee0e9 h'ee0ea h'ee0eb h'ee0ec h'ee0ed h'ee0ee h'ee0ef h'ee0f0 reserved area (access prohibited) h'ee0f1 h'ee0f2 h'ee0f3 h'ee0f4 h'ee0f5 h'ee0f6 h'ee0f7 h'ee0f8 h'ee0f9 h'ee0fa h'ee0fb h'ee0fc h'ee0fd h'ee0fe h'ee0ff appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 532 of 638 rej09b0395-0400 bit names address (low) register name data bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'fff20 reserved area (access prohibited) h'fff21 h'fff22 h'fff23 h'fff24 h'fff25 h'fff26 h'fff27 h'fff28 h'fff29 h'fff2a h'fff2b h'fff2c h'fff2d h'fff2e h'fff2f h'fff30 reserved area (access prohibited) h'fff31 h'fff32 h'fff33 h'fff34 h'fff35 h'fff36 h'fff37 h'fff38 h'fff39 h'fff3a h'fff3b h'fff3c h'fff3d h'fff3e h'fff3f appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 533 of 638 rej09b0395-0400 bit names address (low) register name data bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'fff40 ? ? ? ? ? ? ? ? ? h'fff41 ? ? ? ? ? ? ? ? ? h'fff42 ? ? ? ? ? ? ? ? ? h'fff43 ? ? ? ? ? ? ? ? ? h'fff44 ? ? ? ? ? ? ? ? ? h'fff45 ? ? ? ? ? ? ? ? ? h'fff46 ? ? ? ? ? ? ? ? ? h'fff47 ? ? ? ? ? ? ? ? ? h'fff48 ? ? ? ? ? ? ? ? ? h'fff49 ? ? ? ? ? ? ? ? ? h'fff4a ? ? ? ? ? ? ? ? ? h'fff4b ? ? ? ? ? ? ? ? ? h'fff4c ? ? ? ? ? ? ? ? ? h'fff4d ? ? ? ? ? ? ? ? ? h'fff4e ? ? ? ? ? ? ? ? ? h'fff4f ? ? ? ? ? ? ? ? ? h'fff50 ? ? ? ? ? ? ? ? ? h'fff51 ? ? ? ? ? ? ? ? ? h'fff52 ? ? ? ? ? ? ? ? ? h'fff53 ? ? ? ? ? ? ? ? ? h'fff54 ? ? ? ? ? ? ? ? ? h'fff55 ? ? ? ? ? ? ? ? ? h'fff56 ? ? ? ? ? ? ? ? ? h'fff57 ? ? ? ? ? ? ? ? ? h'fff58 ? ? ? ? ? ? ? ? ? h'fff59 ? ? ? ? ? ? ? ? ? h'fff5a ? ? ? ? ? ? ? ? ? h'fff5b ? ? ? ? ? ? ? ? ? h'fff5c ? ? ? ? ? ? ? ? ? h'fff5d ? ? ? ? ? ? ? ? ? h'fff5e ? ? ? ? ? ? ? ? ? h'fff5f ? ? ? ? ? ? ? ? ? appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 534 of 638 rej09b0395-0400 bit names address (low) register name data bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'fff60 tstr 8 ? ? ? ? ? str2 str1 str0 h'fff61 tsnc 8 ? ? ? ? ? sync2 sync1 sync0 16-bit timer, (all channels) h'fff62 tmdr 8 ? mdf fdir ? ? pwm2 pwm1 pwm0 h'fff63 tolr 8 ? ? tob2 toa2 tob1 toa1 tob0 toa0 h'fff64 tisra 8 ? imiea2 imiea1 imiea0 ? imfa2 imfa1 imfa0 h'fff65 tisrb 8 ? imieb2 imieb1 imieb0 ? imfb2 imfb1 imfb0 h'fff66 tisrc 8 ? ovie2 ovie1 ovie0 ? ovf2 ovf1 ovf0 h'fff67 ? ? ? ? ? ? ? ? ? h'fff68 16tcr0 8 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 h'fff69 tior0 8 ? iob2 iob1 iob0 ? ioa2 ioa1 ioa0 16-bit timer channel 0 h'fff6a 16tcnt0h 16 h'fff6b 16tcnt0l h'fff6c gra0h 16 h'fff6d gra0l h'fff6e grb0h 16 h'fff6f grb0l h'fff70 16tcr1 8 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 h'fff71 tior1 8 ? iob2 iob1 iob0 ? ioa2 ioa1 ioa0 16-bit timer channel 1 h'fff72 16tcnt1h 16 h'fff73 16tcnt1l h'fff74 gra1h 16 h'fff75 gra1l h'fff76 grb1h 16 h'fff77 grb1l h'fff78 16tcr2 8 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 h'fff79 tior2 8 ? iob2 iob1 iob0 ? ioa2 ioa1 ioa0 16-bit timer channel 2 h'fff7a 16tcnt2h 16 h'fff7b 16tcnt2l h'fff7c gra2h 16 h'fff7d gra2l h'fff7e grb2h 16 h'fff7f grb2l appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 535 of 638 rej09b0395-0400 bit names address (low) register name data bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'fff80 8tcr0 16 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 h'fff81 8tcr1 16 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 h'fff82 8tcsr0 16 cmfb cmfa ovf adte ois3 ois2 os1 os0 h'fff83 8tcsr1 16 cmfb cmfa ovf ice ois3 ois2 os1 os0 8-bit timer channels 0 and 1 h'fff84 tcora0 16 h'fff85 tcora1 16 h'fff86 tcorb0 16 h'fff87 tcorb1 16 h'fff88 8tcnt0 16 h'fff89 8tcnt1 16 h'fff8a ? ? ? ? ? ? ? ? ? h'fff8b ? ? ? ? ? ? ? ? ? h'fff8c tcsr * 2 8 ovf wt/ it tme ? ? cks2 cks1 cks0 wdt h'fff8d tcnt * 2 8 h'fff8e ? ? ? ? ? ? ? ? ? h'fff8f rstcsr * 2 8 wrst rstoe ? ? ? ? ? ? h'fff90 8tcr2 16 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 h'fff91 8tcr3 16 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 h'fff92 8tcsr2 16 cmfb cmfa ovf ? ois3 ois2 os1 os0 8-bit timer channels 2 and 3 h'fff93 8tcsr3 16 cmfb cmfa ovf ice ois3 ois2 os1 os0 h'fff94 tcora2 16 h'fff95 tcora3 16 h'fff96 tcorb2 16 h'fff97 tcorb3 16 h'fff98 8tcnt2 16 h'fff99 8tcnt3 16 h'fff9a ? ? ? ? ? ? ? ? ? h'fff9b ? ? ? ? ? ? ? ? ? h'fff9c dadr0 8 d/a converter h'fff9d dadr1 8 h'fff9e dacr 8 daoe1 daoe0 dae ? ? ? ? ? h'fff9f ? 8 ? ? ? ? ? ? ? ? appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 536 of 638 rej09b0395-0400 bit names address (low) register name data bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'fffa0 tpmr 8 ? ? ? ? g3nov g2nov g1nov g0nov tpc h'fffa1 tpcr 8 g3cms1 g3cms0 g2cms1 g2cms0 g1cms1 g1cms0 g0cms1 g0cms0 h'fffa2 nderb 8 nder15 nder14 nder13 nder12 nder11 nder10 nder9 nder8 h'fffa3 ndera 8 nder7 nder6 nder5 nder4 nder3 nder2 nder1 nder0 h'fffa4 ndrb * 3 8 ndr15 ndr14 ndr13 ndr12 ndr11 ndr10 ndr9 ndr8 ndr15 ndr14 ndr13 ndr12 ? ? ? ? h'fffa5 ndra * 3 8 ndr7 ndr6 ndr5 ndr4 ndr3 ndr2 ndr1 ndr0 ndr7 ndr6 ndr5 ndr4 ? ? ? ? h'fffa6 ndrb * 3 8 ? ? ? ? ? ? ? ? ? ? ? ? ndr11 ndr10 ndr9 ndr8 h'fffa7 ndra * 3 8 ? ? ? ? ? ? ? ? ? ? ? ? ndr3 ndr2 ndr1 ndr0 h'fffa8 ? ? ? ? ? ? ? ? ? h'fffa9 ? ? ? ? ? ? ? ? ? h'fffaa ? ? ? ? ? ? ? ? ? h'fffab ? ? ? ? ? ? ? ? ? h'fffac ? ? ? ? ? ? ? ? ? h'fffad ? ? ? ? ? ? ? ? ? h'fffae ? ? ? ? ? ? ? ? ? h'fffaf ? ? ? ? ? ? ? ? ? h'fffb0 smr 8 c/ a chr pe o/ e stop mp cks1 cks0 sci channel 0 h'fffb1 brr 8 h'fffb2 scr 8 tie rie te re mpie teie cke1 cke0 h'fffb3 tdr 8 h'fffb4 ssr 8 tdre rdrf orer fer/ers per tend mpb mpbt h'fffb5 rdr 8 h'fffb6 scmr 8 ? ? ? ? sdir sinv ? smif h'fffb7 reserved area (access prohibited) h'fffb8 smr 8 c/ a chr pe o/ e stop mp cks1 cks0 sci channel 1 h'fffb9 brr 8 h'fffba scr 8 tie rie te re mpie teie cke1 cke0 h'fffbb tdr 8 h'fffbc ssr 8 tdre rdrf orer fer/ers per tend mpb mpbt h'fffbd rdr 8 h'fffbe scmr 8 ? ? ? ? sdir sinv ? smif h'fffbf reserved area (access prohibited) appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 537 of 638 rej09b0395-0400 bit names address (low) register name data bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'fffc0 reserved area (access prohibited) h'fffc1 h'fffc2 h'fffc3 h'fffc4 h'fffc5 h'fffc6 h'fffc7 h'fffc8 h'fffc9 h'fffca h'fffcb h'fffcc h'fffcd h'fffce h'fffcf h'fffd0 ? ? ? ? ? ? ? ? ? h'fffd1 ? ? ? ? ? ? ? ? ? h'fffd2 ? ? ? ? ? ? ? ? ? h'fffd3 p4dr 8 p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 port 4 h'fffd4 ? ? ? ? ? ? ? ? ? h'fffd5 p6dr 8 p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 port 6 h'fffd6 p7dr 8 p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 port 7 h'fffd7 p8dr 8 ? ? ? p8 4 p8 3 p8 2 p8 1 p8 0 port 8 h'fffd8 p9dr 8 ? ? p9 5 p9 4 p9 3 p9 2 p9 1 p9 0 port 9 h'fffd9 padr 8 pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 port a h'fffda pbdr 8 pb 7 pb 6 pb 5 pb 4 pb 3 pb 2 pb 1 pb 0 port b h'fffdb ? ? ? ? ? ? ? ? ? h'fffdc ? ? ? ? ? ? ? ? ? h'fffdd ? ? ? ? ? ? ? ? ? h'fffde ? ? ? ? ? ? ? ? ? h'fffdf ? ? ? ? ? ? ? ? ? appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 538 of 638 rej09b0395-0400 bit names address (low) register name data bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'fffe0 addrah 8 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d converter h'fffe1 addral 8 ad1 ad0 ? ? ? ? ? ? h'fffe2 addrbh 8 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'fffe3 addrbl 8 ad1 ad0 ? ? ? ? ? ? h'fffe4 addrch 8 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'fffe5 addrcl 8 ad1 ad0 ? ? ? ? ? ? h'fffe6 addrdh 8 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'fffe7 addrdl 8 ad1 ad0 ? ? ? ? ? ? h'fffe8 adcsr 8 adf adie adst scan cks ch2 ch1 ch0 h'fffe9 adcr 8 trge ? ? ? ? ? ? ? legend: wdt: watchdog timer tpc: programmable timing pattern controller sci: serial communication interface notes: 1. writing to bits 5 to 2 of bcr is prohibited. 2. for the procedure for writing to tcsr, tcnt, and rstcsr, see section 11.2.4, notes on register rewriting. 3. the address depends on the output trigger setting. appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 539 of 638 rej09b0395-0400 b.2 functions tstr ? timer start register h'60 itu (all channels) re g ister name address to which the re g ister is mapped name of on-chip supportin g module re g ister acronym bit numbers initial bit values names of the bits. dashes (?) indicate reserved bits. full name of bit descriptions of bit settin g s read only write only read and write r w r/w possible types of access bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 str4 0 r/w 3 str3 0 r/w 0 str0 0 r/w 2 str2 0 r/w 1 str1 0 r/w counter start 0 0 tcnt0 is halted 1 tcnt0 is countin g counter start 3 0 tcnt3 is halted 1 tcnt3 is countin g counter start 1 0 tcnt1 is halted 1 tcnt1 is countin g counter start 2 0 tcnt2 is halted 1 tcnt2 is countin g counter start 4 0 tcnt4 is halted 1 tcnt4 is countin g appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 540 of 638 rej09b0395-0400 p4ddr?port 4 data direction register h ' ee003 port 4 bit initial value read/write 0 w 7 p4 7 ddr 0 w 6 p4 6 ddr 0 w 5 p4 5 ddr 0 w 4 p4 4 ddr 0 w 3 p4 3 ddr 0 w 2 p4 2 ddr 0 w 1 p4 1 ddr 0 w 0 p4 0 ddr port 4 input/output select 0 1 generic input generic output p6ddr?port 6 data direction register h ' ee005 port 6 bit 7 ? 6 p6 6 ddr 5 p6 5 ddr 4 p6 4 ddr 3 p6 3 ddr 2 p6 2 ddr 1 p6 1 ddr 0 p6 0 ddr initial value read/write 10 w 0 w 0 w 0 w 0 w 0 w 0 w port 6 input/output select 0 1 generic input generic output ? p8ddr?port 8 data direction register h ' ee007 port 8 bit initial value read/write 7654 p8 4 ddr 0 w 3 p8 3 ddr 0 w 2 p8 2 ddr 0 w 1 p8 1 ddr 0 w 0 p8 0 ddr port 8 input/output select 0 1 generic input generic output initial value read/write 111 0 w 0 w 0 w 0 w modes 1 to 4 modes 5 to 7 1110 w 1 w ? ? ? ? ? ? ? ? ? appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 541 of 638 rej09b0395-0400 p9ddr?port 9 data direction register h ' ee008 port 9 bit initial value read/write 7 1 6 0 w 5 p9 5 ddr 0 w 4 p9 4 ddr 0 w 3 p9 3 ddr 0 w 2 p9 2 ddr 0 w 1 p9 1 ddr 0 w 0 p9 0 ddr port 9 input/output select 0 1 generic input generic output 1 ? ? ? ? paddr?port a data direction register h ' ee009 port a bit initial value read/write 7 pa 7 ddr 6 pa 6 ddr 5 pa 5 ddr 4 pa 4 ddr 0 w 3 pa 3 ddr 0 w 2 pa 2 ddr 0 w 1 pa 1 ddr 0 w 0 pa 0 ddr initial value read/write 10 w 0 w 0 w 0 w modes 3 and 4 modes 1 and 2 0 w 0 w port a input/output select 0 1 generic input generic output 0 w 0 w 0 w 0 w 0 w ? pbddr?port b data direction register h ' ee00a port b bit initial value read/write 7 pb 7 ddr 0 w 6 pb 6 ddr 0 w 5 pb 5 ddr 0 w 4 pb 4 ddr 0 w 3 pb 3 ddr 0 w 2 pb 2 ddr 0 w 1 pb 1 ddr 0 w 0 pb 0 ddr port b input/output select 0 1 generic input generic output 0 w appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 542 of 638 rej09b0395-0400 mdcr?mode control register h ' ee011 system control bit initial value read/write 1 ? 7 ? 1 ? 6 ? 0 ? 5 ? 0 ? 4 ? 0 ? 3 ? ? r 2 mds2 ? r 1 mds1 ? r 0 mds0 mode select 2 to 0 0 1 0 1 operatin g mode *** bit 2 md 2 bit 1 md 1 bit 0 md 0 0 1 0 1 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 0 1 0 1 0 1 note: * determined by the state of the mode pins (md 2 to md 0 ). ? appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 543 of 638 rej09b0395-0400 syscr?system control register h ' ee012 system control bit initial value read/write 0 r/w 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 1 r/w 3 ue 0 r/w 2 nmieg 0 r/w 1 ssoe 1 r/w 0 rame nmi ed g e select 0 1 an interrupt is requested at the fallin g ed g e of nmi an interrupt is requested at the risin g ed g e of nmi ram enable 0 1 on-chip ram is disabled on-chip ram is enabled user bit enable 0 1 ccr bit 6 (ui) is used as an interrupt mask bit ccr bit 6 (ui) is used as a user bit standby timer select 2 to 0 bit 6 sts2 waitin g time = 8,192 states waitin g time = 16,384 states waitin g time = 32,768 states waitin g time = 65,536 states waitin g time = 131,072 states waitin g time = 26,2144 states waitin g time = 1,024 states ille g al settin g bit 5 sts1 bit 4 sts0 standby timer 0 1 0 1 0 1 0 1 0 1 0 1 0 1 software standby 0 1 sleep instruction causes transition to sleep mode sleep instruction causes transition to software standby mode software standby output port enable 0 1 in software standby mode, all address bus and bus control si g nals are hi g h- impedance in software standby mode, address bus retains output state and bus control si g nals are fixed hi g h appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 544 of 638 rej09b0395-0400 brcr?bus release control register h ' ee013 bus controller bit 7 a23e 6 a22e 5 a21e 4 a20e 3 ? 2 ? 1 ? 0 brle initial value read/write 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 0 r/w modes 1 and 2 address 23 to 20 enable 0 1 address output other input/output bus release enable 0 1 the bus cannot be released to an external device the bus can be released to an external device initial value read/write 1 r/w 1 r/w 1 r/w 0 ? 1 ? 1 ? 1 ? 0 r/w modes 3 and 4 iscr?irq sense control register h ' ee014 interrupt controller bit initial value read/write 0 r/w 7 ? 0 r/w 6 ? 0 r/w 5 irq5sc 0 r/w 4 irq4sc 0 r/w 3 irq3sc 0 r/w 2 irq2sc 0 r/w 1 irq1sc 0 r/w 0 irq0sc irq 5 to irq 0 sense control 0 1 interrupts are requested when irq 5 to irq 0 are low interrupts are requested by fallin g -ed g e input at irq 5 to irq 0 appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 545 of 638 rej09b0395-0400 ier?irq enable register h ' ee015 interrupt controller bit initial value read/write 0 r/w 7 ? 0 r/w 6 ? 0 r/w 5 irq5e 0 r/w 4 irq4e 0 r/w 3 irq3e 0 r/w 2 irq2e 0 r/w 1 irq1e 0 r/w 0 irq0e irq 5 to irq 0 enable 0 1 irq 5 to irq 0 interrupts are disabled irq 5 to irq 0 interrupts are enabled isr?irq status register h ' ee016 interrupt controller bit initial value read/write 0 ? 7 ? 0 ? 6 ? 0 r/(w) * 5 irq5f 0 r/(w) * 4 irq4f 0 r/(w) * 3 irq3f 0 r/(w) * 2 irq2f 0 r/(w) * 1 irq1f 0 r/(w) * 0 irq0f irq5 to irq0 fla g s 0 note: * only 0 can be written to clear the fla g . bits 5 to 0 irq5f to irq0f settin g and clearin g conditions 1 note: n = 5 to 0 [clearin g conditions] ? read irqnf when irqnf = 1, then write 0 in irqnf. ? irqnsc = 0, irqn input is hi g h, and interrupt exception handlin g is bein g carried out. ? irqnsc = 1 and irqn interrupt exception handlin g is bein g carried out. [settin g conditions] ? irqnsc = 0 and irqn input is low. ? irqnsc = 1 and irqn input chan g es from hi g h to low. appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 546 of 638 rej09b0395-0400 ipra?interrupt priority register a h ' ee018 interrupt controller bit initial value read/write 0 r/w 7 ipra7 0 r/w 6 ipra6 0 r/w 5 ipra5 0 r/w 4 ipra4 0 r/w 3 ipra3 0 r/w 2 ipra2 0 r/w 1 ipra1 0 r/w 0 ipra0 priority level a7 to a0 0 1 priority level 0 (low priority) priority level 1 (hi g h priority) ? interrupt sources controlled by each bit ipra bit interrupt source bit 7 ipra7 irq 0 bit 6 ipra6 irq 1 bit 5 ipra5 irq 2 , irq 3 bit 4 ipra4 irq 4 , irq 5 bit 3 ipra3 bit 2 ipra2 bit 1 ipra1 bit 0 ipra0 wdt, a/d con- verter 16-bit timer channel 0 16-bit timer channel 1 16-bit timer channel 2 iprb?interrupt priority register b h ' ee019 interrupt controller bit initial value read/write 0 r/w 7 iprb7 0 r/w 6 iprb6 0 r/w 5 ? 0 r/w 4 ? 0 r/w 3 iprb3 0 r/w 2 iprb2 0 r/w 1 ? 0 r/w 0 ? priority level b7, b6, b3, and b2 0 1 priority level 0 (low priority) priority level 1 (hi g h priority) bit 7 iprb7 bit 6 iprb6 bit 5 ? ? bit 4 ? ? bit 3 iprb3 bit 2 iprb2 bit 1 ? ? bit 0 ? ? 8-bit timer channels 0 and 1 8-bit timer channels 2 and 3 sci channel 0 sci channel 1 ? interrupt sources controlled by each bit iprb bit interrupt source appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 547 of 638 rej09b0395-0400 dastcr?d/a standby control register h ' ee01a d/a bit initial value read/write 1 7 1 6 1 5 1 4 1 3 1 2 1 1 0 r/w 0 daste d/a standby enable 0 1 d/a output is disabled in software standby mode d/a output is enabled in software standby mode (initial value) ? ? ? ? ? ? ? ? ? ? ? ? ? ? divcr?division control register h ' ee01b system control bit initial value read/write 1 7 1 6 1 5 1 4 1 3 1 2 0 r/w 1 div1 0 r/w 0 div0 division ratio bits 1 and 0 frequency division ratio bit 1 div1 bit 0 div0 1/1 1/2 1/4 1/8 0 1 0 1 0 1 (initial value) ? ? ? ? ? ? ? ? ? ? ? ? appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 548 of 638 rej09b0395-0400 mstcrh?module standby control register h h ' ee01c system control 765 43210 pstop mstph1 mstph0 r/w r/w r/w r/w 011 11000 module standby h1 to h0 selection bits for placin g modules in standby state. bit initial value read/write reserved bits clock stop enables or disables clock output. ? ? ? ? ? ? ? ? ? mstcrl?module standby control register l h ' ee01d system control 765 43210 mstpl2 mstpl3 mstpl4 mstpl0 r/w r/w r/w r/w r/w r/w r/w r/w 000 00000 module standby l4 to l2, l0 selection bits for placin g modules in standby state. reserved bits bit initial value read/write ?? ? ? appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 549 of 638 rej09b0395-0400 adrcr?address control register h ' ee01e bus controller 7 ? 1 ? bit initial value read/write 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 0 adrctl 1 r/w 2 ? 1 ? 1 ? 1 ? reserved bits address control selects address update mode 1 or address update mode 2. description adrctl address update mode 2 is selected address update mode 1 is selected (initial value) 0 1 cscr?chip select control register h ' ee01f bus controller bit initial value read/write 0 r/w 7 cs7e note: n = 7 to 4 0 r/w 6 cs6e 0 r/w 5 cs5e 0 r/w 4 cs4e 1 3 1 2 1 1 1 0 chip select 7 to 4 enable description bit n csne output of chip select si g nal csn is disabled (initial value) output of chip select si g nal csn is enabled 0 1 ? ? ? ? ? ? ? ? appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 550 of 638 rej09b0395-0400 abwcr?bus width control register h ' ee020 bus controller bit initial value initial value read/write 1 0 r/w 7 abw7 1 0 r/w 6 abw6 1 0 r/w 5 abw5 1 0 r/w 4 abw4 1 0 r/w 3 abw3 1 0 r/w 2 abw2 1 0 r/w 1 abw1 1 0 r/w 0 abw0 area 7 to 0 bus width control bus width of access area bits 7 to 0 abw7 to abw0 areas 7 to 0 are 16-bit access areas areas 7 to 0 are 8-bit access areas 0 1 modes 1 and 3 modes 2 and 4 astcr?access state control register h ' ee021 bus controller bit initial value read/write 1 r/w 7 ast7 1 r/w 6 ast6 1 r/w 5 ast5 1 r/w 4 ast4 1 r/w 3 ast3 1 r/w 2 ast2 1 r/w 1 ast1 1 r/w 0 ast0 area 7 to 0 access state control number of states in access area bits 7 to 0 ast7 to ast0 areas 7 to 0 are two-state access areas areas 7 to 0 are three-state access areas 0 1 appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 551 of 638 rej09b0395-0400 wcrh?wait control register h h ' ee022 bus controller 1 r/w 7 w71 1 r/w 6 w70 1 r/w 5 w61 1 r/w 4 w60 1 r/w 3 w51 1 r/w 2 w50 1 r/w 1 w41 1 r/w 0 w40 0 area 4 wait control 1 and 0 0 1 0 1 no pro g ram wait is inserted 1 pro g ram wait state is inserted 2 pro g ram wait states are inserted 3 pro g ram wait states are inserted 1 0 area 5 wait control 1 and 0 0 1 0 1 no pro g ram wait is inserted 1 pro g ram wait state is inserted 2 pro g ram wait states are inserted 3 pro g ram wait states are inserted 1 0 area 6 wait control 1 and 0 0 1 0 1 no pro g ram wait is inserted 1 pro g ram wait state is inserted 2 pro g ram wait states are inserted 3 pro g ram wait states are inserted 1 0 area 7 wait control 1 and 0 0 1 0 1 no pro g ram wait is inserted 1 pro g ram wait state is inserted 2 pro g ram wait states are inserted 3 pro g ram wait states are inserted 1 bit initial value read/write appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 552 of 638 rej09b0395-0400 wcrl?wait control register l h ' ee023 bus controller bit initial value read/write 1 r/w 7 w31 1 r/w 6 w30 1 r/w 5 w21 1 r/w 4 w20 1 r/w 3 w11 1 r/w 2 w10 1 r/w 1 w01 1 r/w 0 w00 area 0 wait control 1 and 0 0 0 1 0 1 no pro g ram wait is inserted 1 pro g ram wait state is inserted 2 pro g ram wait states are inserted 3 pro g ram wait states are inserted 1 area 1 wait control 1 and 0 0 0 1 0 1 no pro g ram wait is inserted 1 pro g ram wait state is inserted 2 pro g ram wait states are inserted 3 pro g ram wait states are inserted 1 area 2 wait control 1 and 0 0 0 1 0 1 no pro g ram wait is inserted 1 pro g ram wait state is inserted 2 pro g ram wait states are inserted 3 pro g ram wait states are inserted 1 area 3 wait control 1 and 0 0 0 1 0 1 no pro g ram wait is inserted 1 pro g ram wait state is inserted 2 pro g ram wait states are inserted 3 pro g ram wait states are inserted 1 appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 553 of 638 rej09b0395-0400 bcr?bus control register h ' ee024 bus controller bit initial value read/write 1 r/w 7 icis1 1 r/w 6 icis0 0 * 1 ? 5 ? 0 * 1 ? 4 ? 0 * 1 ? 3 ? 1 * 2 ? 2 ? 1 r/w 1 rdea 0 r/w 0 waite 0 1 wait pin wait input is disabled wait pin wait input is enabled idle cycle insertion 0 0 1 no idle cycle is inserted in case of consecutive external read and write cycles idle cycle is inserted in case of consecutive external read and write cycles idle cycle insertion 1 notes: 1. these bits can be read and written, but must not be set to 1. normal operation cannot be g uaranteed if 1 is written in these bits. 2. 0 must not be written in bit 2. 0 1 no idle cycle is inserted in case of consecutive external read cycles for different areas idle cycle is inserted in case of consecutive external read cycles for different areas area division unit select 0 1 area divisions are as follows: areas 0 to 7 are the same size (2 mbytes) wait pin enable area 0: 2 mbytes area 4: 1.93 mbytes area 1: 2 mbytes area 5: 4 kbytes area 2: 8 mbytes area 6: 23.75 kbytes area 3: 2 mbytes area 7: 22 bytes appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 554 of 638 rej09b0395-0400 p4pcr?port 4 input pull-up mos control register h ' ee03e port 4 bit initial value read/write 0 r/w 7 p4 7 pcr 0 r/w 6 p4 6 pcr 0 r/w 5 p4 5 pcr 0 r/w 4 p4 4 pcr 0 r/w 3 p4 3 pcr 0 r/w 2 p4 2 pcr 0 r/w 1 p4 1 pcr 0 r/w 0 p4 0 pcr port 4 input pull-up mos control 7 to 0 0 1 input pull-up transistor is off input pull-up transistor is on note: valid when the correspondin g p4ddr bit is cleared to 0 (desi g natin g g eneric input). appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 555 of 638 rej09b0395-0400 tstr?timer start register h ' fff60 16-bit timer (all channels) 7 ? 1 ? bit initial value read/write 6 ? 1 ? 5 ? 1 ? reserved bits 4 ? 1 ? 3 ? 1 ? 2 str2 0 r/w 1 str1 0 r/w 0 str0 0 r/w 0 1 16tcnt0 is halted (initial value) 16tcnt0 is countin g counter start 0 0 1 16tcnt1 is halted (initial value) 16tcnt1 is countin g counter start 1 0 1 16tcnt2 is halted (initial value) 16tcnt2 is countin g counter start 2 appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 556 of 638 rej09b0395-0400 tsnc?timer synchro register h ' fff61 16-bit timer (all channels) 7 ? 1 ? bit initial value read/write 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 2 sync2 0 r/w 1 sync1 0 r/w 0 sync0 0 r/w 0 1 channel 0 timer counter (16tcnt0) operates independently (16tcnt0 presettin g /clearin g is independent of other channels) (initial value) channel 0 operates synchronously synchronous presettin g /synchronous clearin g of 16tcnt0 is possible timer sync 0 0 1 channel 1 timer counter (16tcnt1) operates independently (16tcnt1 presettin g /clearin g is independent of other channels) (initial value) channel 1 operates synchronously synchronous presettin g /synchronous clearin g of 16tcnt1 is possible timer sync 1 0 1 channel 2 timer counter (16tcnt2) operates independently (16tcnt2 presettin g /clearin g is independent of other channels) (initial value) channel 2 operates synchronously synchronous presettin g /synchronous clearin g of 16tcnt2 is possible timer sync 2 reserved bits appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 557 of 638 rej09b0395-0400 tmdr?timer mode register h ' fff62 16-bit timer (all channels) 7 ? 1 ? bit initial value read/write 6 mdf 0 r/w 5 fdir 0 r/w 4 ? 1 ? 3 ? 1 ? 2 pwm2 0 r/w 1 pwm1 0 r/w 0 pwm0 0 r/w 0 1 channel 0 operates normally (initial value) channel 0 operates in pwm mode pwm mode 0 0 1 channel 1 operates normally (initial value) channel 1 operates in pwm mode pwm mode 1 0 1 channel 2 operates normally (initial value) channel 2 operates in pwm mode pwm mode 2 0 1 ovf is set to 1 in tisrc when 16tcnt2 overflows or underflows (initial value) ovf is set to 1 in tisrc when 16tcnt2 overflows fla g direction 0 1 channel 2 operates normally (initial value) channel 2 operates in phase countin g mode phase countin g mode appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 558 of 638 rej09b0395-0400 tolr?timer output level setting register h ' fff63 16-bit timer (all channels) 7 ? 1 ? bit initial value read/write 6 ? 1 ? 5 tob2 0 w 4 toa2 0 w 3 tob1 0 w 2 toa1 0 w 1 tob0 0 w 0 toa0 0 w 0 1 tioca 0 is 0 tioca 0 is 1 output level settin g a0 0 1 tiocb 0 is 0 tiocb 0 is 1 output level settin g b0 0 1 tioca 1 is 0 tioca 1 is 1 output level settin g a1 0 1 tiocb 1 is 0 tiocb 1 is 1 output level settin g b1 0 1 tioca 2 is 0 tioca 2 is 1 output level settin g a2 0 1 tiocb 2 is 0 (initial value) (initial value) (initial value) (initial value) (initial value) (initial value) tiocb 2 is 1 output level settin g b2 appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 559 of 638 rej09b0395-0400 tisra?timer interrupt status register a h ' fff64 16-bit timer (all channels) ? 1 ? 7 imiea2 0 r/w 6 imiea1 0 r/w 5 imiea0 0 r/w 4 ? 1 ? 3 imfa2 0 r/(w) * 2 imfa1 0 r/(w) * 1 imfa0 0 r/(w) * 0 0 1 input capture/compare match fla g a0 [clearin g conditions] read imfa0 when imfa0 = 1, then write 0 in imfa0 [settin g conditions] ? 16tcnt0 = gra0 when gra0 functions as an output compare re g ister. ? 16tcnt0 value is transferred to gra0 by an input capture si g nal when gra0 functions as an input capture re g ister. 0 1 input capture/compare match fla g a1 [clearin g conditions] read imfa1 when imfa1 = 1, then write 0 in imfa1 [settin g conditions] ? 16tcnt1 = gra1 when gra1 functions as an output compare re g ister. ? 16tcnt1 value is transferred to gra1 by an input capture si g nal when gra1 functions as an input capture re g ister. 0 1 input capture/compare match fla g a2 [clearin g conditions] read imfa2 when imfa 2 = 1, then write 0 in imfa2 (initial value) (initial value) (initial value) [settin g conditions] ? 16tcnt2 = gra2 when gra2 functions as an output compare re g ister. ? 16tcnt2 value is transferred to gra2 by an input capture si g nal when gra2 functions as an input capture re g ister. 0 1 imia0 interrupt requested by imfa0 fla g is disabled imia0 interrupt requested by imfa0 is enabled input capture/compare match interrupt enable a0 0 1 imia1 interrupt requested by imfa1 fla g is disabled imia1 interrupt requested by imfa1 is enabled input capture/compare match interrupt enable a1 0 1 imia2 interrupt requested by imfa2 fla g is disabled (initial value) (initial value) (initial value) imia2 interrupt requested by imfa2 is enabled input capture/compare match interrupt enable a2 bit: initial value: read/write: note: * only 0 can be written to clear the fla g . appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 560 of 638 rej09b0395-0400 tisrb?timer interrupt status register b h ' fff65 16-bit timer (all channels) ? 1 ? 7 imieb2 0 r/w 6 imieb1 0 r/w 5 imieb0 0 r/w 4 ? 1 ? 3 imfb2 0 r/(w) * 2 imfb1 0 r/(w) * 1 imfb0 0 r/(w) * 0 0 1 input capture/compare match fla g b0 [clearin g condition] read imfb0 when imfb0 = 1, then write 0 in imfb0. [settin g conditions] 16tcnt0 = grb0 when grb0 functions as an output compare re g ister. 16tcnt0 value is transferred to grb0 by an input capture si g nal when grb0 functions as an input capture re g ister. 0 1 input capture/compare match fla g b1 [clearin g condition] read imfb1 when imfb1 = 1, then write 0 in imfb1. [settin g conditions] ? 16tcnt1 = grb1 when grb1 functions as an output compare re g ister. ? 16tcnt1 value is transferred to grb1 by an input capture si g nal when grb1 functions as an input capture re g ister. 0 1 input capture/compare match fla g b2 [clearin g condition] read imfb2 when imfb2 = 1, then write 0 in imfb2. (initial value) (initial value) (initial value) [settin g conditions] ? 16tcnt2 = grb2 when grb2 functions as an output compare re g ister. ? 16tcnt2 value is transferred to grb2 by an input capture si g nal when grb2 functions as an input capture re g ister. 0 1 imib0 interrupt requested by imfb0 fla g is disabled imib0 interrupt requested by imfb0 is enabled input capture/compare match interrupt enable b0 0 1 imib1 interrupt requested by imfb1 fla g is disabled imib1 interrupt requested by imfb1 is enabled input capture/compare match interrupt enable b1 0 1 imib2 interrupt requested by imfb2 fla g is disabled (initial value) (initial value) (initial value) imib2 interrupt requested by imfb2 is enabled input capture/compare match interrupt enable b2 note: * only 0 can be written to clear the fla g . bit: initial value: read/write: appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 561 of 638 rej09b0395-0400 tisrc?timer interrupt status register c h ' fff66 16-bit timer (all channels) ? 1 ? 7 ovie2 0 r/w 6 ovie1 0 r/w 5 ovie0 0 r/w 4 ? 1 ? 3 ovf2 0 r/(w) * 2 ovf1 0 r/(w) * 1 ovf0 0 r/(w) * 0 0 1 ovi0 interrupt requested by ovf0 fla g is disabled ovi0 interrupt requested by ovf0 fla g is enabled overflow interrupt enable 0 0 1 ovi1 interrupt requested by ovf1 fla g is disabled ovi1 interrupt requested by ovf1 fla g is enabled overflow interrupt enable 1 0 1 ovi2 interrupt requested by ovf2 fla g is disabled (initial value) (initial value) (initial value) ovi2 interrupt requested by ovf2 fla g is enabled overflow interrupt enable 2 bit: initial value: read/write: [clearin g condition] read ovf0 when ovf0 = 1, then write 0 in ovf0. [settin g condition] 16tcnt0 overflowed from h'ffff to h'0000. overflow fla g 0 0 1 [clearin g condition] read ovf1 when ovf1 = 1, then write 0 in ovf1. [settin g condition] 16tcnt1 overflowed from h'ffff to h'0000. overflow fla g 1 0 1 [clearin g condition] read ovf2 when ovf2 = 1, then write 0 in ovf2. (initial value) (initial value) (initial value) [settin g condition] 16tcnt2 overflowed from h'ffff to h'0000, or underflowed from h'0000 to h'ffff. overflow fla g 2 0 1 note: * only 0 can be written to clear the fla g . appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 562 of 638 rej09b0395-0400 16tcr0?timer control register 0 h ' fff68 16-bit timer channel 0 bit initial value read/write 1 ? 7 ? 0 r/w 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w 0 tpsc0 timer prescaler 2 to 0 description bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 internal clock : internal clock : / 2 internal clock : / 4 internal clock : / 8 external clock a : tclka input external clock b : tclkb input external clock c : tclkc input external clock d : tclkd input 0 1 0 1 0 1 0 1 0 1 0 1 0 1 clock ed g e 1 and 0 description bit 4 ckeg bit 3 ckeg0 risin g ed g es counted fallin g ed g es counted both ed g es counted 0 1 ? 0 0 1 counter clear 1 and 0 description bit 6 cclr1 bit 5 cclr0 16tcnt is not cleared 16tcnt is cleared by gra compare match or input capture 16tcnt is cleared by grb compare match or input capture synchronous clear : 16tcnt is cleared in synchronization with other synchronized timers 0 1 0 1 0 1 (initial value) (initial value) (initial value) appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 563 of 638 rej09b0395-0400 tior0?timer i/o control register 0 h ' fff69 16-bit timer channel 0 i / o control a2 to a0 description bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 no output at compare match (initial value) 0 output at gra compare match 1 output at gra compare match output to gg les at gra compare match (1 output on channel 2) gra captures risin g ed g es of input gra captures fallin g ed g es of input grb captures both ed g es of input gra is an output compare re g ister gra is an input capture re g ister i / o control b2 to b0 description bit 6 iob2 bit 5 iob1 bit 4 iob0 no output at compare match (initial value) 0 output at grb compare match 1 output at grb compare match output to gg les at grb compare match (1 output on channel 2) grb captures risin g ed g es of input grb captures fallin g ed g es of input grb captures both ed g es of input grb is an output compare re g ister grb is an input capture re g ister ? 1 ? 7 iob2 0 r/w 6 iob1 0 r/w 5 iob0 0 r/w 4 ? 1 ? 3 ioa2 0 r/w 2 ioa1 0 r/w 1 ioa0 0 r/w 0 bit: initial value: read/write: 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 564 of 638 rej09b0395-0400 16tcnt0 h/l?timer counter 0 h/l h ' fff6a, h ' fff6b 16-bit timer channel 0 bit initial value read/write 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w up-counter gra0 h/l?general register a0 h/l h ' fff6c, h ' fff6d 16-bit timer channel 0 bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w output compare or input capture re g ister grb0 h/l?general register b0 h/l h ' fff6e, h ' fff6f 16-bit timer channel 0 bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w output compare or input capture re g ister appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 565 of 638 rej09b0395-0400 16tcr1 timer control register 1 h ' fff70 16-bit timer channel 1 7 ? 1 ? bit initial value read/write 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w 0 tpsc0 0 r/w note: bit functions are the same as for 16-bit timer channel 0. tior1?timer i/o control register 1 h ' fff71 16-bit timer channel 1 7 ? 1 ? bit initial value read/write 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ? 1 ? 2 ioa2 0 r/w 1 ioa1 0 r/w 0 ioa0 0 r/w note: bit functions are the same as for 16-bit timer channel 0. 16tcnt1 h/l?timer counter 1 h/l h ' fff72, h ' fff73 16-bit timer channel 1 bit initial value read/write 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w note: bit functions are the same as for 16-bit timer channel 0. appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 566 of 638 rej09b0395-0400 gra1 h/l?general register a1 h/l h ' fff74, h ' fff75 16-bit timer channel 1 bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w note: bit functions are the same as for 16-bit timer channel 0. grb1 h/l?general register b1 h/l h ' fff76, h ' fff77 16-bit timer channel 1 bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w note: bit functions are the same as for 16-bit timer channel 0. 16tcr2?timer control register 2 h ' fff78 16-bit timer channel 2 7 ? 1 ? bit initial value read/write 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w 0 tpsc0 0 r/w notes: 1. bit functions are the same as for 16-bit timer channel 0. 2. when phase countin g mode is selected in channel 2, the settin g s of bits ckeg1 and ckeg0 and tpsc2 to tpsc0 in 16tcr2 are i g nored. appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 567 of 638 rej09b0395-0400 tior2?timer i/o control register 2 h ' fff79 16-bit timer channel 2 7 ? 1 ? bit initial value read/write 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ? 1 ? 2 ioa2 0 r/w 1 ioa1 0 r/w 0 ioa0 0 r/w note: bit functions are the same as for 16-bit timer channel 0. 16tcnt2 h/l?timer counter 2 h/l h ' fff7a, h ' fff7b 16-bit timer channel 2 bit initial value read/write 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w phase countin g mode : other mode : up/down-counter up-counter gra2 h/l?general register a2 h/l h ' fff7c, h ' fff7d 16-bit timer channel 2 bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w note: bit functions are the same as for 16-bit timer channel 0. grb2 h/l?general register b2 h/l h ' fff7e, h ' fff7f 16-bit timer channel 2 bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w note: bit functions are the same as for 16-bit timer channel 0. appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 568 of 638 rej09b0395-0400 8tcr0?timer control register 0 h ' fff80 8-bit timer channel 0 8tcr1?timer control register 1 h ' fff81 8-bit timer channel 1 bit initial value read/write 0 r/w 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w 0 cks0 clock select 2 to 0 0 0 0 1 0 1 0 0 1 1 0 1 1 clock input is disabled internal clock: counted on risin g ed g e of /8 internal clock: counted on risin g ed g e of /64 internal clock: counted on risin g ed g e of /8192 external clock : counted on fallin g ed g e external clock : counted on risin g ed g e external clock: counted on both risin g and fallin g ed g es counter clear 1 and 0 0 0 1 0 1 clearin g is disabled cleared by compare match a cleared by compare match b/input capture b cleared by input capture b 1 timer overflow interrupt enable 0 1 ovi interrupt requested by ovf is disabled ovi interrupt requested by ovf is enabled compare match interrupt enable a 0 1 cmia interrupt requested by cmfa is disabled cmia interrupt requested by cmfa is enabled compare match interrupt enable b 0 1 cmib interrupt requested by cmfb is disabled cmib interrupt requested by cmfb is enabled 1 channel 0: count on 8tcnt1 overflow si g nal * channel 1: count on 8tcnt0 compare match a * note: * if the clock input of channel 0 is the 8tcnt1 overflow si g nal and that of channel 1 is the 8tcnt0 compare match si g nal, no incrementin g clock is g enerated. do not use this settin g . appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 569 of 638 rej09b0395-0400 8tcsr0?timer control/status register 0 h ' fff82 8-bit timer channel 0 output select a1 and a0 0 description description description bit 1 os1 bit 0 os0 ice in 8tcsr1 bit 3 ois3 bit 4 adte trge * 2 bit 2 ois2 1 0 1 no chan g e at compare match a 0 output at compare match a 1 output at compare match a output to gg les at compare match a output/input capture ed g e select b3 and b2 0 0 1 0 1 0 1 0 1 0 1 0 1 no chan g e at compare match b 0 output at compare match b 1 output at compare match b output to gg les at compare match b tcorb input capture on risin g ed g e tcorb input capture on fallin g ed g e tcorb input capture on both risin g and fallin g ed g es 1 a/d tri gg er enable 0 0 1 0 1 a/d converter start requests by compare match a or an external tri gg er are disabled a/d converter start requests by compare match a or an external tri gg er are disabled a/d converter start requests by an external tri gg er are enabled, and a/d converter start requests by compare match a are disabled a/d converter start requests by compare match a are enabled, and a/d converter start requests by an external tri gg er are disabled timer overflow fla g 0 [clearin g condition] read ovf when ovf = 1, then write 0 in ovf. bit initial value read/write 0 r/(w) * 1 7 cmfb 0 r/(w) * 1 6 cmfa 0 r/(w) * 1 5 ovf 0 r/w 4 adte 0 r/w 3 ois3 0 r/w 2 ois2 0 r/w 1 os1 0 r/w 0 os0 0 1 1 [settin g condition] 8tcnt overflows from h'ff to h'00. compare match fla g a 0 [clearin g condition] read cmfa when cmfa = 1, then write 0 in cmfa. 1 [settin g condition] 8tcnt = tcora compare match/input capture fla g b 0 [clearin g condition] read cmfb when cmfb = 1, then write 0 in cmfb. 1 [settin g conditions] ? 8tcnt = tcorb ? the 8tcnt value is transferred to tcorb by an input capture si g nal when tcorb functions as an input capture re g ister. note: 1. only 0 can be written to bits 7 to 5 to clear these fla g s. note: 2. trge is bit 7 of the a/d control re g ister (adcr). 1 appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 570 of 638 rej09b0395-0400 8tcsr1?timer control/status register 1 h ' fff83 8-bit timer channel 1 output select a1 and a0 0 description description bit 1 os1 bit 0 os0 ice in 8tcsr1 bit 3 ois3 bit 2 ois2 1 0 1 no chan g e at compare match a 0 output at compare match a 1 output at compare match a output to gg les at compare match a output/input capture ed g e select b3 and b2 0 0 1 0 1 0 1 0 1 0 1 0 1 no chan g e at compare match b 0 output at compare match b 1 output at compare match b output to gg les at compare match b tcorb input capture on risin g ed g e tcorb input capture on fallin g ed g e tcorb input capture on both risin g and fallin g ed g es 1 timer overflow fla g 0 [clearin g condition] read ovf when ovf = 1, then write 0 in ovf. 0 1 1 [settin g condition] 8tcnt overflows from h'ff to h'00. compare match fla g a 0 [clearin g condition] read cmfa when cmfa = 1, then write 0 in cmfa. 1 [settin g condition] 8tcnt = tcora compare match/input capture fla g b 0 [clearin g condition] read cmfb when cmfb = 1, then write 0 in cmfb. 1 [settin g conditions] ? 8tcnt = tcorb ? the 8tcnt value is transferred to tcorb by an input capture si g nal when tcorb functions as an input capture re g ister. note: * only 0 can be written to bits 7 to 5 to clear these fla g s. bit initial value read/write 0 r/(w) * 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/w 4 ice 0 r/w 3 ois3 0 r/w 2 ois2 0 r/w 1 os1 0 r/w 0 os0 input capture enable 0 1 tcorb is a compare match re g ister tcorb is an input capture re g ister appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 571 of 638 rej09b0395-0400 tcora0?time constant register a0 h ' fff84 8-bit timer channel 0 tcora1?time constant register a1 h ' fff85 8-bit timer channel 1 bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w tcora0 tcora1 tcorb0?time constant register b0 h ' fff86 8-bit timer channel 0 tcorb1?time constant register b1 h ' fff87 8-bit timer channel 1 bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w tcorb0 tcorb1 8tcnt0?timer counter 0 h ' fff88 8-bit timer channel 0 8tcnt1?timer counter 1 h ' fff89 8-bit timer channel 1 bit initial value read/write 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 8tcnt0 8tcnt1 appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 572 of 638 rej09b0395-0400 tcsr?timer control/status register h ' fff8c wdt bit initial value read/write 0 r/(w) * 7 ovf 0 r/w 6 wt/ it 0 r/w 5 tme 4 ? 1 ? 1 ? 3 ? 0 r/w 2 cks2 0 r/w 1 cks1 clock select 2 to 0 0 0 /2 /32 /64 /128 /256 /512 /2048 /4096 1 0 cks0 0 r/w 0 1 0 1 0 1 0 1 1 0 1 timer enable 0 timer disabled: tcnt is initialized to h'00 and halted 1 timer enabled: tcnt starts countin g up timer mode select 0 interval timer: requests interval timer interrupts 1 watchdo g timer: g enerates a reset si g nal overflow fla g 0 [clearin g condition] read ovf when ovf = 1, then write 0 in ovf 1 [settin g condition] tcnt chan g es from h'ff to h'00 note: * only 0 can be written to clear the fla g . cks2 cks1 cks0 description appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 573 of 638 rej09b0395-0400 tcnt?timer counter h ' fff8d (read), h ' fff8c (write) wdt bit initial value read/write 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 count value rstcsr?reset control/status register h ' fff8f (read), h ' fff8e (write) wdt bit initial value read/write 0 r/(w) * 7 wrst 0 r/w 6 rstoe 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 2 ? 1 ? 1 ? 1 ? 0 ? reset output enable 0 external output of reset si g nal is disabled external output of reset si g nal is enabled 1 watchdo g timer reset 0 [clearin g conditions] ? reset si g nal at res pin ? read wrst when wrst = 1, then write 0 in wrst 1 [settin g condition] tcnt overflow g enerates a reset si g nal durin g watchdo g timer operation note: * only 0 can be written in bit 7 to clear the fla g . appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 574 of 638 rej09b0395-0400 8tcr2?timer control register 2 h ' fff90 8-bit timer channel 2 8tcr3?timer control register 3 h ' fff91 8-bit timer channel 3 bit initial value read/write 0 r/w 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w 0 cks0 clock select 2 to 0 0 0 0 1 0 1 0 0 1 1 0 1 1 clock input is disabled internal clock: counted on risin g ed g e of /8 internal clock: counted on risin g ed g e of /64 internal clock: counted on risin g ed g e of /8192 external clock: counted on fallin g ed g e external clock: counted on risin g ed g e external clock: counted on both risin g and fallin g ed g es counter clear 1 and 0 0 0 1 0 1 clearin g is disabled cleared by compare match a cleared by compare match b/input capture b cleared by input capture b 1 timer overflow interrupt enable 0 1 ovi interrupt requested by ovf is disabled ovi interrupt requested by ovf is enabled compare match interrupt enable a 0 1 cmia interrupt requested by cmfa is disabled cmia interrupt requested by cmfa is enabled compare match interrupt enable b 0 1 cmib interrupt requested by cmfb is disabled cmib interrupt requested by cmfb is enabled 1 csk2 csk1 csk0 description channel 2: count on 8tcnt3 overflow si g nal * channel 3: count on 8tcnt2 compare match a * note: * if the clock input of channel 2 is the 8tcnt3 overflow si g nal and that of channel 3 is the 8tcnt2 compare match si g nal, no incrementin g clock is g enerated. do not use this settin g . appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 575 of 638 rej09b0395-0400 8tcsr2?timer control/status register 2 h ' fff92 8-bit timer channel 2 8tcsr3?timer control/status register 3 h ' fff93 8-bit timer channel 3 bit initial value read/write 0 r/(w) * 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/w 4 ice 0 r/w 3 ois3 0 r/w 2 ois2 0 r/w 1 os1 0 r/w 0 os0 timer overflow fla g 0 [clearin g condition] read ovf when ovf = 1, then write 0 in ovf. bit initial value read/write 0 r/(w) * 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 1 ? 4 ? 0 r/w 3 ois3 0 r/w 2 ois2 0 r/w 1 os1 0 r/w 0 os0 8tcsr3 8tcsr2 1 [settin g condition] 8tcnt overflows from h'ff to h'00. compare match fla g a 0 [clearin g condition] read cmfa when cmfa = 1, then write 0 in cmfa. 1 [settin g condition] 8tcnt = tcora compare match/input capture fla g b 0 [clearin g condition] read cmfb when cmfb = 1, then write 0 in cmfb. 1 [settin g conditions] ? 8tcnt = tcorb ? the 8tcnt value is transferred to tcorb by an input capture si g nal when tcorb functions as an input capture re g ister. note: * only 0 can be written to bits 7 to 5 to clear these fla g s. output select a1 and a0 0 description bit 1 os1 bit 0 os0 1 0 1 no chan g e at compare match a 0 output at compare match a 1 output at compare match a output to gg les at compare match a 0 1 description ice in 8tcsr3 bit 3 ois3 bit 2 ois2 output/input capture ed g e select b3 and b2 0 0 1 0 1 0 1 0 1 0 1 0 no chan g e at compare match b 0 output at compare match b 1 output at compare match b output to gg les at compare match b tcorb input capture on risin g ed g e tcorb input capture on fallin g ed g e tcorb input capture on both risin g and fallin g ed g es 1 input capture enable 0 1 tcorb is a compare match re g ister tcorb is an input capture re g ister appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 576 of 638 rej09b0395-0400 tcora2?time constant register a2 h ' fff94 8-bit timer channel 2 tcora3?time constant register a3 h ' fff95 8-bit timer channel 3 bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w tcora2 tcora3 tcorb2?time constant register b2 h ' fff96 8-bit timer channel 2 tcorb3?time constant register b3 h ' fff97 8-bit timer channel 3 bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w tcorb2 tcorb3 8tcnt2?timer counter 2 h ' fff98 8-bit timer channel 2 8tcnt3?timer counter 3 h ' fff99 8-bit timer channel 3 bit initial value read/write 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 8tcnt2 8tcnt3 dadr0?d/a data register 0 h ' fff9c d/a bit initial value read/write 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 d/a conversion data appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 577 of 638 rej09b0395-0400 dadr1?d/a data register 1 h ' fff9d d/a bit initial value read/write 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 d/a conversion data appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 578 of 638 rej09b0395-0400 dacr?d/a control register h ' fff9e d/a bit initial value read/write 0 r/w 7 daoe1 0 r/w 6 daoe0 0 r/w 5 dae 1 ? 4 ? 1 ? 3 ? 1 ? 2 ? 1 ? 1 ? 1 ? 0 ? d/a enable bit 7 daoe1 d/a conversion is disabled in channels 0 and 1 d/a conversion is enabled in channel 0 d/a conversion is disabled in channel 1 d/a conversion is disabled in channel 0 d/a conversion is enabled in channel 1 description d/a conversion is enabled in channels 0 and 1 d/a conversion is enabled in channels 0 and 1 d/a conversion is enabled in channels 0 and 1 bit 6 bit 5 daoe0 dae 0 0 0 1 1 1 0 1 1 0 0 1 0 1 0 1 d/a output enable 0 0 da 0 analo g output is disabled 1 channel-0 d/a conversion and da 0 analo g output are enabled d/a output enable 1 0 da 1 analo g output is disabled 1 channel-1 d/a conversion and da 1 analo g output are enabled ? ? appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 579 of 638 rej09b0395-0400 tpmr?tpc output mode register h ' fffa0 tpc bit initial value read/write 1 ? 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 0 r/w 3 g3nov 0 r/w 2 g2nov 0 r/w 1 g1nov 0 r/w 0 g0nov group 0 non-overlap 0 normal tpc output in g roup 0. output values chan g e at compare match a in the selected 16-bit timer channel 1 non-overlappin g tpc output in g roup 0, controlled by compare match a and b in the selected 16-bit timer channel group 1 non-overlap 0 normal tpc output in g roup 1. output values chan g e at compare match a in the selected 16-bit timer channel 1 non-overlappin g tpc output in g roup 1, controlled by compare match a and b in the selected 16-bit timer channel group 2 non-overlap 0 normal tpc output in g roup 2. output values chan g e at compare match a in the selected 16-bit timer channel 1 non-overlappin g tpc output in g roup 2, controlled by compare match a and b in the selected 16-bit timer channel group 3 non-overlap 0 normal tpc output in g roup 3. output values chan g e at compare match a in the selected 16-bit timer channel 1 non-overlappin g tpc output in g roup 3, controlled by compare match a and b in the selected 16-bit timer channel appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 580 of 638 rej09b0395-0400 tpcr?tpc output control register h ' fffa1 tpc group 0 compare match select 1 and 0 bit 1 g0cms1 16-bit timer channel selected as output tri gg er bit 0 g0cms0 tpc output g roup 0 (tp 3 to tp 0 ) is tri gg ered by compare match in 16-bit timer channel 0 tpc output g roup 0 (tp 3 to tp 0 ) is tri gg ered by compare match in 16-bit timer channel 1 tpc output g roup 0 (tp 3 to tp 0 ) is tri gg ered by compare match in 16-bit timer channel 2 0 1 0 1 0 1 group 1 compare match select 1 and 0 bit 3 g1cms1 16-bit timer channel selected as output tri gg er bit 2 g1cms0 tpc output g roup 1 (tp 7 to tp 4 ) is tri gg ered by compare match in 16-bit timer channel 0 tpc output g roup 1 (tp 7 to tp 4 ) is tri gg ered by compare match in 16-bit timer channel 1 tpc output g roup 1 (tp 7 to tp 4 ) is tri gg ered by compare match in 16-bit timer channel 2 0 1 0 1 0 1 group 2 compare match select 1 and 0 bit 5 g2cms1 16-bit timer channel selected as output tri gg er bit 4 g2cms0 tpc output g roup 2 (tp 11 to tp 8 ) is tri gg ered by compare match in 16-bit timer channel 0 tpc output g roup 2 (tp 11 to tp 8 ) is tri gg ered by compare match in 16-bit timer channel 1 tpc output g roup 2 (tp 11 to tp 8 ) is tri gg ered by compare match in 16-bit timer channel 2 0 1 0 1 0 1 group 3 compare match select 1 and 0 bit 7 g3cms1 16-bit timer channel selected as output tri gg er bit 6 g3cms0 tpc output g roup 3 (tp 15 to tp 12 ) is tri gg ered by compare match in 16-bit timer channel 0 tpc output g roup 3 (tp 15 to tp 12 ) is tri gg ered by compare match in 16-bit timer channel 1 tpc output g roup 3 (tp 15 to tp 12 ) is tri gg ered by compare match in 16-bit timer channel 2 0 1 0 1 0 1 bit initial value read/write 7 g3cms1 6 g3cms0 5 g2cms1 4 g2cms0 1 r/w 3 g1cms1 1 r/w 2 g1cms0 1 r/w 1 g0cms1 1 r/w 0 g0cms0 1 r/w 1 r/w 1 r/w 1 r/w appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 581 of 638 rej09b0395-0400 nderb?next data enable register b h ' fffa2 tpc bit initial value read/write 0 r/w 7 nder15 0 r/w 6 nder14 0 r/w 5 nder13 0 r/w 4 nder12 0 r/w 3 nder11 0 r/w 2 nder10 0 r/w 1 nder9 0 r/w 0 nder8 next data enable 15 to 8 bits 7 to 0 nder15 to nder8 description tpc outputs tp 15 to tp 8 are disabled (ndr15 to ndr8 are not transferred to pb 7 to pb 0 ) tpc outputs tp 15 to tp 8 are enabled (ndr15 to ndr8 are transferred to pb 7 to pb 0 ) 0 1 ndera?next data enable register a h ' fffa3 tpc bit initial value read/write 0 r/w 7 nder7 0 r/w 6 nder6 0 r/w 5 nder5 0 r/w 4 nder4 0 r/w 3 nder3 0 r/w 2 nder2 0 r/w 1 nder1 0 r/w 0 nder0 next data enable 7 to 0 bits 7 to 0 nder7 to nder0 description tpc outputs tp 7 to tp 0 are disabled (ndr7 to ndr0 are not transferred to pa 7 to pa 0 ) tpc outputs tp 7 to tp 0 are enabled (ndr7 to ndr0 are transferred to pa 7 to pa 0 ) 0 1 appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 582 of 638 rej09b0395-0400 ndrb?next data register b h ' fffa4/h ' fffa6 tpc ? same trigger for tpc output groups 2 and 3 ? address h'fffa4 bit initial value read/write 0 r/w 7 ndr15 0 r/w 6 ndr14 0 r/w 5 ndr13 0 r/w 4 ndr12 0 r/w 3 ndr11 0 r/w 2 ndr10 0 r/w 1 ndr9 0 r/w 0 ndr8 store the next output data for tpc output g roup 3 store the next output data for tpc output g roup 2 ? address h'fffa6 1 ? 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 2 ? 1 ? 1 ? 1 ? 0 ? bit initial value read/write ? different triggers for tpc output groups 2 and 3 ? address h'fffa4 bit initial value read/write 0 r/w 7 ndr15 0 r/w 6 ndr14 0 r/w 5 ndr13 0 r/w 4 ndr12 1 ? 3 ? 1 ? 2 ? 1 ? 1 ? 1 ? 0 ? store the next output data for tpc output g roup 3 ? address h'fffa6 bit initial value read/write 0 r/w 7 ? 0 r/w 6 ? 0 r/w 5 ? 0 r/w 4 ? 3 ndr11 2 ndr10 1 ndr9 1 ? 1 ? 1 ? 1 ? 0 ndr8 store the next output data for tpc output g roup 2 appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 583 of 638 rej09b0395-0400 ndra?next data register a h ' fffa5/h ' fffa7 tpc ? same trigger for tpc output groups 0 and 1 ? address h'fffa5 bit initial value read/write 0 r/w 7 ndr7 0 r/w 6 ndr6 0 r/w 5 ndr5 0 r/w 4 ndr4 0 r/w 3 ndr3 0 r/w 2 ndr2 0 r/w 1 ndr1 0 r/w 0 ndr0 store the next output data for tpc output g roup 1 store the next output data for tpc output g roup 0 ? address h'fffa7 1 ? 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 2 ? 1 ? 1 ? 1 ? 0 ? bit initial value read/write ? different triggers for tpc output groups 0 and 1 ? address h'fffa5 bit initial value read/write 0 r/w 7 ndr7 0 r/w 6 ndr6 0 r/w 5 ndr5 0 r/w 4 ndr4 1 ? 3 ? 1 ? 2 ? 1 ? 1 ? 1 ? 0 ? store the next output data for tpc output g roup 1 ? address h'fffa7 bit initial value read/write 0 r/w 7 ? 0 r/w 6 ? 0 r/w 5 ? 0 r/w 4 ? 3 ndr3 2 ndr2 1 ndr1 1 ? 1 ? 1 ? 1 ? 0 ndr0 store the next output data for tpc output g roup 0 appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 584 of 638 rej09b0395-0400 smr?serial mode register h ' fffb0 sci0 bit initial value read/write 0 r/w 7 c/ a 0 r/w 6 chr 0 r/w 5 pe 4 o/ e 0 r/w 0 r/w 3 stop 0 r/w 2 mp 0 r/w 1 cks1 clock select 1 and 0 0 bit 0 clock /4 clock /16 clock /64 clock 1 0 cks0 0 r/w multiprocessor mode 0 multiprocessor function disabled multiprocessor format selected 1 bit 1 clock source cks0 cks1 0 1 0 1 stop bit len g th 0 one stop bit two stop bits 1 parity mode 0 even parity odd parity 1 parity enable 0 parity bit is not added or checked parity bit is added and checked 1 gsm mode (for smart card interface) 0 tend fla g is set 12.5 etu * after start bit tend fla g is set 11.0 etu * after start bit 1 character len g th 0 8-bit data 7-bit data 1 communication mode (for serial communication interface) 0 asynchronous mode synchronous mode 1 note: * etu: elementary time unit (time required to transmit one bit) appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 585 of 638 rej09b0395-0400 brr?bit rate register h ' fffb1 sci0 bit initial value read/write 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 serial communication bit rate settin g appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 586 of 638 rej09b0395-0400 scr?serial control register h ' fffb2 sci0 bit initial value read/write 0 r/w 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 2 teie 0 r/w 1 cke1 0 r/w 0 cke0 clock enable 1 and 0 (for serial communication interface) bit 1 cke1 bit 0 cke0 asynchronous mode synchronous mode asynchronous mode synchronous mode asynchronous mode synchronous mode asynchronous mode synchronous mode 0 1 0 1 0 1 description transmit-end interrupt enable 0 1 transmit-end interrupt requests (tei) are disabled transmit-end interrupt requests (tei) are enabled receive interrupt enable 0 1 receive-data-full (rxi) and receive-error (eri) interrupt requests are disabled receive-data-full (rxi) and receive-error (eri) interrupt requests are enabled internal clock: sck pin available for g eneric i/o internal clock: sck pin used for serial clock output internal clock: sck pin used for clock output internal clock: sck pin used for serial clock output external clock: sck pin used for clock input external clock: sck pin used for serial clock input external clock: sck pin used for clock input external clock: sck pin used for serial clock input multiprocessor interrupt enable 0 1 multiprocessor interrupts are disabled (normal receive operation) multiprocessor interrupts are enabled receive enable 0 1 receivin g is disabled receivin g is enabled transmit enable 0 1 transmittin g is disabled transmittin g is enabled transmit interrupt enable 0 1 transmit-data-empty interrupt request (txi) is disabled transmit-data-empty interrupt request (txi) is enabled clock enable 1 and 0 (for smart card interface) smr gm bit 1 cke1 bit 0 cke0 0 0 1 0 1 0 1 0 1 0 1 description sck pin available for g eneric i/o sck pin used for clock output sck pin output fixed low sck pin used for clock output sck pin output fixed hi g h sck pin used for clock output appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 587 of 638 rej09b0395-0400 tdr?transmit data register h ' fffb3 sci0 bit initial value read/write 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 serial transmit data appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 588 of 638 rej09b0395-0400 ssr?serial status register h ' fffb4 sci0 bit initial value read/write 1 r/(w) * 7 tdre 0 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer/ers 0 r/(w) * 3 per 1 r 2 tend 0 r 1 mpb 0 r/w 0 mpbt transmit end (for serial communication interface) 0 multiprocessor bit transfer 0 1 multiprocessor bit value in transmit data is 0 multiprocessor bit value in transmit data is 1 multiprocessor bit 0 1 multiprocessor bit value in receive data is 0 multiprocessor bit value in receive data is 1 [clearin g condition] read tdre when tdre = 1, then write 0 in tdre. [settin g conditions] ? reset or transition to standby mode ? te is cleared to 0 in scr. ? tdre is 1 when last bit of 1-byte serial character is transmitted. parity error 0 1 [clearin g conditions] ? reset or transition to standby mode ? read per when per = 1, then write 0 in per. [settin g condition] parity error (parity of receive data does not match parity settin g of o/ e bit in smr) framin g error (for serial communication interface) 0 [clearin g conditions] ? reset or transition to standby mode ? read fer when fer = 1, then write 0 in fer. [settin g condition] framin g error (stop bit is 0) error si g nal status (for smart card interface) 0 [clearin g conditions] ? reset or transition to standby mode ? read ers when ers = 1, then write 0 in ers. [settin g condition] a low error si g nal is received. 1 1 overrun error 0 [clearin g conditions] ? reset or transition to standby mode ? read orer when orer = 1, then write 0 in orer. [settin g condition] overrun error (reception of the next serial data ends when rdrf = 1) 1 receive data re g ister full 0 [clearin g conditions] ? reset or transition to standby mode ? read rdrf when rdrf = 1, then write 0 in rdrf. [settin g condition] serial data is received normally and transferred from rsr to rdr. 1 transmit data re g ister empty note: * only 0 can be written, to clear the fla g . 0 [clearin g condition] read tdre when tdre = 1, then write 0 in tdre. [settin g conditions] ? reset or transition to standby mode ? te is 0 in scr. ? data is transferred from tdr to tsr, enablin g new data to be written in tdr 1 1 transmit end (for smart card interface) 0 [clearin g condition] read tdre when tdre = 1, then write 0 in tdre. [settin g conditions] ? reset or transition to standby mode ? te is cleared to 0 in scr and fer/ers is cleared to 0. ? tdre is 1 and fer/ers is 0 (normal transmission) 2.5 etu * (when gm = 0) or 1.0 etu (when gm = 1) after 1-byte serial character is transmitted. 1 note: * etu: elementary time unit (time required to transmit one bit) appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 589 of 638 rej09b0395-0400 rdr?receive data register h ' fffb5 sci0 bit initial value read/write 0 r 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 0 r 0 serial receive data scmr?smart card mode register h ' fffb6 sci0 1 ? 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 0 r/w 3 sdir 0 r/w 2 sinv 1 ? 1 ? 0 r/w 0 smif smart card interface mode select 0 1 smart card interface function is disabled smart card interface function is enabled (initial value) smart card data invert 0 1 unmodified tdr contents are transmitted receive data is stored unmodified in rdr (initial value) inverted 1/0 lo g ic levels of tdr contents are transmitted 1/0 lo g ic levels of received data are inverted before stora g e in rdr smart card data transfer direction 0 1 tdr contents are transmitted lsb-first receive data is stored lsb-first in rdr (initial value) tdr contents are transmitted msb-first receive data is stored msb-first in rdr bit initial value read/write appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 590 of 638 rej09b0395-0400 smr?serial mode register h ' fffb8 sci1 0 r/w 7 c/ a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 2 mp 0 r/w 1 cks1 0 r/w 0 cks0 note: bit functions are the same as for sci0. bit initial value read/write brr?bit rate register h ' fffb9 sci1 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 note: bit functions are the same as for sci0. bit initial value read/write scr?serial control register h ' fffba sci1 0 r/w 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 2 teie 0 r/w 1 cke1 0 r/w 0 cke0 note: bit functions are the same as for sci0. bit initial value read/write tdr?transmit data register h ' fffbb sci1 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 bit initial value read/write note: bit functions are the same as for sci0. appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 591 of 638 rej09b0395-0400 ssr?serial status register h ' fffbc sci1 0 r/(w) * 7 tdre 0 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer/ers 0 r/(w) * 3 per 1 r 2 tend 0 r 1 mpb 0 r/w 0 mpbt bit initial value read/write notes: bit functions are the same as for sci0. * only 0 can be written to clear the fla g . rdr?receive data register h ' fffbd sci1 0 r 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 0 r 0 bit initial value read/write note: bit functions are the same as for sci0. scmr?smart card mode register h ' fffbe sci1 0 r/w 7 ? 0 r/w 6 ? 1 ? 5 ? 0 r/w 4 ? 3 sdir 2 sinv 1 ? 1 ? 1 ? 1 ? 1 ? 0 smif bit initial value read/write note: bit functions are the same as for sci0. p4dr?port 4 data register h ' fffd3 port 4 0 r/w 7 p4 7 0 r/w 6 p4 6 0 r/w 5 p4 5 0 r/w 4 p4 4 0 r/w 3 p4 3 0 r/w 2 p4 2 0 r/w 1 p4 1 0 r/w 0 p4 0 data for port 4 pins bit initial value read/write appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 592 of 638 rej09b0395-0400 p6dr?port 6 data register h ' fffd5 port 6 1 r 7 p6 7 0 r/w 6 p6 6 0 r/w 5 p6 5 0 r/w 4 p6 4 0 r/w 3 p6 3 0 r/w 2 p6 2 0 r/w 1 p6 1 0 r/w 0 p6 0 data for port 6 pins bit initial value read/write p7dr?port 7 data register h ' fffd6 port 7 ? r 7 p7 7 ? r 6 p7 6 ? r 5 p7 5 ? r 4 p7 4 ? r 3 p7 3 ? r 2 p7 2 ? r 1 p7 1 ? r 0 p7 0 data for port 7 pins * * * * * * * * note: * determined by pins p7 7 to p7 0 . bit initial value read/write p8dr?port 8 data register h ' fffd7 port 8 1 ? 7 ? 1 ? 6 ? 1 ? 5 ? 0 r/w 4 p8 4 0 r/w 3 p8 3 0 r/w 2 p8 2 0 r/w 1 p8 1 0 r/w 0 p8 0 data for port 8 pins bit initial value read/write p9dr?port 9 data register h ' fffd8 port 9 1 ? 7 ? 1 ? 6 ? 0 r/w 5 p9 5 0 r/w 4 p9 4 0 r/w 3 p9 3 0 r/w 2 p9 2 0 r/w 1 p9 1 0 r/w 0 p9 0 data for port 9 pins bit initial value read/write appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 593 of 638 rej09b0395-0400 padr?port a data register h ' fffd9 port a 0 r/w 7 pa 7 0 r/w 6 pa 6 0 r/w 5 pa 5 0 r/w 4 pa 4 0 r/w 3 pa 3 0 r/w 2 pa 2 0 r/w 1 pa 1 0 r/w 0 pa 0 data for port a pins bit initial value read/write pbdr?port b data register h ' fffda port b 0 r/w 7 pb 7 0 r/w 6 pb 6 0 r/w 5 pb 5 0 r/w 4 pb 4 0 r/w 3 pb 3 0 r/w 2 pb 2 0 r/w 1 pb 1 0 r/w 0 pb 0 data for port b pins bit initial value read/write appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 594 of 638 rej09b0395-0400 addra h/l?a/d data register a h/l h ' fffe0, h ' fffe1 a/d 0 r 15 ad9 a/d conversion data 10-bit data giving an a/d conversion result 0 r 14 ad8 0 r 13 ad7 0 r 12 ad6 0 r 11 ad5 0 r 10 ad4 0 r 9 ad3 0 r 8 ad2 0 r 7 ad1 0 r 6 ad0 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ? 0 r 1 ? 0 r 0 ? addrah addral bit initial value read/write addrb h/l?a/d data register b h/l h ' fffe2, h ' fffe3 a/d 0 r 15 ad9 0 r 14 ad8 0 r 13 ad7 0 r 12 ad6 0 r 11 ad5 0 r 10 ad4 0 r 9 ad3 0 r 8 ad2 0 r 7 ad1 0 r 6 ad0 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ? 0 r 1 ? 0 r 0 ? addrbh addrbl a/d c onversion data 10-bit data g ivin g an a/d conversion result bit initial value read/write addrc h/l?a/d data register c h/l h ' fffe4, h ' fffe5 a/d 0 r 15 ad9 0 r 14 ad8 0 r 13 ad7 0 r 12 ad6 0 r 11 ad5 0 r 10 ad4 0 r 9 ad3 0 r 8 ad2 0 r 7 ad1 0 r 6 ad0 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ? 0 r 1 ? 0 r 0 ? addrch addrcl a/d c onversion data 10-bit data g ivin g an a/d conversion result bit initial value read/write appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 595 of 638 rej09b0395-0400 addrd h/l?a/d data register d h/l h ' fffe6, h ' fffe7 a/d 0 r 15 ad9 0 r 14 ad8 0 r 13 ad7 0 r 12 ad6 0 r 11 ad5 0 r 10 ad4 0 r 9 ad3 0 r 8 ad2 0 r 7 ad1 0 r 6 ad0 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ? 0 r 1 ? 0 r 0 ? addrdh addrdl a/d c onversion data 10-bit data g ivin g an a/d conversion result bit initial value read/write adcr?a/d control register h ' fffe9 a/d 0 r/w 7 trge ? 1 ? ? 1 ? ? 1 ? ? 1 ? ? 1 ? ? 1 ? ? 65 432 1 0 r/w 0 tri gg er enable 0 1 a/d conversion start by external tri gg er or 8-bit timer compare match is disabled a/d conversion is started by fallin g ed g e of external tri gg er si g nal ( adtrg ) or 8-bit timer compare match bit initial value read/write appendix b internal i/o registers rev.4.00 aug. 20, 2007 page 596 of 638 rej09b0395-0400 adcsr?a/d control/status register h ' fffe8 a/d 0 r/(w) * 7 adf 0 r/w 6 adie 0 r/w 5 adst 0 r/w 4 scan 0 r/w 3 cks 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w 0 ch0 channel select 2 to 0 group selection 0 1 0 1 an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 0 ch2 1 0 1 0 1 0 1 0 1 description sin g le mode scan mode clock select 0 1 conversion time = 134 states (maximum) conversion time = 70 states (maximum) channel selection ch1 ch0 an 0 an 0, an 1 an 0 to an 2 an 0 to an 3 an 4 an 4, an 5 an 4 to an 6 an 4 to an 7 scan mode 0 1 sin g le mode scan mode a/d start 0 1 a/d conversion is stopped 1. sin g le mode: a/d conversion starts; adst is automatically cleared to 0 when conversion ends 2. scan mode: a/d conversion starts and continues, cyclin g amon g the selected channels adst is cleared to 0 by software, by a reset, or by a transition to standby mode a/d interrupt enable 0 1 a/d end interrupt request is disabled a/d end interrupt request is enabled a/d end fla g 0 [clearin g condition] read adf when adf = 1, then write 0 in adf [settin g conditions] ? sin g le mode: a/d conversion ends ? scan mode: a/d conversion ends in all selected channels 1 note: * only 0 can be written to clear the fla g . bit initial value read/write appendix c i/o port block diagrams rev.4.00 aug. 20, 2007 page 597 of 638 rej09b0395-0400 appendix c i/o port block diagrams c.1 port 4 block diagram p4 n rp4p rp4 wp4 wp4d wp4p reset reset reset qd r c p4 pcr n qd r c p4 ddr n qd r c p4 dr n le g end: wp4p: rp4p: wp4d: wp4: rp4: write to p4pcr read p4pcr write to p4ddr write to port 4 read port 4 note: n = 0 to 7 write to external address hardware standby external bus released read external address internal data bus (upper) internal data bus (lower) 8-bit bus mode 16-bit bus mode figure c.1 port 4 block diagram appendix c i/o port block diagrams rev.4.00 aug. 20, 2007 page 598 of 638 rej09b0395-0400 c.2 port 6 block diagrams le g end: wp6d: wp6: rp6: write to p6ddr write to port 6 read port 6 rp6 input wp6d reset qd r c p6 ddr 0 wp6 reset qd r c p6 dr 0 p6 0 internal data bus bus controller wait input enable bus controller wait hardware standby figure c.2 (a) port 6 block diagram (pin p6 0 ) appendix c i/o port block diagrams rev.4.00 aug. 20, 2007 page 599 of 638 rej09b0395-0400 p6 1 le g end: wp6d: wp6: rp6: write to p6ddr write to port 6 read port 6 wp6d reset qd r c p6 ddr 1 wp6 reset qd r c p6 dr 1 rp6 internal data bus bus controller bus release enable breq input hardware standby figure c.2 (b) port 6 block diagram (pin p6 1 ) appendix c i/o port block diagrams rev.4.00 aug. 20, 2007 page 600 of 638 rej09b0395-0400 wp6d reset hardware standby qd r c p6 ddr 2 wp6 reset qd r c p6 dr 2 rp6 p6 2 le g end: wp6d: wp6: rp6: write to p6ddr write to port 6 read port 6 internal data bus bus controller bus release enable back output figure c.2 (c) port 6 block diagram (pin p6 2 ) appendix c i/o port block diagrams rev.4.00 aug. 20, 2007 page 601 of 638 rej09b0395-0400 read port 6 le g end: rp6: hardware standby rp6 p6 7 output output enable internal data bus figure c.2 (d) port 6 block diagram (pin p6 7 ) appendix c i/o port block diagrams rev.4.00 aug. 20, 2007 page 602 of 638 rej09b0395-0400 c.3 port 7 block diagrams p7 n rp7 internal data bus a/d converter input enable channel select si g nal analo g input le g end: rp7: read port 7 note: n = 0 to 5 figure c.3 (a) port 7 block diagram (pins p7 0 to p7 5 ) p7 n rp7 le g end: rp7: read port 7 note: n = 6, 7 internal data bus d/a converter analo g output output enable a/d converter input enable channel select si g nal analo g input figure c.3 (b) port 7 block diagram (pins p7 6 and p7 7 ) appendix c i/o port block diagrams rev.4.00 aug. 20, 2007 page 603 of 638 rej09b0395-0400 c.4 port 8 block diagrams p8 0 rp8 wp8d reset qd r c p8 ddr 0 wp8 reset qd r c p8 dr 0 le g end: wp8d: wp8: rp8: write to p8ddr write to port 8 read port 8 internal data bus interrupt controller input irq 0 figure c.4 (a) port 8 block diagram (pin p8 0 ) appendix c i/o port block diagrams rev.4.00 aug. 20, 2007 page 604 of 638 rej09b0395-0400 p8 n wp8d reset qd r c p8 ddr n wp8 reset qd r c p8 dr n rp8 le g end: wp8d: wp8: rp8: ssoe: note: n = 1, 2 write to p8ddr write to port 8 read port 8 software standby output port enable internal data bus bus controller output interrupt controller irq irq cs cs 2 3 1 2 input ssoe software standby external bus released hardware standby figure c.4 (b) port 8 block diagram (pins p8 1 and p8 2 ) appendix c i/o port block diagrams rev.4.00 aug. 20, 2007 page 605 of 638 rej09b0395-0400 a/d converter wp8d p8 3 dr c qd write to p8ddr write to port 8 read port 8 software standby output port enable le g end: wp8d: wp8: rp8: ssoe: wp8 r reset internal data bus rp8 p8 3 bus controller cs 1 output reset interrupt controller irq 3 input adtrg input p8 3 ddr c qd r ssoe software standby external bus released hardware standby figure c.4 (c) port 8 block diagram (pin p8 3 ) appendix c i/o port block diagrams rev.4.00 aug. 20, 2007 page 606 of 638 rej09b0395-0400 p8 4 wp8d qd c p8 ddr 4 wp8 reset qd r c p8 dr 4 rp8 le g end: wp8d: wp8: rp8: ssoe: write to p8ddr write to port 8 read port 8 software standby output port enable internal data bus bus controller output 0 cs ssoe software standby external bus released hardware standby reset r figure c.4 (d) port 8 block diagram (pin p8 4 ) appendix c i/o port block diagrams rev.4.00 aug. 20, 2007 page 607 of 638 rej09b0395-0400 c.5 port 9 block diagrams le g end: wp9d: wp9: rp9: write to p9ddr write to port 9 read port 9 p9 0 rp9 wp9d reset hardware standby qd r c p9 ddr 0 wp9 reset qd r c p9 dr 0 internal data bus sci output enable serial transmit data guard time figure c.5 (a) port 9 block diagram (pin p9 0 ) appendix c i/o port block diagrams rev.4.00 aug. 20, 2007 page 608 of 638 rej09b0395-0400 le g end: wp9d: wp9: rp9: write to p9ddr write to port 9 read port 9 p9 1 rp9 wp9d reset qd r c p9 ddr 1 wp9 reset qd r c p9 dr 1 internal data bus sci output enable serial transmit data guard time hardware standby figure c.5 (b) port 9 block diagram (pin p9 1 ) appendix c i/o port block diagrams rev.4.00 aug. 20, 2007 page 609 of 638 rej09b0395-0400 le g end: wp9d: wp9: rp9: write to p9ddr write to port 9 read port 9 p9 2 wp9d reset qd r c p9 ddr 2 wp9 reset qd r c p9 dr 2 rp9 internal data bus input enable serial receive data sci hardware standby figure c.5 (c) port 9 block diagram (pin p9 2 ) appendix c i/o port block diagrams rev.4.00 aug. 20, 2007 page 610 of 638 rej09b0395-0400 p9 3 ddr c qd wp9d rp9 p9 3 dr c qd p9 3 serial receive data input enable write to p9ddr write to port 9 read port 9 le g end: wp9d: wp9: rp9: wp9 r r reset internal data bus reset sci hardware standby figure c.5 (d) port 9 block diagram (pin p9 3 ) appendix c i/o port block diagrams rev.4.00 aug. 20, 2007 page 611 of 638 rej09b0395-0400 le g end: wp9d: wp9: rp9: write to p9ddr write to port 9 read port 9 wp9d hardware standby reset qd r c p9 ddr 4 wp9 reset qd r c p9 dr 4 rp9 p9 4 internal data bus sci clock input enable clock output enable clock output clock input interrupt controller input irq 4 figure c.5 (e) port 9 block diagram (pin p9 4 ) appendix c i/o port block diagrams rev.4.00 aug. 20, 2007 page 612 of 638 rej09b0395-0400 r p9 5 ddr c qd reset wp9d wp9 rp9 r p9 5 dr c qd reset p9 5 sci clock input enable clock output enable clock output interrupt controller irq 5 input clock input write to p9ddr write to port 9 read port 9 le g end: wp9d: wp9: rp9: internal data bus hardware standby figure c.5 (f) port 9 block diagram (pin p9 5 ) appendix c i/o port block diagrams rev.4.00 aug. 20, 2007 page 613 of 638 rej09b0395-0400 c.6 port a block diagrams le g end: wpad: wpa: rpa: note: n = 0, 1 write to paddr write to port a read port a pa n wpad reset hardware standby qd r c pa ddr n reset qd r c pa d r n rpa wpa internal data bus tpc output enable tpc next data output tri gg er counter clock input 16-bit timer counter clock input 8-bit timer figure c.6 (a) port a block diagram (pins pa 0 and pa 1 ) appendix c i/o port block diagrams rev.4.00 aug. 20, 2007 page 614 of 638 rej09b0395-0400 le g end: wpad: wpa: rpa: note: n = 2, 3 write to paddr write to port a read port a pa n rpa wpa wpad reset qd r c pa ddr n reset qd r c pa dr n internal data bus tpc output enable tpc next data output tri gg er output enable compare match output input capture counter clock input 16-bit timer counter clock input 8-bit timer hardware standby figure c.6 (b) port a block diagram (pins pa 2 and pa 3 ) appendix c i/o port block diagrams rev.4.00 aug. 20, 2007 page 615 of 638 rej09b0395-0400 le g end: wpad: wpa: rpa: ssoe: note: n = 4 to 7 the pa 7 address output enable settin g is fixed at 1 in modes 3 and 4. write to paddr write to port a read port a software standby output port enable pa n wpad reset rpa wpa qd r c pa n ddr reset qd r c pa n dr internal address bus internal data bus tpc 16-bit timer tpc output enable next data output tri gg er output enable compare match output input capture software standby ssoe bus released modes 3 and 4 address output enable hardware standby figure c.6 (c) port a block diagram (pins pa 4 to pa 7 ) appendix c i/o port block diagrams rev.4.00 aug. 20, 2007 page 616 of 638 rej09b0395-0400 c.7 port b block diagrams pbn le g end: wpbd: wpb: rpb: ssoe: note: n = 0, 2 write to pbddr write to port b read port b software standby output port enable reset qd r c pb ddr n wpbd reset qd r c pb dr n wpb rpb internal data bus tpc output enable tpc next data output tri gg er output enable compare match output 8-bit timer bus released bus controller cs output enable cs7 cs5 output software standby hardware standby ssoe figure c.7 (a) port b block diagram (pins pb 0 and pb 2 ) appendix c i/o port block diagrams rev.4.00 aug. 20, 2007 page 617 of 638 rej09b0395-0400 r pb n ddr c qd reset wpbd wpb rpb r pb n dr c qd reset pb n tpc 8-bit timer tpc output enable bus controller cs output enable cs6 cs4 output next data output tri gg er output enable compare match output tmo2 tmo3 input write to pbddr write to port b read port b software standby output port enable le g end: wpbd: wpb: rpb: ssoe: note: n = 1, 3 bus released software standby ssoe internal data bus hardware standby figure c.7 (b) port b block diagram (pins pb 1 and pb 3 ) appendix c i/o port block diagrams rev.4.00 aug. 20, 2007 page 618 of 638 rej09b0395-0400 pb 4 le g end: wpbd: wpb: rpb: write to pbddr write to port b read port b wpb rpb reset qd r c pb ddr hardware standby 4 wpbd reset qd r c pb dr 4 internal data bus tpc output enable next data output tri gg er tpc figure c.7 (c) port b block diagram (pin pb 4 ) appendix c i/o port block diagrams rev.4.00 aug. 20, 2007 page 619 of 638 rej09b0395-0400 r pb 5 ddr c qd reset wpbd wpb rpb r pb 5 dr c qd reset pb 5 tpc tpc output enable next data output tri gg er write to pbddr write to port b read port b le g end: wpbd: wpb: rpb: internal data bus hardware standby figure c.7 (d) port b block diagram (pin pb 5 ) appendix c i/o port block diagrams rev.4.00 aug. 20, 2007 page 620 of 638 rej09b0395-0400 wpbd reset reset qd r c pb ddr qd r c pb dr 6 rpb wpb tpc le g end: wpbd: wpb: rpb: write to pbddr write to port b read port b tpc output enable next data output tri gg er internal data bus 6 pb 6 hardware standby figure c.7 (e) port b block diagram (pin pb 6 ) appendix c i/o port block diagrams rev.4.00 aug. 20, 2007 page 621 of 638 rej09b0395-0400 pb 7 wpbd reset reset qd r c pb ddr qd r c pb dr 7 rpb wpb tpc le g end: wpbd: wpb: rpb: write to pbddr write to port b read port b tpc output enable next data output tri gg er internal data bus 7 hardware standby figure c.7 (f) port b block diagram (pin pb 7 ) appendix d pin states rev.4.00 aug. 20, 2007 page 622 of 638 rej09b0395-0400 appendix d pin states d.1 port states in each mode table d.1 port states pin name mode reset hardware standby mode software standby mode bus- released mode program execution mode a 7 to a 0 ? l t (ssoe = 0) t (ssoe = 1) keep t a 7 to a 0 a 15 to a 8 ? l t (ssoe = 0) t (ssoe = 1) keep t a 15 to a 8 d 15 to d 8 ? t t t t d 15 to d 8 p4 7 to p4 0 1, 3 t t keep keep i/o port 2, 4 t t t t d 7 to d 0 a 19 to a 16 ? l t (ssoe = 0) t (ssoe = 1) keep t a 19 to a 16 p6 0 ? t t keep keep i/o port wait p6 1 ? t t (brle = 0) keep (brle = 1) t t i/o port breq p6 2 ? t t (brle = 0) keep (brle = 1) h l (brle = 0) i/o port (brle = 1) back as , rd , hwr , lwr ? h t (ssoe = 0) t (ssoe = 1) h t as , rd , hwr , lwr p6 7 ? clock output t (pstop = 0) h (pstop = 1) keep (pstop = 0) (pstop = 1) keep (pstop = 0) (pstop = 1) input port appendix d pin states rev.4.00 aug. 20, 2007 page 623 of 638 rej09b0395-0400 pin name mode reset hardware standby mode software standby mode bus- released mode program execution mode p7 7 to p7 0 ? t t t t input port p8 0 ? t t keep ? i/o port p8 1 ? t t (ddr = 0) t (ddr = 1, ssoe = 0) t (ddr = 1, ssoe = 1) h (ddr = 0) keep (ddr = 1) t (ddr = 0) input port (ddr = 1) cs 3 p8 2 ? t t (ddr = 0) t (ddr = 1, ssoe = 0) t (ddr = 1, ssoe = 1) h (ddr = 0) keep (ddr = 1) t (ddr = 0) input port (ddr = 1) cs 2 p8 3 ? t t (ddr = 0) t (ddr = 1, ssoe = 0) t (ddr = 1, ssoe = 1) h (ddr = 0) keep (ddr = 1) t (ddr = 0) input port (ddr = 1) cs 1 p8 4 ? h t (ddr = 0) t (ddr = 1, ssoe = 0) t (ddr = 1, ssoe = 1) h (ddr = 0) keep (ddr = 1) t (ddr = 0) input port (ddr = 1) cs 0 p9 5 to p9 0 ? t t keep keep i/o port pa 3 to pa 0 ? t t keep keep i/o port pa 6 to pa 4 1, 2 t t keep keep i/o port 3, 4 t t (address output) * 1 (ssoe = 0) t (ssoe = 1) keep (otherwise) * 2 keep (address output) * 1 t (otherwise) * 2 keep (address output) * 1 a 23 to a 21 (otherwise) * 2 i/o port appendix d pin states rev.4.00 aug. 20, 2007 page 624 of 638 rej09b0395-0400 pin name mode reset hardware standby mode software standby mode bus- released mode program execution mode pa 7 1, 2 t t keep keep i/o port 3, 4 l t (ssoe = 0) t (ssoe = 1) keep t a 20 pb 3 to pb 0 ? t t (cs output) * 3 (ssoe = 0) t (ssoe = 1) h (otherwise) * 4 keep (cs output) * 3 t (otherwise) * 4 keep (cs output) * 3 cs 7 to cs 4 (otherwise) * 4 i/o port pb 7 to pb 4 ? t t keep keep i/o port legend: h: high l: low t: high-impedance state keep: input pins are in the high-impedance state; output pins maintain their previous state. ddr: data direction register notes: 1. when a23e, a22e, a21e = 0 in brcr (bus release control register). 2. when a23e, a22e, a21e = 1 in brcr (bus release control register). 3. when cs7e, cs6e, cs5e, cs4e = 1 in cscr (chip select control register). 4. when cs7e, cs6e, cs5e, cs4e = 0 in cscr (chip select control register). appendix d pin states rev.4.00 aug. 20, 2007 page 625 of 638 rej09b0395-0400 d.2 pin states at reset modes 1 and 2: figure d.1 is a timing diagram for the case in which res goes low during an external memory access in mode 1 or 2. as soon as res goes low, all ports are initialized to the input state. as , rd , hwr , lwr , and cs 0 go high, and d 15 to d 0 go to the high-impedance state. the address bus is initialized to the low output level 2.5 clock cycles after the low level of res is sampled. clock pin p6 7 / goes to the output state at the next rise of after res goes low. as , rd (read) d 15 to d 0 (write) hwr , lwr (write) internal reset signal res p6 7 / i/o port, cs 7 to cs 1 cs 0 a 19 to a 0 t 1 t 2 t 3 access to external memory h'00000 high impedance high impedance figure d.1 reset during memory access (modes 1 and 2) appendix d pin states rev.4.00 aug. 20, 2007 page 626 of 638 rej09b0395-0400 modes 3 and 4: figure d.2 is a timing diagram for the case in which res goes low during an external memory access in mode 3 or 4. as soon as res goes low, all ports are initialized to the input state. as , rd , hwr , lwr , and cs 0 go high, and d 15 to d 0 go to the high-impedance state. the address bus is initialized to the low output level 2.5 clock cycles after the low level of res is sampled. however, when pa 4 to pa 6 are used as address bus pins, or when p8 3 to p8 1 and pb 0 to pb 3 are used as cs output pins, they go to th e high-impedance state at the same time as res goes low. clock pin p6 7 / goes to the output state at the next rise of after res goes low. t 1 t 2 t 3 access to external memory h'00000 high impedance high impedance as , rd (read) d 15 to d 0 (write) hwr , lwr (write) internal reset signal res p6 7 / i/o port, pa 4 /a 23 to pa 6 /a 21 , cs 7 to cs 1 cs 0 a 20 to a 0 figure d.2 reset during memory access (modes 3 and 4) appendix e timing of transition to and recovery from hardware standby mode rev.4.00 aug. 20, 2007 page 627 of 638 rej09b0395-0400 appendix e timing of transition to and recovery from hardware standby mode timing of transition to hardware standby mode 1. to retain ram contents with the rame bit set to 1 in syscr, drive the res signal low 10 system clock cycles before the stby signal goes low, as shown below. res must remain low until stby goes low (minimum delay from stby low to res high: 0 ns). t 1 10t cyc t 2 0 ns stby res 2. to retain ram contents with the rame bit cleared to 0 in syscr, res does not have to be driven low as in (1). timing of recovery from hardware standby mode: drive the res signal low approximately 100 ns before stby goes high. stby res t 100 ns t osc appendix f product code lineup rev.4.00 aug. 20, 2007 page 628 of 638 rej09b0395-0400 appendix f product code lineup table f.1 h8/3008 product code lineup product type product code mark code package (package code) h8/3008 romless 5 v hd6413008f hd6413008f 100-pin qfp (fp-100b) hd6413008te hd6413008te 100-pin tqfp (tfp-100b) 3 v hd6413008vf hd6413008vf 100-pin qfp (fp-100b) hd6413008vte hd6413008vte 100-pin tqfp (tfp-100b) appendix g package dimensions rev.4.00 aug. 20, 2007 page 629 of 638 rej09b0395-0400 appendix g package dimensions figure g.1 shows the fp-100b package dimensions of the h8/3008. figure g.2 shows the tfp- 100b package dimensions. note) 1. dimensions" * 1"and" * 2" do not include mold flash 2. dimension" * 3"does not include trim offset. * 1 * 2 * 3 p e d e d f 100 125 26 76 75 51 50 xm y z z d h e h b terminal cross section p 1 1 c b c b 2 1 1 detail f c a a l l a 1.0 1.0 0.08 0.10 0.5 8 0 0.25 0.12 0.15 0.20 0.00 0.27 0.22 0.17 0.22 0.17 0.12 3.05 16.3 16.0 15.7 l 1 z e z d y x c b 1 b p a h d a 2 e d a 1 c 1 e e l h e 0.7 0.5 0.3 max nom min dimension in millimeters symbol reference 14 2.70 16.3 16.0 15.7 1.0 14 p-qfp100-14x14-0.50 1.2g mass[typ.] fp-100b/fp-100bv prqp0100ka-a renesas code jeita package code previous code figure g.1 package dimensions (fp-100b) appendix g package dimensions rev.4.00 aug. 20, 2007 page 630 of 638 rej09b0395-0400 note) 1. dimensions" * 1"and" * 2" do not include mold flash 2. dimension" * 3"does not include trim offset. 1.00 1.00 0.08 0.10 0.5 8 0 15.8 16.0 16.2 0.15 0.20 1.20 0.20 0.10 0.00 0.27 0.22 0.17 0.22 0.17 0.12 l 1 z e z d y x c b 1 b p a h d a 2 e d a 1 c 1 e e l h e 0.6 0.5 0.4 max nom min dimension in millimeters symbol reference 14 1.00 16.2 16.0 15.8 1.0 14 index mark * 1 * 2 * 3 p e d e d 100 1 f xm y 26 25 76 75 50 51 z z h e h d b 2 1 1 detail f c l a a a l terminal cross section p 1 1 b c b c p-tqfp100-14x14-0.50 0.5g mass[typ.] tfp-100b/tfp-100bv ptqp0100ka-a renesas code jeita package code previous code figure g.2 package dimensions (tfp-100b) appendix h comparison of h8/300h series product specifications rev.4.00 aug. 20, 2007 page 631 of 638 rej09b0395-0400 appendix h comparison of h8/300h series product specifications h.1 differences between h8/3067 and h8/3062 group, h8/3048 group, h8/3006 and h8/3007, and h8/3008 item h8/3067 group, h8/3062 group h8/3048 group h8/3006, h8/3007 h8/3008 1 operating mode mode 5 16 mbyte rom enabled expanded mode 1 mbyte rom enabled expanded mode mode 6 64 kbyte single-chip mode 16 mbyte rom enabled expanded mode 2 interrupt controller internal interrupt sources 36 (h8/3067) 27 (h8/3062 group) 30 36 27 3 bus controller burst rom interface yes (h8/3067) no (h8/3062 group) no yes no idle cycle insertion function yes no yes yes wait mode 2 modes 4 modes 2 modes 2 modes wait state number setting per area common to all areas per area per area address output method choice of address update mode (fixed in h8/3067f-ztat and h8/3062f-ztat) fixed fixed choice of address update mode 4 dram interface connectable areas area 2/3/4/5 (h8/3067 only) area 3 area 2/3/4/5 no precharge cycle insertion function yes (h8/3067 only) no yes no fast page mode yes (h8/3067 only) no yes no address shift amount 8 bit/9 bit/10 bit (h8/3067 only) 8 bit/9 bit 8 bit/9 bit/10 bit no appendix h comparison of h8/300h series product specifications rev.4.00 aug. 20, 2007 page 632 of 638 rej09b0395-0400 item h8/3067 group, h8/3062 group h8/3048 group h8/3006, h8/3007 h8/3008 5 timer functions 16-bit timers 8-bit timers itu 16-bit timers 8-bit timers 16-bit timers 8-bit timers number of channels 16 bits 38 bits 4 (16 bits 2) 16 bits 5 16 bits 38 bits 4 (16 bits 2) 16 bits 3 8 bits 4 (16 bits 2) pulse output 6 pins 4 pins (2 pins) 12 pins 6 pins 4 pins (2 pins) 6 pins 4 pins (2 pins) input capture 6 2 10 6 2 6 2 external clock 4 systems (selec- table) 4 systems (fixed) 4 systems (selec- table) 4 systems (selec- table) 4 systems (fixed) 4 systems (selec- table) 4 systems (fixed) internal clock , /2, /4, /8 /8, /64, /8192 , /2, /4, /8 , /2, /4, /8 /8, /64, /8192 , /2, /4, /8 /8, /64, /8192 comple- mentary pwm function no no yes no no no no reset- synchronous pwm function no no yes no no no no buffer operation no no yes no no no no output initialization function yes no no yes no yes no pwm output 3 4 (2) 5 3 4 (2) 3 4 (2) dmac activation 3 channels (h8/3067 only) no 4 channels 3 channels no no a/d conversion activation no yes no no yes yes interrupt sources 3 sources 3 8 sources 3 sources 5 3 sources 3 8 sources 8 sources 6 tpc time base 3 kinds, 16-bit timer base 4 kinds, itu base 3 kinds, 16-bit timer base 3 kinds, 16-bit timer base 7 wdt reset signal external output function yes (except products with on-chip flash memory) yes yes yes appendix h comparison of h8/300h series product specifications rev.4.00 aug. 20, 2007 page 633 of 638 rej09b0395-0400 item h8/3067 group, h8/3062 group h8/3048 group h8/3006, h8/3007 h8/3008 8 sci number of channels 3 channels (h8/3067) 2 channels (h8/3062 group) 2 channels 3 channels 2 channels smart card interface supported on all channels supported on sci0 only supported on all channels supported on all channels 9 a/d converter conversion start trigger input external trigger/8-bit timer compare match external trigger external trigger/8-bit timer compare match external trigger/8-bit timer compare match conversion states 70/134 134/266 70/134 70/134 10 pin control pin /input port multiplexing output only /input port multiplexing output/input port a 20 in 16 mb rom enabled expanded mode a 20 / i/o port multiplexing a 20 output address bus, as , rd , hwr , lwr , cs 7 ? cs 0 , rfsh in software standby state high-level output/high- impedance selectable ( rfsh : h8/3067 only) high-level output (except cs 0 ) low-level output ( cs 0 ) high-level output/high- impedance selectable high-level output/high- impedance selectable cs 7 ? cs 0 in bus-released state high-impedance high-level output high-impedance high-impedance 11 flash memory functions program/ erase voltage 12 v application unnecessary. single-power-supply programming. 12 v application from off- chip block divisions 8 blocks (12 blocks in h8/3064f-ztat b-mask version) 16 blocks appendix h comparison of h8/300h series product specifications rev.4.00 aug. 20, 2007 page 634 of 638 rej09b0395-0400 h.2 comparison of pin function s of 100-pin package products (fp-100b, tfp-100b) table h.1 pin arrangement of each product (fp-100b, tfp-100b) on-chip-rom products romless products pin no. h8/3067 group h8/3062 group h8/3048 group h8/3042 group h8/3006, h8/3007 h8/3008 1 v cc v cc /v cl * 2 v cc v cc v cc v cc /v cl * 2 2 pb 0 /tp 8 /tmo 0 / cs 7 pb 0 /tp 8 /tmo 0 / cs 7 pb 0 /tp 8 / tioca 3 pb 0 /tp 8 / tioca 3 pb 0 /tp 8 /tmo 0 / cs 7 pb 0 /tp 8 /tmo 0 / cs 7 3 pb 1 /tp 9 /tmio 1 / dreq 0 / cs 6 pb 1 /tp 9 /tmio 1 / cs 6 pb 1 /tp 9 / tiocb 3 pb 1 /tp 9 / tiocb 3 pb 1 /tp 9 /tmio 1 / dreq 0 / cs 6 pb 1 /tp 9 /tmio 1 / cs 6 4 pb 2 /tp 10 /tmo 2 / cs 5 pb 2 /tp 10 /tmo 2 / cs 5 pb 2 /tp 10 / tioca 4 pb 2 /tp 10 / tioca 4 pb 2 /tp 10 /tmo 2 / cs 5 pb 2 /tp 10 /tmo 2 / cs 5 5 pb 3 /tp 11 / tmio 3 / dreq 1 / cs 4 pb 3 /tp 11 / tmio 3 / cs 4 pb 3 /tp 11 / tiocb 4 pb 3 /tp 11 / tiocb 4 pb 3 /tp 11 / tmio 3 / dreq 1 / cs 4 pb 3 /tp 11 / tmio 3 / cs 4 6 pb 4 /tp 12 / ucas pb 4 /tp 12 pb 4 /tp 12 / tocxa 4 pb 4 /tp 12 / tocxa 4 pb 4 /tp 12 / ucas pb 4 /tp 12 7 pb 5 /tp 13 / lcas /sck 2 pb 5 /tp 13 pb 5 /tp 13 / tocxb 4 pb 5 /tp 13 / tocxb 4 pb 5 /tp 13 / lcas /sck 2 pb 5 /tp 13 8 pb 6 /tp 14 /txd 2 pb 6 /tp 14 pb 6 /tp 14 / dreq 0 / cs 7 pb 6 /tp 14 / dreq 0 pb 6 /tp 14 /txd 2 pb 6 /tp 14 9 pb 7 /tp 15 /rxd 2 pb 7 /tp 15 pb 7 /tp 15 / dreq 1 / adtrg pb 7 /tp 15 / dreq 1 / adtrg pb 7 /tp 15 /rxd 2 pb 7 /tp 15 10 reso /fwe * 1 reso /fwe * 1 reso /v pp reso reso nc/ reso 11 vss vss vss vss vss vss 12 p9 0 /txd 0 p9 0 /txd 0 p9 0 /txd 0 p9 0 /txd 0 p9 0 /txd 0 p9 0 /txd 0 13 p9 1 /txd 1 p9 1 /txd 1 p9 1 /txd 1 p9 1 /txd 1 p9 1 /txd 1 p9 1 /txd 1 14 p9 2 /rxd 0 p9 2 /rxd 0 p9 2 /rxd 0 p9 2 /rxd 0 p9 2 /rxd 0 p9 2 /rxd 0 15 p9 3 /rxd 1 p9 3 /rxd 1 p9 3 /rxd 1 p9 3 /rxd 1 p9 3 /rxd 1 p9 3 /rxd 1 16 p9 4 /sck 0 / irq 4 p9 4 /sck 0 / irq 4 p9 4 /sck 0 / irq 4 p9 4 /sck 0 / irq 4 p9 4 /sck 0 / irq 4 p9 4 /sck 0 / irq 4 17 p9 5 /sck 1 / irq 5 p9 5 /sck 1 / irq 5 p9 5 /sck 1 / irq 5 p9 5 /sck 1 / irq 5 p9 5 /sck 1 / irq 5 p9 5 /sck 1 / irq 5 18 p4 0 /d 0 p4 0 /d 0 p4 0 /d 0 p4 0 /d 0 p4 0 /d 0 p4 0 /d 0 19 p4 1 /d 1 p4 1 /d 1 p4 1 /d 1 p4 1 /d 1 p4 1 /d 1 p4 1 /d 1 20 p4 2 /d 2 p4 2 /d 2 p4 2 /d 2 p4 2 /d 2 p4 2 /d 2 p4 2 /d 2 21 p4 3 /d 3 p4 3 /d 3 p4 3 /d 3 p4 3 /d 3 p4 3 /d 3 p4 3 /d 3 22 vss vss vss vss vss vss 23 p4 4 /d 4 p4 4 /d 4 p4 4 /d 4 p4 4 /d 4 p4 4 /d 4 p4 4 /d 4 appendix h comparison of h8/300h series product specifications rev.4.00 aug. 20, 2007 page 635 of 638 rej09b0395-0400 on-chip-rom products romless products pin no. h8/3067 group h8/3062 group h8/3048 group h8/3042 group h8/3006, h8/3007 h8/3008 24 p4 5 /d 5 p4 5 /d 5 p4 5 /d 5 p4 5 /d 5 p4 5 /d 5 p4 5 /d 5 25 p4 6 /d 6 p4 6 /d 6 p4 6 /d 6 p4 6 /d 6 p4 6 /d 6 p4 6 /d 6 26 p4 7 /d 7 p4 7 /d 7 p4 7 /d 7 p4 7 /d 7 p4 7 /d 7 p4 7 /d 7 27 p3 0 /d 8 p3 0 /d 8 p3 0 /d 8 p3 0 /d 8 d 8 d 8 28 p3 1 /d 9 p3 1 /d 9 p3 1 /d 9 p3 1 /d 9 d 9 d 9 29 p3 2 /d 10 p3 2 /d 10 p3 2 /d 10 p3 2 /d 10 d 10 d 10 30 p3 3 /d 11 p3 3 /d 11 p3 3 /d 11 p3 3 /d 11 d 11 d 11 31 p3 4 /d 12 p3 4 /d 12 p3 4 /d 12 p3 4 /d 12 d 12 d 12 32 p3 5 /d 13 p3 5 /d 13 p3 5 /d 13 p3 5 /d 13 d 13 d 13 33 p3 6 /d 14 p3 6 /d 14 p3 6 /d 14 p3 6 /d 14 d 14 d 14 34 p3 7 /d 15 p3 7 /d 15 p3 7 /d 15 p3 7 /d 15 d 15 d 15 35 vcc vcc vcc vcc vcc vcc 36 p1 0 /a 0 p1 0 /a 0 p1 0 /a 0 p1 0 /a 0 a 0 a 0 37 p1 1 /a 1 p1 1 /a 1 p1 1 /a 1 p1 1 /a 1 a 1 a 1 38 p1 2 /a 2 p1 2 /a 2 p1 2 /a 2 p1 2 /a 2 a 2 a 2 39 p1 3 /a 3 p1 3 /a 3 p1 3 /a 3 p1 3 /a 3 a 3 a 3 40 p1 4 /a 4 p1 4 /a 4 p1 4 /a 4 p1 4 /a 4 a 4 a 4 41 p1 5 /a 5 p1 5 /a 5 p1 5 /a 5 p1 5 /a 5 a 5 a 5 42 p1 6 /a 6 p1 6 /a 6 p1 6 /a 6 p1 6 /a 6 a 6 a 6 43 p1 7 /a 7 p1 7 /a 7 p1 7 /a 7 p1 7 /a 7 a 7 a 7 44 vss vss vss vss vss vss 45 p2 0 /a 8 p2 0 /a 8 p2 0 /a 8 p2 0 /a 8 a 8 a 8 46 p2 1 /a 9 p2 1 /a 9 p2 1 /a 9 p2 1 /a 9 a 9 a 9 47 p2 2 /a 10 p2 2 /a 10 p2 2 /a 10 p2 2 /a 10 a 10 a 10 48 p2 3 /a 11 p2 3 /a 11 p2 3 /a 11 p2 3 /a 11 a 11 a 11 49 p2 4 /a 12 p2 4 /a 12 p2 4 /a 12 p2 4 /a 12 a 12 a 12 50 p2 5 /a 13 p2 5 /a 13 p2 5 /a 13 p2 5 /a 13 a 13 a 13 51 p2 6 /a 14 p2 6 /a 14 p2 6 /a 14 p2 6 /a 14 a 14 a 14 52 p2 7 /a 15 p2 7 /a 15 p2 7 /a 15 p2 7 /a 15 a 15 a 15 53 p5 0 /a 16 p5 0 /a 16 p5 0 /a 16 p5 0 /a 16 a 16 a 16 54 p5 1 /a 17 p5 1 /a 17 p5 1 /a 17 p5 1 /a 17 a 17 a 17 55 p5 2 /a 18 p5 2 /a 18 p5 2 /a 18 p5 2 /a 18 a 18 a 18 56 p5 3 /a 19 p5 3 /a 19 p5 3 /a 19 p5 3 /a 19 a 19 a 19 appendix h comparison of h8/300h series product specifications rev.4.00 aug. 20, 2007 page 636 of 638 rej09b0395-0400 on-chip-rom products romless products pin no. h8/3067 group h8/3062 group h8/3048 group h8/3042 group h8/3006, h8/3007 h8/3008 57 vss vss vss vss vss vss 58 p6 0 / wait p6 0 / wait p6 0 / wait p6 0 / wait p6 0 / wait p6 0 / wait 59 p6 1 / breq p6 1 / breq p6 1 / breq p6 1 / breq p6 1 / breq p6 1 / breq 60 p6 2 / back p6 2 / back p6 2 / back p6 2 / back p6 2 / back p6 2 / back 61 p6 7 / p6 7 / p6 7 / p6 7 / 62 stby stby stby stby stby stby 63 res res res res res res 64 nmi nmi nmi nmi nmi nmi 65 vss vss vss vss vss vss 66 extal extal extal extal extal extal 67 xtal xtal xtal xtal xtal xtal 68 vcc vcc vcc vcc vcc vcc 69 p6 3 / as p6 3 / as p6 3 / as p6 3 / as as as 70 p6 4 / rd p6 4 / rd p6 4 / rd p6 4 / rd rd rd 71 p6 5 / hwr p6 5 / hwr p6 5 / hwr p6 5 / hwr hwr hwr 72 p6 6 / lwr p6 6 / lwr p6 6 / lwr p6 6 / lwr lwr lwr 73 md 0 md 0 md 0 md 0 md 0 md 0 74 md 1 md 1 md 1 md 1 md 1 md 1 75 md 2 md 2 md 2 md 2 md 2 md 2 76 avcc avcc avcc avcc avcc avcc 77 v ref v ref v ref v ref v ref v ref 78 p7 0 /an 0 p7 0 /an 0 p7 0 /an 0 p7 0 /an 0 p7 0 /an 0 p7 0 /an 0 79 p7 1 /an 1 p7 1 /an 1 p7 1 /an 1 p7 1 /an 1 p7 1 /an 1 p7 1 /an 1 80 p7 2 /an 2 p7 2 /an 2 p7 2 /an 2 p7 2 /an 2 p7 2 /an 2 p7 2 /an 2 81 p7 3 /an 3 p7 3 /an 3 p7 3 /an 3 p7 3 /an 3 p7 3 /an 3 p7 3 /an 3 82 p7 4 /an 4 p7 4 /an 4 p7 4 /an 4 p7 4 /an 4 p7 4 /an 4 p7 4 /an 4 83 p7 5 /an 5 p7 5 /an 5 p7 5 /an 5 p7 5 /an 5 p7 5 /an 5 p7 5 /an 5 84 p7 6 /an 6 /da 0 p7 6 /an 6 /da 0 p7 6 /an 6 /da 0 p7 6 /an 6 /da 0 p7 6 /an 6 /da 0 p7 6 /an 6 /da 0 85 p7 7 /an 7 /da 1 p7 7 /an 7 /da 1 p7 7 /an 7 /da 1 p7 7 /an 7 /da 1 p7 7 /an 7 /da 1 p7 7 /an 7 /da 1 86 avss avss avss avss avss avss 87 p8 0 / rfsh / irq 0 p8 0 / irq 0 p8 0 / rfsh / irq 0 p8 0 / rfsh / irq 0 p8 0 / rfsh / irq 0 p8 0 / irq 0 88 p8 1 / cs 3 / irq 1 p8 1 / cs 3 / irq 1 p8 1 / cs 3 / irq 1 p8 1 / cs 3 / irq 1 p8 1 / cs 3 / irq 1 p8 1 / cs 3 / irq 1 89 p8 2 / cs 2 / irq 2 p8 2 / cs 2 / irq 2 p8 2 / cs 2 / irq 2 p8 2 / cs 2 / irq 2 p8 2 / cs 2 / irq 2 p8 2 / cs 2 / irq 2 appendix h comparison of h8/300h series product specifications rev.4.00 aug. 20, 2007 page 637 of 638 rej09b0395-0400 on-chip-rom products romless products pin no. h8/3067 group h8/3062 group h8/3048 group h8/3042 group h8/3006, h8/3007 h8/3008 90 p8 3 / cs 1 / irq 3 / adtrg p8 3 / cs 1 / irq 3 / adtrg p8 3 / cs 1 / irq 3 p8 3 / cs 1 / irq 3 p8 3 / cs 1 / irq 3 / adtrg p8 3 / cs 1 / irq 3 / adtrg 91 p8 4 / cs 0 p8 4 / cs 0 p8 4 / cs 0 p8 4 / cs 0 p8 4 / cs 0 p8 4 / cs 0 92 vss vss vss vss vss vss 93 pa 0 /tp 0 / tend 0 /tclka pa 0 /tp 0 /tclka pa 0 /tp 0 / tend 0 /tclka pa 0 /tp 0 / tend 0 /tclka pa 0 /tp 0 / tend 0 /tclka pa 0 /tp 0 / tclka 94 pa 1 /tp 1 / tend 1 /tclkb pa 1 /tp 1 /tclkb pa 1 /tp 1 / tend 1 /tclkb pa 1 /tp 1 / tend 1 /tclkb pa 1 /tp 1 / tend 1 /tclkb pa 1 /tp 1 / tclkb 95 pa 2 /tp 2 / tioca 0 /tclkc pa 2 /tp 2 / tioca 0 /tclkc pa 2 /tp 2 / tioca 0 /tclkc pa 2 /tp 2 / tioca 0 /tclkc pa 2 /tp 2 / tioca 0 /tclkc pa 2 /tp 2 / tioca 0 /tclkc 96 pa 3 /tp 3 / tiocb 0 /tclkd pa 3 /tp 3 / tiocb 0 /tclkd pa 3 /tp 3 / tiocb 0 /tclkd pa 3 /tp 3 / tiocb 0 /tclkd pa 3 /tp 3 / tiocb 0 /tclkd pa 3 /tp 3 / tiocb 0 /tclkd 97 pa 4 /tp 4 / tioca 1 /a 23 pa 4 /tp 4 / tioca 1 /a 23 pa 4 /tp 4 / tioca 1 / cs 6 /a 23 pa 4 /tp 4 / tioca 1 /a 23 pa 4 /tp 4 / tioca 1 /a 23 pa 4 /tp 4 / tioca 1 /a 23 98 pa 5 /tp 5 / tiocb 1 /a 22 pa 5 /tp 5 / tiocb 1 /a 22 pa 5 /tp 5 / tiocb 1 / cs 5 /a 22 pa 5 /tp 5 / tiocb 1 /a 22 pa 5 /tp 5 / tiocb 1 /a 22 pa 5 /tp 5 / tiocb 1 /a 22 99 pa 6 /tp 6 / tioca 2 /a 21 pa 6 /tp 6 / tioca 2 /a 21 pa 6 /tp 6 / tioca 2 / cs 4 /a 21 pa 6 /tp 6 / tioca 2 /a 21 pa 6 /tp 6 / tioca 2 /a 21 pa 6 /tp 6 / tioca 2 /a 21 100 pa 7 /tp 7 / tiocb 2 /a 20 pa 7 /tp 7 / tiocb 2 /a 20 pa 7 /tp 7 / tiocb 2 /a 20 pa 7 /tp 7 / tiocb 2 /a 20 pa 7 /tp 7 / tiocb 2 /a 20 pa 7 /tp 7 / tiocb 2 /a 20 notes: 1. functions as reso in the mask rom versions, and as fwe in the on-chip flash memory versions. 2. the 5 v operation models of the h8/3064f-ztat b-mask version and the h8/3062f- ztat b-mask version have a v cl pin, and require an external capacitor (0.1 f). appendix h comparison of h8/300h series product specifications rev.4.00 aug. 20, 2007 page 638 of 638 rej09b0395-0400 renesas 16-bit single-chip microcomputer hardware manual h8/3008 publication date: 1st edition, september 2000 rev.4.00, august 20, 2007 published by: sales strategic planning div. renesas technology corp. edited by: customer support department global strategic communication div. renesas solutions corp. ? 2007. renesas technology corp., all rights reserved. printed in japan. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology malaysia sdn. bhd unit 906, block b, menara amcorp, amcorp trade centre, no.18, jalan persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices colophon 6.0 h8/3008 rej09b0395-0400 hardware manual 1753, shimonumabe, nakahara-ku, kawasaki-shi, kanagawa 211-8668 japan |
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